JPH02168642A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02168642A JPH02168642A JP63324203A JP32420388A JPH02168642A JP H02168642 A JPH02168642 A JP H02168642A JP 63324203 A JP63324203 A JP 63324203A JP 32420388 A JP32420388 A JP 32420388A JP H02168642 A JPH02168642 A JP H02168642A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- integrated circuit
- semiconductor integrated
- circuit device
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 abstract description 20
- 238000005259 measurement Methods 0.000 abstract description 4
- 238000007689 inspection Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.
従来、半導体集積回路装置において、基板上に配線層を
形成する場合には、基板と配線層間に絶縁膜を形成して
いる。また、二層以上の配線層を形成する場合にも、配
線層相互間に絶縁膜を形成している。Conventionally, in a semiconductor integrated circuit device, when forming a wiring layer on a substrate, an insulating film is formed between the substrate and the wiring layer. Furthermore, even when two or more wiring layers are formed, an insulating film is formed between the wiring layers.
この絶縁膜には、製造条件の不適性により、ピンホール
の発生がしばしば見られる。Pinholes are often found in this insulating film due to unsuitable manufacturing conditions.
第２図にピンホールが発生している状態の示す。第２図
において、１は基板であり、３は第一の絶縁層であり、
５は第二の絶縁層である。２は第一の配線層３を絶縁す
る絶縁膜であり、４は第一および第二の配線層間の絶縁
膜である。第２図中央部に示されているのが、ピンホー
ルであり、第一および第二の配線層間を短絡させている
。FIG. 2 shows a state in which pinholes are generated. In FIG. 2, 1 is a substrate, 3 is a first insulating layer,
5 is a second insulating layer. 2 is an insulating film that insulates the first wiring layer 3, and 4 is an insulating film between the first and second wiring layers. What is shown in the center of FIG. 2 is a pinhole, which short-circuits the first and second wiring layers.
ピンホールにより短絡が発生すれば、機能検査で不良と
なるので問題は少ない。しかしながら、ピンホールのう
ち、小面積のものは、絶縁膜を極薄く残す場合が多い、
これは製造直後は良品であるが、短時間の動作の後に不
良となり、いわゆる初期故障として扱われる。If a short circuit occurs due to a pinhole, it is not a problem because it will fail in a functional test. However, pinholes with small areas often leave an extremely thin insulating film.
This is a good product immediately after manufacture, but becomes defective after a short period of operation, and is treated as a so-called initial failure.
また、ピンホールによる短絡が発生しても、オーミック
コンタクトが得られにくい材質の組合わせであれば、同
様に初期故障として発見される場合が多い。Further, even if a short circuit occurs due to a pinhole, if the combination of materials makes it difficult to obtain ohmic contact, it is often discovered as an initial failure.
このような初期故障を出荷前に発生させることにより、
フィールド故障率を下げるなめには、高温、高電圧等に
よる加速試験、エージング等が必要となる。By causing such initial failures before shipping,
In order to reduce the field failure rate, accelerated testing using high temperature and high voltage, aging, etc. are required.
本発明によれば、「層間絶縁膜と製造状態を認識するた
めの手段を有することを特徴とする半導体集積回路装置
」が得られる。According to the present invention, a "semiconductor integrated circuit device characterized by having an interlayer insulating film and means for recognizing the manufacturing state" is obtained.
次に、本発明の一実施例を示した図面を参照して、本発
明をより詳細に説明する。Next, the present invention will be described in more detail with reference to the drawings showing one embodiment of the present invention.
第１図を参照すると、配線層間に形成されている絶縁膜
の製造状態を認識するための配線層パターンが示されて
いる。第１図において、６は基板側にある第一配線層で
あり、７は上側にある第二の配線層である。８は第一の
配線層の接続用パッドであり、９は第二の配線層の接続
用パッドである。Referring to FIG. 1, a wiring layer pattern is shown for recognizing the manufacturing state of an insulating film formed between wiring layers. In FIG. 1, 6 is a first wiring layer on the substrate side, and 7 is a second wiring layer on the upper side. 8 is a connection pad for the first wiring layer, and 9 is a connection pad for the second wiring layer.
絶縁膜ピンホールの発生率は、半導体集積回路装置の製
造ロット内においてほぼ一定と見なし得る。らさに、各
々のピンホールの面積について考慮した場合、分布確率
は製造ロット内でほぼ均一と見なすことができる。した
がって、接続用パッド８および９の導電率を測定し、こ
の測定値を製造ロット内の複数のは動態集積回路装置に
ついて採取し、さらにこの測定値を統計的に処理するこ
とにより、眉間絶縁膜の製造状態を認識することができ
る。これにより、初期故障の発生が予測できる。The rate of occurrence of insulating film pinholes can be considered to be approximately constant within a production lot of semiconductor integrated circuit devices. Moreover, when considering the area of each pinhole, the distribution probability can be considered to be approximately uniform within a manufacturing lot. Therefore, by measuring the electrical conductivity of the connection pads 8 and 9, collecting these measured values for a plurality of dynamic integrated circuit devices in a manufacturing lot, and further statistically processing these measured values, it is possible to The manufacturing status of the product can be recognized. This makes it possible to predict the occurrence of initial failures.
オーミックコンタクトが得られない材質の場合であって
も、導電率の測定条件を！＆適化するすることにより、
測定は可能である。Conductivity measurement conditions even for materials where ohmic contact cannot be achieved! & By optimizing
Measurement is possible.
以上説明したように、本発明によれば、半導体集積回路
装置内部に眉間絶縁膜の製造状態を認識するための手段
を設けることにより、半導体集積回路装置の検査の著し
い容易さが得られる。As described above, according to the present invention, by providing a means for recognizing the manufacturing state of the glabellar insulating film inside the semiconductor integrated circuit device, inspection of the semiconductor integrated circuit device can be significantly facilitated.
第１図は本発明の一実施例による半導体集積回路装置に
使用される配線層パターンを示す図、第２図は半導体集
積回路装置において層間絶縁膜にピンホールが発生して
いる状態を示す図である。
１・・・基板、２．４・・・層間絶縁膜、３，５，６゜
７・・・配線層パターン、８，９・・・配線層の接続用
パッド。FIG. 1 is a diagram showing a wiring layer pattern used in a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a state in which pinholes are generated in an interlayer insulating film in a semiconductor integrated circuit device. It is. 1... Substrate, 2.4... Interlayer insulating film, 3, 5, 6° 7... Wiring layer pattern, 8, 9... Connection pad for wiring layer.
Claims (1)
とを特徴とする半導体集積回路装置。A semiconductor integrated circuit device comprising an interlayer insulating film and means for recognizing a manufacturing state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63324203A JPH02168642A (en) | 1988-12-21 | 1988-12-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63324203A JPH02168642A (en) | 1988-12-21 | 1988-12-21 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02168642A true JPH02168642A (en) | 1990-06-28 |
Family
ID=18163210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63324203A Pending JPH02168642A (en) | 1988-12-21 | 1988-12-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02168642A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8519388B2 (en) | 2007-12-17 | 2013-08-27 | Nxp B.V. | Embedded structure for passivation integrity testing |
-
1988
- 1988-12-21 JP JP63324203A patent/JPH02168642A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8519388B2 (en) | 2007-12-17 | 2013-08-27 | Nxp B.V. | Embedded structure for passivation integrity testing |
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