JPH02164074A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02164074A JPH02164074A JP32124888A JP32124888A JPH02164074A JP H02164074 A JPH02164074 A JP H02164074A JP 32124888 A JP32124888 A JP 32124888A JP 32124888 A JP32124888 A JP 32124888A JP H02164074 A JPH02164074 A JP H02164074A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- electrode
- polysilicon
- metal silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000000470 constituent Substances 0.000 abstract description 5
- 238000002844 melting Methods 0.000 abstract description 5
- 230000008018 melting Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000005121 nitriding Methods 0.000 abstract 3
- 239000003990 capacitor Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000007774 longterm Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- -1 W and Ti Chemical class 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ＭＩＳ型半導体装置に関し、ゲート絶縁膜ま
たはＭＯ８容量の耐圧特性および長期信頼性を向上させ
た半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MIS type semiconductor device, and more particularly to a semiconductor device in which the withstand voltage characteristics and long-term reliability of a gate insulating film or an MO8 capacitor are improved.
従来、半導体装置のゲート電極材料としては、ポリシリ
コン膜が用いられており、信頼性が高いことから広く使
われている。しかし、層抵抗が２０〜３０Ω／口と高い
ため、半導体装置の動作速度を速くできない欠点がある
。高速化には、配線抵抗の低抵抗化が不可欠であり、従
来ポリシリコン膜上に層抵抗の低いＷＳｉｘ、ＴｉＳｉ
ｘなどの金属シリサイド膜を積層した電極、即ちポリサ
イド電極が用いられていた。Conventionally, polysilicon films have been used as gate electrode materials for semiconductor devices, and are widely used because of their high reliability. However, since the layer resistance is as high as 20 to 30 Ω/hole, there is a drawback that the operating speed of the semiconductor device cannot be increased. In order to increase the speed, it is essential to reduce the wiring resistance, and conventionally, low resistance layers such as WSix and TiSi are used on the polysilicon film.
An electrode in which metal silicide films such as x are laminated, that is, a polycide electrode has been used.
すなわち、第３図は、従来用いられるポリサイド電極を
用いたＭＯ３容量の構造を説明する断面図である。図に
おいて、１はシリコン基板、５は金属シリサイド膜、４
はポリシリコン膜、２はフィールド酸化膜、３はゲート
絶縁膜を示す。That is, FIG. 3 is a cross-sectional view illustrating the structure of an MO3 capacitor using a conventionally used polycide electrode. In the figure, 1 is a silicon substrate, 5 is a metal silicide film, and 4 is a silicon substrate.
2 is a polysilicon film, 2 is a field oxide film, and 3 is a gate insulating film.
ゲート絶縁膜３の上にポリシリコン膜４と金属シリサイ
ド膜５が順次積層され、シリコン基板１との間にＭＯ８
容量が構成される。A polysilicon film 4 and a metal silicide film 5 are sequentially laminated on the gate insulating film 3, and an MO8 film is formed between the gate insulating film 3 and the silicon substrate 1.
capacity is configured.
上述した、従来のポリサイド電極は、ポリシリコン膜上
に直接、金属シリサイド膜を形成した構造の電極膜を用
いていた金属シリサイド膜を電極に用いた場合、ポリシ
リコン電極に比べＭＩＳ構造に用いるゲート絶縁膜が耐
圧不良を起したり、絶縁破壊に対する長期信頼性を低下
させる欠点があった。例えば、通常のポリシリコン電極
の場合、耐圧のヒストグラムは第４図であるのに対して
、ポリサイド電極の場合には、第５図に示すように耐圧
特性が劣化する。この原因は、金属シリサイド膜の構成
元素であるＷやＴｉなどの高融点金属が、下地ポリシリ
コン膜中を通り抜はゲート絶縁膜表面にまで到達し、絶
縁膜に損傷を与えるためと推定される。The conventional polycide electrode mentioned above uses an electrode film with a structure in which a metal silicide film is directly formed on a polysilicon film.When a metal silicide film is used as an electrode, the gate used in an MIS structure is smaller than a polysilicon electrode. This has the disadvantage that the insulating film may have a breakdown voltage problem and its long-term reliability against dielectric breakdown may be reduced. For example, in the case of a normal polysilicon electrode, the withstand voltage histogram is as shown in FIG. 4, whereas in the case of a polycide electrode, the withstand voltage characteristics deteriorate as shown in FIG. The reason for this is presumed to be that high-melting point metals such as W and Ti, which are constituent elements of the metal silicide film, pass through the underlying polysilicon film and reach the surface of the gate insulating film, damaging the insulating film. Ru.
従来、半導体装置の電極としてポリサイド電極を用いる
と、金属シリサイド膜の構成元素である高融点金属がポ
リシリコン膜を通り抜はゲート絶縁膜表面に到達し絶縁
膜と反応し、ＭＩＳ型半導体装置の信頼性を低下させる
という問題に対し、本発明では、金属シリサイド膜から
その構成元素である高融点金属がポリシリコン膜を通り
抜けてゲート絶縁膜に到達するのを防ぐため、金属シリ
サイド膜とポリシリコン膜の間に導電性のある窒化金属
膜を設けることにより歩留りが高く、かつ長期信頼性に
も優れたＭＩＳ型半導体装置を実現するものである。Conventionally, when a polycide electrode is used as an electrode in a semiconductor device, a high-melting point metal, which is a constituent element of the metal silicide film, passes through the polysilicon film and reaches the surface of the gate insulating film, where it reacts with the insulating film, causing problems in MIS semiconductor devices. To address the problem of reduced reliability, in the present invention, in order to prevent the high melting point metal from the metal silicide film, which is a constituent element thereof, from passing through the polysilicon film and reaching the gate insulating film, the metal silicide film and the polysilicon film are By providing a conductive metal nitride film between the films, an MIS type semiconductor device with high yield and excellent long-term reliability is realized.
つぎに本発明を実施例により説明する。 Next, the present invention will be explained by examples.
第１図は本発明の一実施例のＭＯ８容量部を示す断面図
である。第１図において、これを第３図の従来例と比べ
ると、本実施例では、ポリシリコン膜４と金属シリサイ
ド膜５との間に、第３図ではなかった、窒化金属膜６を
有することに違いがある。図のようなＭＯ８容量を形成
する手順としては、まず、周知の選択酸化法を用いてシ
リコン基板１上の所望の領域にフィールド酸化膜２を形
成した後に、ゲート絶縁膜３を形成する。次に、電極と
してポリシリコン膜４を形成した後に、このポリシリコ
ン膜に不純物拡散法によりドーピングを行い、次に窒化
金属膜６、金属シリサイド膜５を積層した後に、フォト
エツチング技術を用いて所望の領域に電極膜を形成し、
ＭＯ８容量が完成する。窒化金属膜６としては、ＴｉＮ
などを数１００人程変形膜厚とすること、金属シリサイ
ド膜５としてＷＳｉｘ、ＴｉＳｉｘ、ＭｏＳｉｘなどの
シリサイドを１０００〜４０００人程度設けるのが変形
、このような構造の電極を用いることにより、第４図に
示すようなポリシリコン電極の場合の耐圧のヒストグラ
ムと同様な優れた耐圧のＭＯ３容量を実現することがで
きた。FIG. 1 is a sectional view showing an MO8 capacitor section according to an embodiment of the present invention. Comparing this with the conventional example shown in FIG. 3 in FIG. 1, this example has a metal nitride film 6 between the polysilicon film 4 and the metal silicide film 5, which is not shown in FIG. There is a difference. The procedure for forming the MO8 capacitor as shown in the figure is to first form a field oxide film 2 in a desired region on a silicon substrate 1 using a well-known selective oxidation method, and then to form a gate insulating film 3. Next, after forming a polysilicon film 4 as an electrode, this polysilicon film is doped by an impurity diffusion method, and then a metal nitride film 6 and a metal silicide film 5 are laminated, and then a desired pattern is formed using a photoetching technique. Form an electrode film in the area of
MO8 capacity is completed. As the metal nitride film 6, TiN
By using an electrode with such a structure, it is possible to make the thickness of the metal silicide film 5 about 1000 to 4000. It was possible to realize an MO3 capacitor with an excellent breakdown voltage similar to the histogram of breakdown voltage in the case of a polysilicon electrode as shown in the figure.
第２図は、本発明の他の実施例の断面図であり、ＭＯＳ
トランジスタのゲート電極に適用した場合である。第２
図において、９は絶縁膜、７はアルミ電極、８はソース
、ドレイン領域である。このＭＯＳ）ランジスタの形成
をする手順としては、まず選択酸化法によりシリコン基
板１の所望の領域にフィールド酸化膜２を形成した後、
ゲート絶縁膜３を形成する。次に、ポリシリコン膜４を
形成した後に、ポリシリコン膜４に不純物をドーピング
し、次に、スパッタ法等で、窒化金属膜６を数１００人
程変形成した後、金属シリサイド膜５を形成し、しかる
後にバターニングを行ない電極を形成する。次にイオン
注入などの手法を用いて、ソース、ドレインとなる不純
物領域８を形成した後に、絶縁膜９を形成し、次にソー
ス、ドレイン領域の表面の一部の絶縁膜を除去した後に
、アルミ配線７を形成し、ＭＯＳ）ランジスタが完成す
る。このような構造の電極を用いることにより耐圧不良
が極めて少く長期信頼性の優れたＭＯＳトランジスタを
実現することができる。FIG. 2 is a cross-sectional view of another embodiment of the present invention, in which a MOS
This is a case where it is applied to a gate electrode of a transistor. Second
In the figure, 9 is an insulating film, 7 is an aluminum electrode, and 8 is a source and drain region. The procedure for forming this MOS transistor is to first form a field oxide film 2 in a desired region of a silicon substrate 1 by selective oxidation, and then
A gate insulating film 3 is formed. Next, after forming a polysilicon film 4, impurities are doped into the polysilicon film 4, and then a metal nitride film 6 is formed by several hundred layers by sputtering or the like, and then a metal silicide film 5 is formed. After that, patterning is performed to form electrodes. Next, using a technique such as ion implantation, an impurity region 8 that will become the source and drain is formed, and then an insulating film 9 is formed, and then a part of the insulating film on the surface of the source and drain region is removed. Aluminum wiring 7 is formed, and a MOS transistor is completed. By using an electrode having such a structure, it is possible to realize a MOS transistor with extremely few breakdown voltage defects and excellent long-term reliability.
Ｃ発明の効果〕
以上説明したように本発明は、ＭＩＳ型半導体装置にポ
リサイド電極を用いる場合、ポリシリコン膜と金属シリ
サイド膜との間に、導電性のある窒化金属膜をはさむこ
とにより、金属シリサイドの構成元素である高融点金属
がポリシリコン中を通り抜けてゲート絶縁膜表面に、到
達することによる絶縁膜の絶縁破壊特性の劣化の問題を
改善することができる。C. Effects of the Invention] As explained above, when using a polycide electrode in an MIS type semiconductor device, the present invention provides a metal It is possible to improve the problem of deterioration of the dielectric breakdown characteristics of the insulating film caused by the high melting point metal that is a constituent element of silicide passing through polysilicon and reaching the surface of the gate insulating film.
第１図は、本発明の一実施例を説明する断面図、第２図
は本発明の他の実施例を説明する断面図、第３図は従来
のポリサイド電極を有する半導体装置の断面図である。
第４図、第５図は、ＭＩＳ容量における耐圧のヒストグ
ラムであり、横軸は、絶縁破壊の電界で、縦軸は、絶縁
破壊の頻度を示す。
ｌ・・・・・・シリコン基板、２・・・・・・フィール
ド酸化膜、３・・・・・・ゲート絶縁膜、４・・・・・
・ポリシリコン膜、５・・・・・・金属シリサイド膜、
６・・・・・・窒化金属膜、７・・・・・・アルミ電極
、８・・・・・・ソース、ドレイン、９・・・・・・絶
縁膜。
代理人 弁理士 内 原 晋
革
蓑
連FIG. 1 is a cross-sectional view for explaining one embodiment of the present invention, FIG. 2 is a cross-sectional view for explaining another embodiment of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor device having a conventional polycide electrode. be. 4 and 5 are histograms of breakdown voltages in MIS capacitors, where the horizontal axis shows the electric field of dielectric breakdown, and the vertical axis shows the frequency of dielectric breakdown. l...Silicon substrate, 2...Field oxide film, 3...Gate insulating film, 4...
・Polysilicon film, 5...Metal silicide film,
6...Metal nitride film, 7...Aluminum electrode, 8...Source, drain, 9...Insulating film. Agent Patent Attorney Shin Uchihara
Claims (1)
次積層した構造の電極膜を有することを特徴とする半導
体装置。A semiconductor device characterized by having an electrode film having a structure in which a polysilicon film, a metal nitride film, and a metal silicide film are sequentially laminated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32124888A JPH02164074A (en) | 1988-12-19 | 1988-12-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32124888A JPH02164074A (en) | 1988-12-19 | 1988-12-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02164074A true JPH02164074A (en) | 1990-06-25 |
Family
ID=18130464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32124888A Pending JPH02164074A (en) | 1988-12-19 | 1988-12-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02164074A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6248069A (en) * | 1985-08-28 | 1987-03-02 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPS62111466A (en) * | 1985-11-09 | 1987-05-22 | Toshiba Corp | Semiconductor device |
| JPS63224255A (en) * | 1987-03-13 | 1988-09-19 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1988
- 1988-12-19 JP JP32124888A patent/JPH02164074A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6248069A (en) * | 1985-08-28 | 1987-03-02 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPS62111466A (en) * | 1985-11-09 | 1987-05-22 | Toshiba Corp | Semiconductor device |
| JPS63224255A (en) * | 1987-03-13 | 1988-09-19 | Toshiba Corp | Semiconductor device and manufacture thereof |
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