JPH0216013B2 - - Google Patents
Info
- Publication number
- JPH0216013B2 JPH0216013B2 JP58206968A JP20696883A JPH0216013B2 JP H0216013 B2 JPH0216013 B2 JP H0216013B2 JP 58206968 A JP58206968 A JP 58206968A JP 20696883 A JP20696883 A JP 20696883A JP H0216013 B2 JPH0216013 B2 JP H0216013B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- bonding
- zil
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000004020 conductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、同一の半導体チツプを異なるパツ
ケージにアセンブリする際、より効果的に、か
つ、簡単にワイヤボンデイングすることができる
ようにした半導体装置に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device that enables wire bonding to be performed more effectively and easily when assembling the same semiconductor chip into different packages. It is something.
従来のDILパツケージの場合、第１図に示すよ
うに、半導体チツプ１の中にある信号パツド（ボ
ンデイング用パツド）２と、フレーム３の信号を
入力したり、出力したりする信号入出力部４と
を、ワイヤボンド５で接続し、半導体チツプ１の
信号を外部に取り出したり取り入れたりしてい
る。DILパツケージでは、フレーム３は、第１図
に示すように両方向に２列に伸びている。
In the case of a conventional DIL package, as shown in FIG. 1, there are a signal pad (bonding pad) 2 in a semiconductor chip 1 and a signal input/output section 4 that inputs and outputs signals from a frame 3. are connected by a wire bond 5, and signals from the semiconductor chip 1 are taken out and taken in to the outside. In the DIL package, the frames 3 extend in two rows in both directions, as shown in FIG.
一方、ZILパツケージでは、第２図に示すよう
にDILパツケージと異なり、フレーム３は一方向
側に伸びており、フレーム３の縦方向の寸法を短
くするため、フレーム３の他方向側に信号入出力
部がなく、フレーム３の、紙面に対して両側およ
び下方にある。したがつて、最適なボンデイング
用パツド２の位置は、DILパツケージとZILパツ
ケージでは異なつたものとなつている。 On the other hand, in the ZIL package, as shown in Figure 2, unlike the DIL package, the frame 3 extends in one direction, and in order to shorten the vertical dimension of the frame 3, the signal is input to the other side of the frame 3. There is no output part, and it is located on both sides and below of the frame 3 with respect to the plane of the paper. Therefore, the optimum position of the bonding pad 2 is different between the DIL package and the ZIL package.
このようにそれぞれ異なるパツケージにおける
従来の半導体チツプ１では、ボンデイング用パツ
ド２は同一信号については１個のみであり、例え
ばDILパツケージとZILパツケージに同一の半導
体チツプ１をアセンブリする場合、ワイヤボンド
用の導線が長くなるとか、自動機に対応しにくい
などの欠点があつた。 In this way, in the conventional semiconductor chip 1 in different packages, there is only one bonding pad 2 for the same signal.For example, when assembling the same semiconductor chip 1 into a DIL package and a ZIL package, there is only one bonding pad 2 for wire bonding. There were drawbacks such as the length of the conductor and the difficulty in using automatic machines.
この発明は、上記のような従来のものの欠点を
除去するためになされたもので、半導体チツプ内
に同一信号のボンデイング用パツドを複数個設け
ることにより、異なるパツケージに同一の半導体
チツプをアセンブリした場合でも、最適にワイヤ
ボンドできるようにしたものである。
This invention was made to eliminate the above-mentioned drawbacks of the conventional products, and by providing a plurality of bonding pads for the same signal in a semiconductor chip, it is possible to assemble the same semiconductor chip in different packages. However, it is designed to allow optimal wire bonding.
第３図、第４図はそれぞれこの発明の一実施例
を示すもので、それぞれ第１図、第２図に対応す
るものである。すなわち、第３図の実施例はDIL
パツケージを示し、第４図はZILパツケージを示
すものである。
FIGS. 3 and 4 each show an embodiment of the present invention, and correspond to FIGS. 1 and 2, respectively. That is, the embodiment shown in FIG.
FIG. 4 shows a ZIL package.
第３図、第４図では、半導体チツプ１に設ける
信号パツド（ボンデイング用パツド）２を第１
図、第２図に対して、ボンデイング用パツド２
ａ，２ｂおよび２ｃ，２ｄとして設けたものであ
る。いま、半導体チツプ１のボンデイング用パツ
ドを第３図、第４図のように２ａ，２ｂ，２ｃ，
２ｄとすると、ボンデイング用パツド２ａと２ｂ
は同一信号部であり、また、ボンデイング用パツ
ド２ｃと２ｄも同一信号部である。 In FIGS. 3 and 4, the signal pad (bonding pad) 2 provided on the semiconductor chip 1 is
For Figure 2, bonding pad 2
They are provided as a, 2b and 2c, 2d. Now, as shown in FIGS. 3 and 4, bonding pads 2a, 2b, 2c, and
2d, bonding pads 2a and 2b
are the same signal section, and bonding pads 2c and 2d are also the same signal section.
第３図、第４図のように、同一信号のボンデイ
ング用パツド２ａ，２ｂおよび２ｃ，２ｄを、パ
ツケージに応じて複数個設けることにより、同一
半導体チツプ１を異なるパツケージに最適にワイ
ヤボンドすることができる。 As shown in FIGS. 3 and 4, by providing a plurality of bonding pads 2a, 2b and 2c, 2d for the same signal depending on the package, the same semiconductor chip 1 can be optimally wire-bonded to different packages. Can be done.
すなわち、DILパツケージでは、２ｂおよび２
ｄをボンデイング用パツドとして使用し、２ａお
よび２ｃは使用しない。 That is, in the DIL package, 2b and 2
d is used as a bonding pad, 2a and 2c are not used.
また、ZILパツケージでは、２ａおよび２ｃを
ボンデイング用パツドとして使用し、２ｂおよび
２ｄは使用しない。これにより、DILパツケー
ジ、ZILパツケージともに同一半導体チツプ１
で、最短距離にワイヤボンデイングすることがで
きる。 Further, in the ZIL package, 2a and 2c are used as bonding pads, and 2b and 2d are not used. As a result, both the DIL package and ZIL package use the same semiconductor chip.
This allows wire bonding to be performed over the shortest distance.
なお、上記実施例は、DILパツケージ、ZILパ
ツケージについて説明したが、この発明はこれに
限らず、SILパツケージその他、どんなパツケー
ジにも適用できるものである。 Although the above embodiments have been described with respect to a DIL package and a ZIL package, the present invention is not limited thereto, and can be applied to any other package including a SIL package.
以上説明したように、この発明は、半導体チツ
プを各種のパツケージに適用した場合でも最適な
ワイヤボンデイングが可能なようにパツケージに
応じて複数個のボンデイング用パツドを半導体チ
ツプに設けたので、いずれのパツケージに適用し
た場合でも、前記ボンデイング用パツドを選択的
に使用することによつて、最適なワイヤボンデイ
ングを実現することができる利点がある。
As explained above, in the present invention, a plurality of bonding pads are provided on a semiconductor chip according to the package so that optimal wire bonding is possible even when the semiconductor chip is applied to various packages. Even when applied to a package, there is an advantage that optimal wire bonding can be achieved by selectively using the bonding pads.
第１図はDILパツケージの平面図、第２図は
ZILパツケージの平面図、第３図、第４図はそれ
ぞれDILパツケージ、ZILパツケージでのこの発
明の一実施例を説明するためのDILパツケージお
よびZILパツケージの平面図である。
図中、１は半導体チツプ、２，２ａ，２ｂ，２
ｃ，２ｄは信号パツド（ボンデイング用パツド）、
３はフレーム、４は信号入出力部、５はワイヤボ
ンドである。なお、図中の同一符号は同一または
相当部分を示す。
Figure 1 is a plan view of the DIL package, Figure 2 is
3 and 4 are plan views of a DIL package and a ZIL package, respectively, for explaining an embodiment of the present invention in a DIL package and a ZIL package. In the figure, 1 is a semiconductor chip, 2, 2a, 2b, 2
c, 2d are signal pads (bonding pads),
3 is a frame, 4 is a signal input/output section, and 5 is a wire bond. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ツドとフレームに設けられた信号入出力部とをワ
イヤボンデイングする半導体装置において、前記
半導体チツプに、この半導体チツプを適用する各
種のパツケージに応じて前記ボンデイング用パツ
ドを選択的に使用するため予め同一信号のボンデ
イング用パツドを複数個設けたことを特徴とする
半導体装置。1. In a semiconductor device in which a bonding pad provided on a semiconductor chip and a signal input/output section provided in a frame are wire-bonded, the bonding pad is attached to the semiconductor chip according to various packages to which this semiconductor chip is applied. 1. A semiconductor device characterized in that a plurality of bonding pads of the same signal are provided in advance in order to selectively use the bonding pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20696883A JPS6098652A (en) | 1983-11-02 | 1983-11-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20696883A JPS6098652A (en) | 1983-11-02 | 1983-11-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6098652A JPS6098652A (en) | 1985-06-01 |
| JPH0216013B2 true JPH0216013B2 (en) | 1990-04-13 |
Family
ID=16531982
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20696883A Granted JPS6098652A (en) | 1983-11-02 | 1983-11-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6098652A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0635910U (en) * | 1992-10-16 | 1994-05-13 | 株式会社ニコン | Beam injection device |
| JPH0657572U (en) * | 1993-01-14 | 1994-08-09 | レーザーテクノ株式会社 | Laser device for marking out |
| WO2023100383A1 (en) | 2021-11-30 | 2023-06-08 | 株式会社タムラ製作所 | Solder alloy, solder joining member, solder paste, and semiconductor package |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62114256A (en) * | 1985-11-13 | 1987-05-26 | Mitsubishi Electric Corp | Semiconductor device |
| JPS63208235A (en) * | 1987-02-24 | 1988-08-29 | Nec Corp | Semiconductor device |
| JP2763004B2 (en) * | 1987-10-20 | 1998-06-11 | 株式会社 日立製作所 | Semiconductor device |
| US4990996A (en) * | 1987-12-18 | 1991-02-05 | Zilog, Inc. | Bonding pad scheme |
| JP2560805B2 (en) * | 1988-10-06 | 1996-12-04 | 三菱電機株式会社 | Semiconductor device |
| JPH0770601B2 (en) * | 1989-06-13 | 1995-07-31 | 株式会社東芝 | Master slice type semiconductor device |
| JPH03238839A (en) * | 1990-02-15 | 1991-10-24 | Nec Corp | Semiconductor integrated circuit device |
| US5905300A (en) * | 1994-03-31 | 1999-05-18 | Vlsi Technology, Inc. | Reinforced leadframe to substrate attachment |
| JP2679669B2 (en) * | 1995-02-28 | 1997-11-19 | 日本電気株式会社 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5456360A (en) * | 1977-10-14 | 1979-05-07 | Hitachi Ltd | Production of semiconductor chips |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5531822Y2 (en) * | 1974-12-05 | 1980-07-29 | ||
| JPS5895044U (en) * | 1981-12-18 | 1983-06-28 | セイコーインスツルメンツ株式会社 | IC chip terminal structure |
-
1983
- 1983-11-02 JP JP20696883A patent/JPS6098652A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5456360A (en) * | 1977-10-14 | 1979-05-07 | Hitachi Ltd | Production of semiconductor chips |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0635910U (en) * | 1992-10-16 | 1994-05-13 | 株式会社ニコン | Beam injection device |
| JPH0657572U (en) * | 1993-01-14 | 1994-08-09 | レーザーテクノ株式会社 | Laser device for marking out |
| WO2023100383A1 (en) | 2021-11-30 | 2023-06-08 | 株式会社タムラ製作所 | Solder alloy, solder joining member, solder paste, and semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6098652A (en) | 1985-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950030328A (en) | Semiconductor device, manufacturing method and lead frame | |
| JPH0216013B2 (en) | ||
| KR940008057A (en) | Method and apparatus for joining leads inside a lead-on chip of a lead frame | |
| JP2677737B2 (en) | Semiconductor device | |
| JPH02105450A (en) | Semiconductor device | |
| JPH01220837A (en) | Semiconductor integrated circuit device | |
| JPS59175145A (en) | Lead frame | |
| JPH02246257A (en) | Lead frame for zip | |
| JPH0272556U (en) | ||
| JP2703999B2 (en) | Semiconductor manufacturing equipment | |
| JPH05114622A (en) | Semiconductor device | |
| KR200155176Y1 (en) | A semiconductor package | |
| JPS62131555A (en) | Semiconductor integrated circuit device | |
| JPH0651001Y2 (en) | Optical coupling element | |
| JPS5921168B2 (en) | Manufacturing method for semiconductor integrated circuits | |
| JPH04348538A (en) | Wire bonding structure | |
| JPS63288029A (en) | Resin-sealed semiconductor device | |
| JP2963952B2 (en) | Semiconductor device | |
| JPH0414250A (en) | Wire bonding lead | |
| JPS63311748A (en) | Resin-sealed multi-tip package | |
| JPH06295934A (en) | Film carrier lead and lsi structure using the same | |
| JPH01135058A (en) | Semiconductor device | |
| JPH04287959A (en) | Leadframe | |
| JPH04372161A (en) | Semiconductor device | |
| JPH02112242A (en) | Semiconductor device |