JPH0414250A - Wire bonding lead - Google Patents

Wire bonding lead

Info

Publication number
JPH0414250A
JPH0414250A JP11648690A JP11648690A JPH0414250A JP H0414250 A JPH0414250 A JP H0414250A JP 11648690 A JP11648690 A JP 11648690A JP 11648690 A JP11648690 A JP 11648690A JP H0414250 A JPH0414250 A JP H0414250A
Authority
JP
Japan
Prior art keywords
leads
lead
gap
protruding
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11648690A
Other languages
Japanese (ja)
Inventor
Koji Shibata
浩司 柴田
Yoshitaka Nagayama
永山 義高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP11648690A priority Critical patent/JPH0414250A/en
Publication of JPH0414250A publication Critical patent/JPH0414250A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Abstract

PURPOSE:To reduce the gap between leads and realize a compact package, by making the side surfaces of end portions to which wires of a plurality of leads are bonded protrude toward the side direction, and forming each protruding part of adjacent leads in the manner in which positions of the maximum protruding ends are mutually shifted in the longitudinal direction of the lead. CONSTITUTION:A semiconductor chip 1 is bonded on a chip mounting part 4. Protruding parts 22 are formed on both side surfaces of each tip part 21 of a plurality of leads 2A, 2B, 2C reaching in parallel the vicinity of a side edge, thereby constituting the whole part in a trapezoidal form. Each trapezoid is alternately symmetric, and the maximum protruding end is positioned so as to be separated in the longitudinal direction of the lead by the amount of the trapezoid height. Thereby, when an insulation gap having a width of l2 is obliquely ensured between facing ends, the gap l1 between the leads 2A-2C becomes smaller than conventional gaps. The semiconductor chip 1 and the tip part 21 of each of the leads 2A-2C are connected by wedge-bonding wires 3A-3C. As to the second bonding of the tip part 21, stable bonding having sufficient strength is enabled by making the pressing leg part 51 of a clamping jig 5 abut on the protruding part 22 on both sides.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はワイヤボンディングリードに関し、例えば超音
波によりワイヤボンディングされるリド端部の形状改良
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wire bonding lead, and relates to improving the shape of the end of the lead that is wire-bonded using ultrasonic waves, for example.

[従来の技術] 第5図において、リードフレームの正方形のチップマウ
ント部4上にはやや小さい正方形状の半導体チップ1が
接合しである。半導体チップ1はトランジスタ、抵抗等
が高集積化されたIC1あるいはインテリジエン[〜化
されて入出力端子を複数本有するパワートランジスタ等
である。上記チップマウント部4はCu合金等の板材よ
りなる。
[Prior Art] In FIG. 5, a rather small square semiconductor chip 1 is bonded onto a square chip mount portion 4 of a lead frame. The semiconductor chip 1 is an IC 1 in which transistors, resistors, etc. are highly integrated, or an intelligent power transistor or the like having a plurality of input/output terminals. The chip mount section 4 is made of a plate material such as a Cu alloy.

図略のリードフレーム外周より上記チップマウント部4
の近くへ複数のり一ド2A、2B、2Cが平行に至って
おり、その先端部21と上記チップ1のポンディングパ
ッド(図略)間を例えばウェッジボンディングによりA
ρ、Cu、Au等の金属ワイヤ3A、3B、3Cで接続
しである。
The above chip mount section 4 is viewed from the outer periphery of the lead frame (not shown).
A plurality of glues 2A, 2B, and 2C extend in parallel near the chip 1, and a bond between the tip 21 and the bonding pad (not shown) of the chip 1 is connected by wedge bonding, for example.
They are connected by metal wires 3A, 3B, and 3C made of ρ, Cu, Au, etc.

[発明が解決しようとする課顕] ところで、ウェッジボンディングされるリード端部21
は図示の如く側面を四角形状に突出せしめてあり、この
突出部22−に第6図に示す如くクランプ治具5の抑え
脚部51を当ててボンディング強度の向上と安定を図っ
ている。かかる例は実開昭63−164245号公報に
も開示されている。
[Problem to be solved by the invention] By the way, the lead end 21 to be wedge bonded
As shown in the figure, the side surface of the clamp 22 is projected in a square shape, and the holding leg 51 of the clamp jig 5 is applied to this projection 22-, as shown in FIG. 6, in order to improve and stabilize the bonding strength. Such an example is also disclosed in Japanese Utility Model Application No. 63-164245.

しかしながら、上記突出部22−を設けたことにより、
この間の絶縁間隙あるいは最少打抜き間隙、112  
(以降絶縁間隙g2と呼ぶ)を確保すると、相隣れるリ
ード2A、2B、2C間の間隔g3が大きくなり、パッ
ケージ全体が大形化するという問題がある。
However, by providing the protrusion 22-,
Insulation gap or minimum punching gap between this, 112
If an insulating gap g2 (hereinafter referred to as an insulating gap g2) is ensured, the gap g3 between adjacent leads 2A, 2B, and 2C increases, resulting in a problem that the entire package becomes larger.

本発明はかかる課題を解決するもので、クランプ用の突
出部を設けたリード間の間隔をより小さくすることがで
き、パッケージのコンパクト化を可能としたワイヤボン
ディングリードを提供することを目的とする。
The present invention solves this problem, and aims to provide a wire bonding lead that can reduce the distance between the leads provided with protrusions for clamping, thereby making it possible to make the package more compact. .

[課題を解決するための手段] 本発明の詳細な説明すると、半導体チップ1(第1図)
とワイヤボンディングにより接続される複数のリード2
A、2B、2Cを設け、これらリード2A〜2Cの、ワ
イヤ3A、3B、3Cがボンディングされる端部21の
側面を側方へ突出せしめるとともに、相隣れるリード2
A〜2Cで各突出部22を、その最大突出端の位置が互
いにリード長手方向へずれるように形成したものである
[Means for Solving the Problems] To explain the present invention in detail, a semiconductor chip 1 (FIG. 1)
and multiple leads 2 connected by wire bonding.
A, 2B, and 2C are provided, and the side surfaces of the ends 21 of these leads 2A to 2C, to which the wires 3A, 3B, and 3C are bonded, protrude laterally, and the adjacent leads 2
The protrusions 22 in A to 2C are formed such that the positions of their maximum protruding ends are shifted from each other in the longitudinal direction of the lead.

[作用] 上記構成のワイヤボンディングリードにおいては、各リ
ード突出部22の最大突出端の位置を互いにリード長手
方向へずらして形成しであるから、各最大突出端とこれ
が対向する他のり一ド2A〜2C側面との間に絶縁間隙
92を所定長確保しても、各リード2A〜20間の間隔
p1は従来よりも小さくなり、パッケージのコンパクト
化が実現される。
[Function] In the wire bonding lead having the above configuration, the positions of the maximum protruding ends of the respective lead protrusions 22 are shifted from each other in the lead longitudinal direction. Even if a predetermined length of the insulating gap 92 is secured between the leads 2A to 2C, the distance p1 between the leads 2A to 20 is smaller than that in the conventional case, and the package can be made more compact.

[第1実施例] 第1図において、正方形のチップマウント部4上には正
方形の半導体チップ1が接合され、チップマウント部4
の側縁近傍に平行に至った複数のり一ド2A、2B、2
Cには、各先端部21両側面に側方へ三角形状に突出す
る突出部22が形成されて全体が台形状となっている。
[First Embodiment] In FIG. 1, a square semiconductor chip 1 is bonded on a square chip mount part 4.
A plurality of glued lines 2A, 2B, 2 that are parallel to each other near the side edges of
In C, protrusions 22 that protrude laterally in a triangular shape are formed on both sides of each tip 21, so that the entire tip has a trapezoidal shape.

先端の各台形は交互に対称形となっており、各突出部2
1の最大突出端はリード長手方向へ台形の高さ分だけ離
れて位置している。
Each trapezoid at the tip is alternately symmetrical, and each protrusion 2
The maximum protruding ends of No. 1 are located apart from each other by the height of the trapezoid in the longitudinal direction of the lead.

しかして、上記突出部22の対向端間に斜めに幅g2の
絶縁間隙を確保した場合にも、各リード2A〜20間の
間隔g1は従来の間隔g3に比して小さくなる。
Therefore, even when an insulating gap of width g2 is secured diagonally between the opposing ends of the protrusion 22, the gap g1 between the leads 2A to 20 is smaller than the conventional gap g3.

上記半導体チップ1と各リード2A〜2Cの端部21間
はワイヤ3A〜3Cをウェッジボンディングして接続し
てあり、これら端部21の二番ボンデインクは第2図に
示す如く、クランプ治具5の抑え脚部51を両側の突出
部22に当てることにより、十分な強度を有する安定し
たホンディングが可能である。
The semiconductor chip 1 and the ends 21 of the leads 2A to 2C are connected by wedge bonding wires 3A to 3C, and the second bonding ink of these ends 21 is connected to a clamp jig 5 as shown in FIG. By applying the restraining legs 51 to the protrusions 22 on both sides, stable honding with sufficient strength is possible.

[第2実施例] 第3図において、リード2A、2B、2C12D、2E
のうち、左右端にあるもの2D、2Eの端部は全体が平
行四辺形をなし、その左右の対向辺がボンディング接続
されたワイヤ3D、3Eとほぼ同方向に傾斜している。
[Second Example] In FIG. 3, leads 2A, 2B, 2C12D, 2E
The ends of the left and right wires 2D and 2E have a parallelogram shape as a whole, and the left and right opposite sides thereof are inclined in substantially the same direction as the bonding-connected wires 3D and 3E.

かかる構造によれば、ワイヤ3D、3Eが大きな角度で
振っている左右端のリード端部21においてボンディン
グ時のクランプを良好になすことができる。
According to this structure, good clamping during bonding can be achieved at the left and right lead ends 21 where the wires 3D and 3E are swung at a large angle.

[第3実施例] 第4図において、各リード2A、2B、2Cの端部21
には両側に四角形状に突出する突出部22か形成してあ
り、これら突出部22は隣接対向するものが互いにリー
ド2A〜2Cの長手方向へ位置をずらしである。
[Third Example] In FIG. 4, the ends 21 of each lead 2A, 2B, 2C
There are formed protrusions 22 projecting in a rectangular shape on both sides, and the protrusions 22 that are adjacent and facing each other are shifted in position from each other in the longitudinal direction of the leads 2A to 2C.

かかる構造によっても上記各実施例と同様の効果がある
Such a structure also provides the same effects as those of the above embodiments.

[発明の効果] 以上の如く、本発明のワイヤボンディングリドによれば
、強固かつ安定したワイヤボンティングが可能であると
ともに、リード間の間隔を従来に比して小さくすること
ができるから、パッケジ全体を小形化することが可能で
ある。
[Effects of the Invention] As described above, according to the wire bonding lead of the present invention, strong and stable wire bonding is possible, and the spacing between the leads can be made smaller than before, which improves the package. It is possible to downsize the entire device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は本発明の第1実施例を示し、第1
図はワイヤボンディングリード接続部の拡大平面図、第
2図はワイヤボンディングリード端部の拡大斜視図、第
3図および第4図は本発明のそれぞれ第2および第3実
施例を示すワイヤボンディングリード接続部の拡大平面
図、第5図および第6図は従来例を示し、第5図はワイ
ヤボンディングリード接続部の拡大平面図、第6図はワ
イヤボンディングリード端部の拡大斜視図である。 1・・・半導体チップ 2A、2B、2C12D、2E・・・リード21・・・
端部 22・・・突出部 3A、3B、3C・・・ワイヤ 第1図 第2図 第5図 第6図
1 and 2 show a first embodiment of the present invention;
FIG. 2 is an enlarged perspective view of the end of the wire bonding lead, and FIGS. 3 and 4 are wire bonding leads showing second and third embodiments of the present invention, respectively. 5 and 6 show conventional examples, FIG. 5 is an enlarged plan view of the wire bonding lead connection portion, and FIG. 6 is an enlarged perspective view of the end of the wire bonding lead. 1...Semiconductor chips 2A, 2B, 2C12D, 2E...Leads 21...
End portion 22... Protruding portions 3A, 3B, 3C... Wire Figure 1 Figure 2 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】[Claims]  半導体チップとワイヤボンディングにより接続される
複数のリードを設け、これらリードの、ワイヤがボンデ
ィングされる端部の側面を側方へ突出せしめるとともに
、相隣れるリードで上記各突出部を、その最大突出端の
位置が互いにリード長手方向へずれるように形成したこ
とを特徴とするワイヤボンディングリード。
A plurality of leads are provided to be connected to the semiconductor chip by wire bonding, and the side surfaces of the ends of these leads to which the wires are bonded are made to protrude laterally, and the protrusions of the adjacent leads are extended to their maximum protrusion. A wire bonding lead characterized in that the positions of the ends are shifted from each other in the longitudinal direction of the lead.
JP11648690A 1990-05-02 1990-05-02 Wire bonding lead Pending JPH0414250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11648690A JPH0414250A (en) 1990-05-02 1990-05-02 Wire bonding lead

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11648690A JPH0414250A (en) 1990-05-02 1990-05-02 Wire bonding lead

Publications (1)

Publication Number Publication Date
JPH0414250A true JPH0414250A (en) 1992-01-20

Family

ID=14688312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11648690A Pending JPH0414250A (en) 1990-05-02 1990-05-02 Wire bonding lead

Country Status (1)

Country Link
JP (1) JPH0414250A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696749B1 (en) * 2000-09-25 2004-02-24 Siliconware Precision Industries Co., Ltd. Package structure having tapering support bars and leads

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696749B1 (en) * 2000-09-25 2004-02-24 Siliconware Precision Industries Co., Ltd. Package structure having tapering support bars and leads

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