JPH0215646A - Method of testing ic wafer - Google Patents

Abstract

PURPOSE:To shorten testing time and reduce the abrasion of a stationary probe by a method wherein the result of a wafer test (I) is stored in a memory medium, the test result is read out of the memory medium in another wafer test (II), and the test (II) involves wafers other than those already judged to be defective. CONSTITUTION:While testing is under way in a wafer test (I) 1, the results from testing the respective chips on a wafer involved are stored in a floppy disk(FD) 3. Next, during another wafer test (II) 2, the results of the wafer test (I) 1 stored in the floppy disk(FD) 3 are read therefrom, and chips only judged nondefective in the wafer test (I) are subjected to testing. Accordingly, in a test wherein one and the same wafer is subjected to testing two or more times, time required for testing is shortened and the stationary probe is protected from unnecessary abrasion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC wafer testing method using a memory medium in a wafer test in which the same wafer is tested two or more times.

[Conventional technology]

Figure 2 shows I
It is a flowchart regarding the C wafer test method, (
II) is wafer test (I), (2) is wafer test (
II).

Next, the operation will be explained. On the same wafer, perform wafer test (I) (II) on all chips on the wafer, then perform wafer test (II) (II) on all chips on the wafer.
2).

[Problem to be solved by the invention]

Conventional wafer tests that perform two or more wafer tests are configured as described above, so all chips must be tested, which results in long test processing times for each wafer (or the need for fixed probe needles). There are problems such as rapid wear,
The challenge was how to deal with this.

This invention was made to solve the above-mentioned problems, and aims to shorten test processing time for each wafer and reduce wear on fixed probe needles.

[Means to solve the problem]

The test method according to the present invention stores the results of the wafer test (I) in a memory medium, reads the test results from the memory medium in the wafer test (II), and does not perform the test on items that are already defective. It is designed to test only those that are .

[Effect]

The wafer test method according to the present invention makes it possible to test only non-defective products by performing the wafer test using the test results stored in the memory medium in the wafer test in which the wafer test is performed two or more times.
It enables shortening of test time and reduction of wear on fixed probe needles.

〔Example〕

FIG. 1 is a flowchart of an IC wafer test method according to an embodiment of the present invention, in which (II) is Ueno 1 test (I), (2) is wafer test (II), and (3) is storage of test results. Showing a floppy desk.

The operation will be explained below. Wafer test (I) (I
While conducting tests on floppy disk (3) (hereinafter referred to as F
(denoted as D). Next Ueno) (II)
) When carrying out (2), wafer test (I) (II
) The test results are read out from FD (3) in which the results of wafer test (I) are stored, and the test is performed only on the chips that were found to be non-defective in the wafer test (I).

In the above embodiment, a floppy disk (3) is shown as the memory medium, but other memory media such as a hard disk or magnetic tape may also be used. Further, in the above embodiment, wafer test I (II) and wafer test 1 (2) are performed consecutively, but other operations may be performed in between.

〔Effect of the invention〕

As described above, according to the present invention, since the wafer test is configured to be performed using a memory medium on the same wafer where the wafer test is performed twice or more, the test time can be shortened and the wear of the fixed probe can be reduced. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an IC wafer testing method according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional wafer testing method. In the figure, (II) is a wafer test (I), (2) is a wafer test (II), and (3) is a floppy disk. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An IC wafer test method, characterized in that the wafer test (I) results are stored in a memory medium, and the wafer test (II) is performed using the stored information.