JP2549085B2 - Semiconductor test equipment - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device testing technique, and in manufacturing a small amount of a large number of products such as a gate array, semiconductor devices of different products formed on one wafer are described. The present invention relates to a semiconductor test device for testing or for performing a corresponding test on a semiconductor element of a corresponding address on a wafer even if it is of the same type.

[Technical background of the invention and its problems]

Conventionally, different types of semiconductor elements (chips) are mounted on one wafer
In order to facilitate the test after the completion of this wafer when forming, the same type of product is arranged in each row, and the test is performed by a different test program for each row.

However, in such a test device, it is necessary to form chips of the same type in a row or in a row on a wafer, and it is difficult to form chips of many types. Further, since unnecessary chips are manufactured and evaluated, cost performance is low, and improvement in this respect is desired. Further, even if the same kind of product is used, when a special test is performed on the chip of the corresponding address on the wafer, it is necessary to perform the wafer measurement again on the chip, which is inefficient in manufacturing and evaluation.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object thereof is to provide an excellent semiconductor test apparatus capable of performing a functional test with a test program corresponding to the measurement conditions of chips on a wafer. Is.

[Outline of Invention]

That is, in the present invention, in order to achieve the above object, a storage medium in which wafer information including wafer number information, lot number information, and division information of a test program corresponding to an address on a wafer is stored, and this storage medium are stored. Wafer information input / output device for reading the wafer information stored in the medium and writing information after the test, a test program storage memory for storing the test program, and a load address of the test program stored in the test program storage memory Test program load address storage table, an address decoder for determining the load address of the test program load address storage table based on the output information of the wafer prober, and a test program for the load address determined by this address decoder A semiconductor test device is configured by providing a read circuit for reading from the test program storage memory and loading it to the CPU, so that different types of chips arbitrarily formed on the wafer can be automatically tested. I have to.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration. In the figure, reference numeral 11 is a storage medium in which wafer information is stored, and is composed of, for example, a magnetic disk, a magnetic tape, a magnetic card and the like. As the wafer information, the wafer number, the lot number, the classification information of the product type corresponding to the address on the wafer, the number of fixed elements, the test program, etc. are stored in advance, and the pass / fail information etc. is stored after the test. To be done. Reference numeral 12 denotes a wafer information input / output device for reading wafer information of the designated storage medium 11 and writing pass / fail information of the chip after the test into the storage medium 11, 13
Is a tester for controlling the wafer prober 14 to perform a functional test of the chip, and 15 is loaded with a test program corresponding to the chip being probed from the scan signals in the X and Y directions obtained from the wafer prober 14. Test program load address storage table 16
The table 16 stores the load address of the test program of each chip on the wafer obtained from the wafer information. Reference numeral 17 is a read circuit for reading the address stored in the address designated by the address decoder 15 from the table 16 and causing the CPU 18 to load the test program stored in the address, and 19 is a test program A test program storage memory for storing the, and 20 are input / output devices such as a keyboard and a printer.

Next, the operation of the above configuration will be described with reference to the flowchart of FIG. First, the wafer information stored in the storage medium 11 is read by the wafer information input / output device 12 and set in the CPU 18 (ST1). Next, the test program stored in the storage medium 11 is read by the wafer information input / output device 12 and loaded into the test program storage memory 19 (ST2). Next, the CPU18
Of the wafer information input / output device 12 from the storage medium 11 by the control of
Test program load address storage table via
The load address of each program corresponding to the wafer X and Y addresses is stored in 16 (ST3). Then, the address decoder 15 determines the storage address of the test program load address stored in the table 16 based on the X and Y signals representing the chip position output from the wafer prober 14 (ST4). Next, the read circuit 17 reads the storage address of the table 16, reads the test program from the test program storage memory 19 according to this address (ST5), sends the test program to the tester 13 via the CPU 18, and performs the test. Execute (ST6). After that, the test result (pass / fail information) obtained from the tester 13 is written in the storage medium 11 by the wafer information input / output device 12 (ST7). Next, 1 by CPU18
It is judged whether all the wafers have been tested (ST8), and if not completed, the scan positions X and Y of the tester 13 are moved (S
Then, the process returns to step ST3 and the same test is performed while moving the scan positions X and Y until the test of the chips on the entire surface of the wafer is completed. Then, after the chips on the entire surface of the wafer are tested, the process proceeds to the next step.

With such a configuration, different types of chips arbitrarily arranged on the wafer can be sequentially tested in a moving manner. Need not be formed. Therefore, various types of chips can be formed on one wafer, and it is not necessary to form unnecessary chips and evaluate them, so that cost performance is high. Moreover, the pass / fail information of the chips tested after the test is stored in the storage medium in which the wafer information is stored, so it is easy to manage and analyze the information of each individual wafer, and the feedback to the previous process can be promptly provided. In addition, this information can be effectively used for sorting work in the subsequent process.

In the above embodiment, the test program is stored in the storage medium.
Although the data is stored in 11, the external storage medium dedicated to the test program (eg, magnetic disk, etc.) as shown in FIG.
21 and a reading device 22 for reading the test program written in the external storage medium 21 may be provided. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In the above-mentioned structure, the basic operation is the same as that of the above-mentioned embodiment, and therefore its detailed description is omitted. With such a configuration, the test program and the wafer information are stored in separate storage media, so that the test program corresponding to the wafer to be tested can be freely selected, and the operability of the semiconductor test apparatus is improved. Can be achieved.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain an excellent semiconductor test apparatus capable of performing a functional test on an arbitrary chip on a wafer with a test program corresponding to the measurement condition of the chip.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a semiconductor test apparatus according to an embodiment of the present invention, FIG. 2 is a flow chart for explaining the operation of the apparatus shown in FIG. 1, and FIG. 3 is another example of the present invention. It is a block diagram for explaining an example. 11 ... Storage medium, 12 ... Wafer information input / output device, 13 ...
Tester, 14 ... Wafer prober, 15 ... Address decoder, 16 ... Test program load address storage table, 17 ... Read circuit, 18 ... CPU, 19 ... Test program storage memory.

Claims (1)

(57) [Claims] 1. A storage medium in which wafer information including wafer number information, lot number information, and division information of a test program corresponding to an address on a wafer is stored, and the wafer information stored in the storage medium is read out and tested. Wafer information input / output device for writing subsequent information, test program storage memory for storing test program, test program load address storage table for storing load address of test program stored in this test program storage memory, and wafer prober An address decoder that determines the load address of the test program load address storage table based on the output information of the test program and the test program of the load address that is determined by this address decoder are read from the test program storage memory and C A reading circuit for loading the PU, executing a test according to the test program loaded in the CPU, and writing the test result information in the storage medium in which the wafer information is stored by the wafer information input / output device. Semiconductor test equipment characterized by.