CN117476082A - Multi-chip integrated test method and system - Google Patents

Multi-chip integrated test method and system Download PDF

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Publication number
CN117476082A
CN117476082A CN202311421705.6A CN202311421705A CN117476082A CN 117476082 A CN117476082 A CN 117476082A CN 202311421705 A CN202311421705 A CN 202311421705A CN 117476082 A CN117476082 A CN 117476082A
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test
tested
memory
probe card
memory cells
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CN202311421705.6A
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Inventor
谢晋春
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202311421705.6A priority Critical patent/CN117476082A/en
Publication of CN117476082A publication Critical patent/CN117476082A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

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Abstract

The invention provides a multi-chip integrated test method and a system, wherein the test system comprises the following steps: the substrate to be tested is provided with first to N-th storage units to be tested on one exposure area, and at least one of the first to N-th storage units to be tested is provided with different test ports and at least one of the first to N-th storage units to be tested is provided with different storage capacities; the probe card comprises a probe card, a first probe card and a second probe card, wherein the probe card covers the test ports of the first to N-th memory units to be tested in at least one exposure area; and the test module integrates the test vectors of the first to N-th memory units to be tested into a virtual vector with the same length according to the period, and performs functional test on the first to N-th memory units to be tested on the substrate to be tested in a parallel mode by utilizing the probe card and the virtual vector until the memory unit to be tested with the largest memory capacity completes the functional test. According to the invention, the function test is carried out on a plurality of memory units to be tested with different storage capacities of different test ports at the same time, so that the test efficiency is improved, and the cost is reduced.

Description

Multi-chip integrated test method and system
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method and a system for testing multi-chip integration.
Background
In the semiconductor industry, prior to mass production of a product, a design product needs to be subjected to sample verification to verify whether the design has defects or not, so as to avoid loss of mass production. Or some institutions or companies, the designed products do not need to be produced in mass production, and only need to produce a small number of chips for verification. At this time, a Foundry (Foundry) provides a service, that is, a plurality of items (products) are manufactured on the same wafer (Multi project wafer, MPW), and the MPW service not only meets the requirements of related parties, but also effectively reduces the cost.
While MPW effectively reduces the plate making cost of designing new product chips, the probe cards and test procedures for testing different product chips are generally different, and currently, in testing MPW wafers, single test is often adopted for testing. And more particularly to products containing memory (memory cells), which often also include complications in testing port channels and memory capacities. Therefore, there is a need to reduce the testing cost of multi-project wafers.
Disclosure of Invention
The invention aims to provide a multi-chip integrated test method and a multi-chip integrated test system, which are used for reducing test cost.
In order to solve the above technical problems, the multi-chip integrated test system provided by the present invention includes:
the substrate to be tested is provided with first to N-th storage units to be tested on one exposure area, at least one of the first to N-th storage units to be tested is provided with different test ports, at least one of the first to N-th storage units is provided with different storage capacities, and N is an integer greater than or equal to 2;
the probe card comprises a probe position covering the test ports of the first to N-th memory units to be tested in at least one exposure area;
and the test module is used for integrating the test vectors of the first to N-th memory units to be tested into a virtual vector with the same length according to the period, and performing functional test on the first to N-th memory units to be tested on the substrate to be tested in a parallel mode by utilizing the probe card and the virtual vector until the memory unit to be tested with the largest memory capacity finishes functional test.
Optionally, the substrate to be tested is a multi-project wafer, one exposure area of the multi-project wafer is provided with first to nth devices to be tested, and the first to nth devices to be tested are respectively provided with the corresponding first to nth memory cells to be tested.
Optionally, one exposure area of the substrate to be tested includes M system-on-chips, the M system-on-chips include the first to nth memory cells to be tested, and M is a positive integer less than N.
Optionally, the test module includes an automatic test machine, a main test program running on the automatic test machine, and a virtual vector executed on the main test program, where the main test program is constructed with a framework for testing a single device under test, the first to nth memory units under test are used as different modules of the single device under test, and each channel of the virtual vector is defined by actual arrangement of channels of the first to nth memory units under test and can apply or read signal states.
Optionally, the first to nth memory cells to be tested have a plurality of test modes, and test vectors in each test mode of the first to nth memory cells to be tested are respectively integrated into virtual vectors in test modes corresponding to the test modules.
Optionally, the first to nth memory cells to be tested are all embedded nonvolatile memory structures, and the first to nth memory cells to be tested include an erase test mode, a program test mode and a read test mode.
Optionally, the maximum storage capacity in the first to nth storage units to be measured is used as a unified length of each channel of the virtual vector, and the virtual vector fills the channels with the storage capacity smaller than the maximum storage capacity to the unified length and makes the IO ports of the channels in a high-resistance state or a non-writing non-comparison state.
Optionally, a sleep command or a clock stop command is sent to make the IO port of the corresponding memory cell to be tested in a high-impedance state or a non-writing non-comparison state.
Optionally, the test module further uses the probe card to measure ac parameters and dc parameters of the first to nth memory cells to be tested on the substrate to be tested.
Based on another aspect of the present invention, there is also provided a multi-chip integrated test method, including:
providing a substrate to be tested, wherein a first to an N-th storage units to be tested are arranged on one exposure area of the substrate to be tested, at least one of the first to the N-th storage units to be tested is provided with different test ports, at least one of the first to the N-th storage units is provided with different storage capacities, and N is an integer greater than or equal to 2;
providing a probe card, wherein the needle position of the probe card covers the test ports of the first to N-th memory units to be tested of at least one exposure area;
and integrating the test vectors of the first to N-th memory units to be tested into a virtual vector with the same length, and simultaneously performing functional test on the first to N-th memory units to be tested on the substrate to be tested by using the probe card and the virtual vector until the memory unit to be tested with the largest memory capacity completes the functional test.
The invention carries out functional test on the first to N-th memory cells to be tested in parallel, wherein the needle position of the probe card covers the test ports of the first to N-th memory cells to be tested in at least one exposure area, when the probe card and the test module are used for carrying out functional test, the first to N-th memory cells to be tested in one exposure area are regarded as a device to be tested, each memory cell to be tested is a part of the device to be tested, and each test vector of the first to N-th memory cells to be tested is integrated into a virtual vector with the same length according to the period, and each memory cell to be tested in the device to be tested is tested simultaneously until the memory cell to be tested with the largest memory capacity completes functional test, thereby realizing the simultaneous measurement of a plurality of different memory cells to be tested on the substrate to be tested, improving the test efficiency and reducing the test cost.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention.
FIG. 1 is a schematic diagram of a multi-chip integrated test system according to a first embodiment;
FIG. 2 is a schematic diagram of a portion of virtual vectors of a multi-chip integrated test system according to the first embodiment;
fig. 3 is a flowchart of a multi-chip integrated test method according to the third embodiment.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
Example 1
An embodiment provides a multi-chip integrated test system.
Fig. 1 is a schematic diagram of a multi-chip integrated test system according to a first embodiment.
As shown in fig. 1, the multi-chip integrated test system provided in this embodiment includes a substrate to be tested, a probe card, and a test module. The method comprises the steps that one exposure area of a substrate to be tested is provided with first to N-th storage units to be tested, at least one of the first to N-th storage units to be tested is provided with different test ports, at least one of the first to N-th storage units to be tested is provided with different storage capacities, and N is an integer greater than or equal to 2; the needle position of the probe card covers the test ports of the first to N-th memory units to be tested of at least one exposure area; and the test module integrates the test vectors of the first to N-th memory cells to be tested into virtual vectors with the same length according to the cycle, and performs functional test on the first to N-th memory cells to be tested on the substrate to be tested in a parallel mode by using the probe card and the virtual vectors until the memory cell to be tested with the largest memory capacity completes the functional test.
The substrate may be a multi-project wafer, and includes a plurality of exposure areas sequentially arranged, each exposure area may include first to nth devices to be tested, and the first to nth devices to be tested may be any suitable semiconductor devices, but the first to nth devices to be tested each include a memory unit, i.e., the first to nth devices to be tested are correspondingly provided with the first to nth memory units to be tested. The test ports and the storage capacities of the first to N-th memory cells (devices to be tested) are not identical, i.e. at least one memory cell to be tested has different test channel settings and test channel numbers, and at least one memory cell to be tested has different storage capacities. In some examples, at least one of the first to nth memory cells may further have a different memory structure, for example, a portion of the memory cells to be tested are embedded nonvolatile memory structures, and another portion of the memory cells to be tested are read-only memory structures.
The probe card can be set in a mode of simultaneously measuring a plurality of devices to be measured according to an actual test port (bonding pad) on an exposure area of the substrate to be measured, and the pin position of the probe card can cover bonding pads (bumps) of first to N-th memory cells to be measured of one or more exposure areas.
In the embodiment, the probe card and the testing module are utilized to perform the function test on a plurality of different devices to be tested (including the memory cells to be tested) on the substrate to be tested in a parallel manner, so that the testing efficiency is improved, and the testing cost is reduced. The test module may include an upper computer, an ATE device, a probe station, and the like, and cooperates with the probe card to measure the first through nth memory cells to be measured of the at least one exposure area simultaneously. The method comprises the steps of placing a substrate to be tested on a probe station, connecting an upper computer, ATE equipment, a probe card and the substrate in sequence, executing a test vector (pattern) on a main test program running on the ATE equipment, simultaneously performing functional test on first to N-th memory units to be tested of at least one exposure area on the substrate to be tested, acquiring test results, and sending a test structure to the upper computer for analysis and summarization. In some examples, the host computer and the ATE equipment may also be provided as a single unit.
The main test program running on the ATE equipment may be developed (constructed) according to the architecture of the measurement virtual device under test (single device under test), where each channel (pin) of the first to nth memory cells under test is used as a channel of the virtual device under test, the test vectors (first to nth test vectors) of the first to nth memory cells under test are used as partial vectors of the virtual device under test, and each test vector of the first to nth memory cells under test is integrated into one virtual vector for performing a functional test on the virtual device under test. Each channel in the main test program of the embodiment needs to be defined according to the actual channel arrangement of the probe card, so that the two channels are matched to meet the functional test of the first to the N-th memory units to be tested. In addition, in the present embodiment, when writing the test vector, each channel of the first to nth memory cells to be tested can apply (print) a signal or read a signal state, that is, the test vector of the present embodiment covers each channel (pin) of the first to nth memory cells to be tested.
In particular, in this embodiment, the first to nth test vectors corresponding to the first to nth test units are integrated into virtual vectors so as to perform the functional test on the first to nth test units simultaneously (in parallel), that is, the first rows of the first to nth test vectors are spliced according to the physical channel arrangement of the probe card to form the first rows of the virtual vectors, and the subsequent rows are the same as the first rows of the virtual vectors. Because the lengths (rows) of the test vectors with different storage capacities are different, when writing the virtual vector, the maximum storage capacity of the first to N-th memory cells to be tested is used as the capacity of the virtual vector, namely, the maximum length of the first to N-th test vectors is used as the unified length of each channel of the virtual vector. And the method can adopt operations such as sending a sleep command, stopping a clock and the like to perform invalid filling on a channel with smaller storage capacity (shorter length) in the virtual vector to a uniform length, so that an IO port in a corresponding (smaller storage capacity) storage unit to be tested is in a high-resistance state or a non-writing non-comparison state, and thus, when the function test is executed, the function test of the storage unit to be tested with smaller storage capacity is continued after the function test of the storage unit to be tested with larger storage capacity is completed, and interference between the two storage units is avoided. In practice, the memory cell to be tested includes a plurality of test modes, each of which has a corresponding virtual vector, and in this embodiment, the memory cell to be tested is an embedded memory structure, which may include a program mode, a read mode, and an erase mode. Of course, if the storage structure of a part of the storage units to be tested is different from other storage structures, for example, the part of the storage units to be tested also includes other test modes, the test model can be independently placed for final test, and other storage units to be tested which do not participate in the test are filled in the virtual vector of the test mode in an invalid manner as described above, so that the IO port of the storage units to be tested is in a high-resistance state or a non-writing non-comparison state.
In an example, please refer to fig. 2, which shows virtual vectors (shown in solid line boxes) formed by first to eighth to-be-tested memory cells (DUT 1 to DUT 8), wherein the first to seventh to-be-tested memory cells are respectively provided with three channels, the eighth to-be-tested memory cell is provided with four channels, each test vector of the first to eighth to-be-tested memory cells is a first to eighth test vector (shown in dashed line boxes), the last bit in the first to eighth test vectors is an IO bit, the first few bits are status bits (including power supply, clock, control, etc.), and the storage capacity of the third to eighth to-be-tested memory cells is larger than that of the second to-be-tested memory cell, and the storage capacity of the second to-be-tested memory cell is larger than that of the first to-be-tested memory cell. In the virtual vector formed by the first to eighth test vectors, after the first to eighth test cells complete the functional test, all the subsequent status bits are set to "00" so that the IO bits thereof are fixed to "Z", and similarly, after the second to eighth test cells complete the functional test, all the subsequent status bits are set to "0" so that the IO bits thereof are fixed to "X" (Z and X represent similar states, Z is a high resistance state, X is a non-writing non-comparison state or no input and no output state), and the remaining third to eighth test cells continue to perform the functional test until the test cell with the largest storage capacity completes the functional test.
Of course, in the above functional test process, the main test program also captures the test result information in the IO port of each storage unit to be tested, so as to compare with the preset information of each storage unit to be tested, so as to perform functional judgment and corresponding positioning processing.
In addition, the probe card and the test module of the embodiment can also be used for carrying out communication tests, such as open-short circuit tests, direct current tests, alternating current tests and the like, on the first to the N devices to be tested on the substrate. In the open-short circuit test and partial direct current test, corresponding test channels of the first to N-th devices to be tested are set to be in corresponding test states; when the test vector is needed to be adopted for part of the direct current test items, the method similar to the virtual vector in the function test can be adopted similarly, so that the test efficiency is improved.
Example two
The second embodiment provides a multi-chip integrated test system.
The multi-chip integrated test system provided in the second embodiment is similar to the test system provided in the first embodiment, and the two are similar in terms of test principle and test system arrangement, and the difference is mainly as follows: in the second embodiment, an exposure area on the substrate is provided with M devices to be tested, where M devices to be tested have the first to nth memory cells to be tested, and M is a positive integer less than N, that is, at least one device to be tested has at least one memory cell to be tested. In some examples, the device under test on the substrate in the second embodiment is a System-on-a-Chip (SoC), and the SoC has more than two memory cells under test, where the more than two memory cells under test have different test ports and different storage capacities.
Example III
An embodiment III provides a multi-chip integrated test method.
Fig. 3 is a flowchart of a multi-chip integrated test method according to the third embodiment.
As shown in fig. 3, the multi-chip integrated test method provided in this embodiment includes:
s01: providing a substrate to be tested, wherein a first to an N-th storage units to be tested are arranged on one exposure area of the substrate to be tested, at least one of the first to the N-th storage units to be tested is provided with different test ports, at least one of the first to the N-th storage units is provided with different storage capacities, and N is an integer greater than or equal to 2;
s02: providing a probe card, wherein the needle position of the probe card covers the test ports of the first to N-th memory units to be tested of at least one exposure area;
s03: and integrating the test vectors of the first to N-th memory units to be tested into a virtual vector with the same length, and simultaneously performing functional test on the first to N-th memory units to be tested on the substrate to be tested by using the probe card and the virtual vector until the memory unit to be tested with the largest memory capacity completes the functional test.
The multi-chip integrated test method may specifically refer to the test system provided in the first embodiment, and will not be described herein.
In summary, the present invention performs the functional test on the first to nth test memory cells having different test ports and different memory capacities on one exposure area of the substrate to be tested in a parallel manner, wherein the needle position of the probe card covers the test ports of the first to nth test memory cells of at least one exposure area, when the functional test is performed by using the probe card and the test module, the first to nth test memory cells on one exposure area are regarded as one device to be tested, each test memory cell is a part of the device to be tested, and each test vector of the first to nth test memory cells is periodically integrated into a virtual vector having the same length to simultaneously test each test memory cell in the device to be tested until the memory cell to be tested with the largest memory capacity completes the functional test, thereby realizing the simultaneous measurement of a plurality of different memory cells to be tested on the substrate to be tested, improving the test efficiency, and reducing the test cost.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. A multi-chip integrated test system, comprising:
the substrate to be tested is provided with first to N-th storage units to be tested on one exposure area, at least one of the first to N-th storage units to be tested is provided with different test ports, at least one of the first to N-th storage units is provided with different storage capacities, and N is an integer greater than or equal to 2;
the probe card comprises a probe position covering the test ports of the first to N-th memory units to be tested in at least one exposure area;
and the test module is used for integrating the test vectors of the first to N-th memory units to be tested into a virtual vector with the same length according to the period, and performing functional test on the first to N-th memory units to be tested on the substrate to be tested in a parallel mode by utilizing the probe card and the virtual vector until the memory unit to be tested with the largest memory capacity finishes functional test.
2. The multi-chip integrated test system of claim 1, wherein the substrate to be tested is a multi-project wafer, one exposure area of the multi-project wafer having first through nth devices to be tested, each of the first through nth devices to be tested having a corresponding one of the first through nth memory cells to be tested.
3. The multi-chip integrated test system of claim 1, wherein one exposure area of the substrate under test comprises M system-on-chips, M of the system-on-chips comprising the first through nth memory cells under test, M being a positive integer less than N.
4. The multi-chip integrated test system of claim 1, wherein the test module comprises an automatic tester, a main test program running on the automatic tester, and a virtual vector executing on the main test program, the main test program being constructed in a configuration for testing a single device under test, wherein the first through nth memory cells are different modules of the single device under test, and each channel of the virtual vector is defined by an actual arrangement of channels of the first through nth memory cells and is capable of applying or reading a signal state.
5. The multi-chip integrated test system according to claim 4, wherein the first to nth memory cells to be tested have a plurality of test modes, and the test vectors in each test mode of the first to nth memory cells to be tested are respectively integrated into the virtual vector in the test mode corresponding to the test module.
6. The multi-chip integrated test system of claim 5, wherein the first through N-th memory cells are all embedded nonvolatile memory structures, and the first through N-th memory cells include an erase test mode, a program test mode, and a read test mode.
7. The multi-chip integrated test system of claim 1, wherein a maximum memory capacity among the first through nth memory cells to be tested is taken as a uniform length of each channel of the virtual vector, and the virtual vector fills channels in which the memory capacity is smaller than the maximum memory capacity to the uniform length and makes the IO ports thereof in a high-impedance state or a non-writing non-comparison state.
8. The multi-chip integrated test system of claim 7, wherein the sending of the sleep command or the stop clock command is used to place the IO port of the corresponding memory cell under test in a high-impedance state or a non-write non-compare state.
9. The multi-chip integrated test system of claim 1, wherein the test module further uses the probe card to perform ac parameter measurement and dc parameter measurement on the first through nth test memory cells on the substrate under test.
10. A multi-chip integrated test method, comprising:
providing a substrate to be tested, wherein a first to an N-th storage units to be tested are arranged on one exposure area of the substrate to be tested, at least one of the first to the N-th storage units to be tested is provided with different test ports, at least one of the first to the N-th storage units is provided with different storage capacities, and N is an integer greater than or equal to 2;
providing a probe card, wherein the needle position of the probe card covers the test ports of the first to N-th memory units to be tested of at least one exposure area;
and integrating the test vectors of the first to N-th memory units to be tested into a virtual vector with the same length, and simultaneously performing functional test on the first to N-th memory units to be tested on the substrate to be tested by using the probe card and the virtual vector until the memory unit to be tested with the largest memory capacity completes the functional test.
CN202311421705.6A 2023-10-30 2023-10-30 Multi-chip integrated test method and system Pending CN117476082A (en)

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