JPH02151033A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02151033A JPH02151033A JP30522288A JP30522288A JPH02151033A JP H02151033 A JPH02151033 A JP H02151033A JP 30522288 A JP30522288 A JP 30522288A JP 30522288 A JP30522288 A JP 30522288A JP H02151033 A JPH02151033 A JP H02151033A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- aluminum
- aluminum wiring
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 38
- 229910052782 aluminium Inorganic materials 0.000 abstract description 38
- 239000010410 layer Substances 0.000 abstract description 32
- 239000011229 interlayer Substances 0.000 abstract description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- 229960000583 acetic acid Drugs 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製法に関し、特に半導体集積回路
装置における二層あるいはそれ以上の多層配線の形成方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming two or more layers of multilayer wiring in a semiconductor integrated circuit device.
従来、この種の多層配ｔｉ構造を用いた半導体装置の製
法は、第２図（Ａ）、（Ｂ）の工程断面図に示すように
、まず同図（Ａ）において、シリコンの半導体基板１上
に、Ｓ、Ｏ２等の絶縁膜２を介して第１層目となる第１
アルミニウム配線３ａをドライエツチングにて形成する
。この時第１アルミニウム配線３ａの断面は、長方形又
は正方形となっている。Conventionally, in the manufacturing method of a semiconductor device using this type of multilayer Ti structure, as shown in the process cross-sectional views of FIGS. 2(A) and 2(B), first, in FIG. A first layer is formed on the top through an insulating film 2 made of S, O2, etc.
Aluminum wiring 3a is formed by dry etching. At this time, the cross section of the first aluminum wiring 3a is rectangular or square.
次いで同図（Ｂ）において、ＣＶＤ法で形成された５Ｉ
０２等の眉間絶縁膜４を介して、第２層目となる第２ア
ルミニウム配線５を蒸着又はスパッタ法によって形成し
ていた。Next, in the same figure (B), 5I formed by CVD method
A second aluminum wiring 5 serving as a second layer was formed by vapor deposition or sputtering via a glabellar insulating film 4 such as 02.
また、この方法を改良した方法として、第３図（Ａ）、
（Ｂ）の工程断面図に示すように、感光性樹脂いわゆる
ホトレジスト６ｃをマスクとし、１回目の露光工程及び
ドライエツチング工程により、同図（Ａ）のように第１
アルミニウム配線層３の厚さを半分程残し、次いで２回
目の露光工程及びドライエツチング工程により、第１ア
ルミニウム配線層３の残りの部分を除去すると共に同図
（Ｂ）のように第１アルミニウム配線３ａの断面形状を
ステップ幅ｄの階段状に形成する方法がとられていた。In addition, as an improved method of this method, Fig. 3 (A),
As shown in the cross-sectional view of the process in (B), a photosensitive resin, so-called photoresist 6c, is used as a mask, and through the first exposure process and dry etching process, the first
After leaving about half the thickness of the aluminum wiring layer 3, the remaining portion of the first aluminum wiring layer 3 is removed by a second exposure process and a dry etching process, and the first aluminum wiring is formed as shown in FIG. A method has been used in which the cross-sectional shape of 3a is formed into a step-like shape with a step width d.
上述した従来の多層配線構造を有する半導体装置の製法
は、第２図（Ｂ）に示すように、配線が長方形又は正方
形断面の場合には、第１アルミニウム配線３ａの上端部
により生ずる層間絶縁膜４の肩部４ａにおいて、第２ア
ルミニウム配線５に段切れが生じてしまうという欠点が
あった。As shown in FIG. 2(B), in the manufacturing method of a semiconductor device having a conventional multilayer wiring structure as described above, when the wiring has a rectangular or square cross section, an interlayer insulating film is formed at the upper end of the first aluminum wiring 3a. There is a drawback that a break occurs in the second aluminum wiring 5 at the shoulder portion 4a of the second aluminum wiring 5.
又、第３図に示すように配線が階段状断面の場合には、
第１アルミニウム配線３ａの上端部の急峻性が緩和され
、第２図（Ｂ）に示すような第２アルミニウム配線５の
段切れは回避される。Also, if the wiring has a stepped cross section as shown in Figure 3,
The steepness of the upper end portion of the first aluminum wiring 3a is alleviated, and breakage of the second aluminum wiring 5 as shown in FIG. 2(B) is avoided.
しかし、この方法では、２回の露光工程を必要とするの
で工数がかかること、２回のマスク合わせてパターンの
ずれが生ずること、さらに階段を作るためのステップ幅
ｄが３〜５μｍ程度は必要であり、半導体装置の高集積
化に伴うアルミニウム配線の微細パターン化が難しい等
の欠点があった。However, this method requires two exposure steps, which takes a lot of man-hours, and the pattern shift occurs when the two masks are aligned.Furthermore, the step width d to create the stairs needs to be about 3 to 5 μm. However, there are drawbacks such as difficulty in forming fine patterns of aluminum wiring as semiconductor devices become more highly integrated.
本発明は、半導体基板上に形成された配線層上にホトレ
ジス！・層からなる所定パターンのエツチング用マスク
を形成し、該マスクを用いて前記配線層を所定の膜厚だ
けウェットエツチングにより除去し、次いで該マスクを
そのまま用いて前記ウェットエツチングの際残した配線
層膜厚をドライエツチングにより除去し、階段状の断面
形状を有する配線を形成する半導体装置の製法である。The present invention uses photoresist on a wiring layer formed on a semiconductor substrate! - Form an etching mask with a predetermined pattern consisting of layers, use the mask to remove the wiring layer by a predetermined thickness by wet etching, and then use the mask as it is to remove the wiring layer left during the wet etching. This is a method of manufacturing a semiconductor device in which the film thickness is removed by dry etching to form wiring having a stepped cross-sectional shape.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（人）〜（Ｅ）は本発明の一実施例を工程順に示
した工程断面図である。FIGS. 1 (person) to (E) are process sectional views showing an embodiment of the present invention in order of process.
まず同図（Ａ）において、集積回路等が形成された半導
体基板１上に、５Ｌ０２等の絶縁膜２を介して被着形成
された第１アルミニウム配線層３を設け、その上にホト
レジストを塗布してホトレジスト層６を形成する。この
場合のホトレジストとしてはポジタイプを用いるが、ネ
ガタイプを用いることもできる。First, in the same figure (A), a first aluminum wiring layer 3 is provided on a semiconductor substrate 1 on which an integrated circuit, etc. is formed, through an insulating film 2 such as 5L02, and a photoresist is applied thereon. Then, a photoresist layer 6 is formed. In this case, a positive type photoresist is used, but a negative type can also be used.
そして、このホトレジスト層６に対してホトマスク７に
より露光処理を行う。光の当った部分（露光部６ａと称
する）は変化し現像液に可・溶となる０次に同図（Ｂ）
において、このホトレジスト層６に対して現像処理を施
して露光部６ａを除去し、第１アルミニウム配線層３の
面上に未露光部６ｂの所定パターンのホトレジスト６ｃ
を形成する。Then, this photoresist layer 6 is exposed to light using a photomask 7. The area hit by the light (referred to as the exposed area 6a) changes and becomes soluble and soluble in the developer, as shown in the same figure (B).
Then, the photoresist layer 6 is developed to remove the exposed portion 6a, and a predetermined pattern of photoresist 6c of the unexposed portion 6b is formed on the surface of the first aluminum wiring layer 3.
form.
次に同図（Ｃ）において、４０℃程度に加熱したリン酸
（ＨｓＰＯｎ）と硝酸（ＨＮＯ３）と氷酢酸（ＣＨｓＣ
ＯＯＨ）と水とを、例えば容積比が１６：１：２： ｌ
である混合液を用いて、ホトレジスト６ｃをマスクにし
て第１アルミニウム配線層３を所定の厚さ（例えば元の
厚さの２７３程度）だけ残してウェットエツチングする
。この際、第１アルミニウム配線層３のホトレジスト６
ｃの下側両サイド部分もオーバーエツチングされて除去
される。Next, in the same figure (C), phosphoric acid (HsPOn), nitric acid (HNO3) and glacial acetic acid (CHsC) heated to about 40°C are shown.
OOH) and water at a volume ratio of 16:1:2:l, for example.
The first aluminum interconnection layer 3 is wet-etched using a mixed solution having a predetermined thickness (for example, about 273 mm of the original thickness) using the photoresist 6c as a mask. At this time, the photoresist 6 of the first aluminum wiring layer 3
Both lower side portions of c are also overetched and removed.
続いて同図（Ｄ）のように、ホトレジスト６ｃをマスク
にして、例えば六面体カソード電極を備えた反応性イオ
ンエツチング装置を用いて、圧力条件を３０ｍＴｏｒｒ
、 ＲＦパワー条件を１５００Ｗ、ガス条件を三塩化
ホウ素（ＢＣｌ２）と塩素（ＣＩ２）と四弗化炭素（Ｃ
Ｆ４）の流量比が１５：５：２の混合ガスとして、第１
アルミニウム配線層の前工程で残した部分をドライエツ
チング除去し、第１アルミニウム配線３ａを形成する。Next, as shown in FIG. 6(D), using the photoresist 6c as a mask, using a reactive ion etching device equipped with a hexahedral cathode electrode, for example, the pressure condition was set to 30 mTorr.
, RF power condition was 1500W, gas condition was boron trichloride (BCl2), chlorine (CI2), and carbon tetrafluoride (C
F4) as a mixed gas with a flow rate ratio of 15:5:2.
The portion of the aluminum wiring layer left in the previous step is removed by dry etching to form a first aluminum wiring 3a.
次いで、この状態のまま半導体基板１をプラズマ灰化装
置内に配し、酸素プラズマにてホトレジスト６Ｃを灰化
削減せしめる。Next, the semiconductor substrate 1 is placed in a plasma ashing apparatus in this state, and the photoresist 6C is ashed and reduced by oxygen plasma.
然る後同図（Ｅ）に示すように、第１アルミニウム配線
３ａを含む全面にＣＶＤ法によって５Ｌ０２等の眉間絶
縁膜４を被着形成後、全面にアルミニウムを蒸着し、次
いでこのアルミニウム層を所定パタンにエツチングして
第２アルミニウム配線５を形成する。第２アルミニウム
配線５は、第１アルミニウム配線３ａの断面が階段形状
であるので、段切れすることなく第１アルミニウム配線
３ａと交叉して形成される。Thereafter, as shown in FIG. 3(E), a glabellar insulating film 4 such as 5L02 is deposited on the entire surface including the first aluminum wiring 3a by the CVD method, and then aluminum is vapor-deposited on the entire surface, and then this aluminum layer is deposited on the entire surface. A second aluminum wiring 5 is formed by etching into a predetermined pattern. Since the cross section of the first aluminum wiring 3a is step-shaped, the second aluminum wiring 5 is formed to intersect with the first aluminum wiring 3a without being broken.
なお、本発明は上記実施例のみに限定されず、三層以上
の多層配線にも適用できる。その際には下層の配線を全
て上述の方法によって階段状断面とすればよい。Note that the present invention is not limited to the above-mentioned embodiments, but can also be applied to multilayer wiring of three or more layers. In this case, all of the lower layer wiring may be made into a step-like cross section by the above-described method.
以上説明したように本発明は、第１層目を形成する場合
に、所定のパタンのホトレジストをマスクにしたウェッ
トエツチングと、それに続くドライエツチングを行うこ
とにより、断面が階段状の配線を形成することができる
。従って、第１層目配線上に絶縁膜を介して形成される
第２層目配線の段切れを防止できる効果がある。As explained above, in the present invention, when forming the first layer, wet etching is performed using a photoresist with a predetermined pattern as a mask, followed by dry etching to form interconnections having a stepped cross section. be able to. Therefore, it is possible to prevent breakage of the second layer wiring formed on the first layer wiring via the insulating film.
また、階段状の断面形状を持つ第２層目の形成に際して
、最も手数を要する露光工程が一回で済むので、製造工
数が著しく低減し作業能率が向上する。かつ露光工程が
一回でよいため、これに基ずく欠陥が生じにくく、しか
も従来の二度のマスク合せが一度で済むのでバタンずれ
が起らず、高精度に階段状断面の配線が形成できる効果
がある。Further, when forming the second layer having a step-like cross-sectional shape, only one exposure step is required, which is the most labor-intensive step, so the number of manufacturing steps is significantly reduced and work efficiency is improved. In addition, since only one exposure process is required, defects based on this are less likely to occur.Furthermore, because the conventional two-mask alignment process is completed once, there is no button shift, and wiring with a stepped cross section can be formed with high precision. effective.
また、ウェットエツチング量を制御することによって、
階段状のステップ幅ｄをサブミクロンに狭くすることが
可能となり、各種多層配線のＷ１細パタン化が可能とな
る。In addition, by controlling the amount of wet etching,
It becomes possible to narrow the stepped step width d to submicron, and it becomes possible to make W1 fine patterns of various multilayer wirings.
第１図（Ａ）〜（Ｅ）は本発明の実施例の各工程断面図
、第２図（Ａ）、（Ｉｔ）は従来例の各工程断面図、第
３図（人）、（Ｉｔ）は改良された従来例を示す図で、
階段状断面の配線を形成する各工程断面図である。
１・・・半導体基板、２・・・絶縁膜、３・・・第１ア
ルミニウム配線層、３ａ・・・第１アルミニウム配線、
４・・・層間絶縁膜、４ａ・・・層間絶縁膜肩部、５・
・・第２アルミニウム配線、６・・・ホトレジスト層、
６ａ・・・露光部、６ｂ・・・未露光部、６ｃ・・・ホ
トレジスト、７・・・ホトマスク。Figures 1 (A) to (E) are cross-sectional views of each process in the embodiment of the present invention, Figures 2 (A) and (It) are cross-sectional views of each process in the conventional example, and Figures 3 (person) and (It). ) is a diagram showing an improved conventional example.
FIG. 3 is a cross-sectional view of each step of forming wiring with a stepped cross section. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... First aluminum wiring layer, 3a... First aluminum wiring,
4... Interlayer insulating film, 4a... Interlayer insulating film shoulder, 5.
...Second aluminum wiring, 6...Photoresist layer,
6a...Exposed area, 6b...Unexposed area, 6c...Photoresist, 7...Photomask.
Claims (1)
らなる所定パターンのエッチング用マスクを形成し、該
マスクを用いて前記配線層を所定の膜厚だけウェットエ
ッチングにより除去し、次いで該マスクをそのまま用い
て前記ウェットエッチングの際残した配線層膜厚をドラ
イエッチングにより除去し、階段状の断面形状を有する
配線を形成することを特徴とする半導体装置の製法。An etching mask with a predetermined pattern made of a photoresist layer is formed on the wiring layer formed on the semiconductor substrate, and the wiring layer is removed by wet etching to a predetermined thickness using the mask, and then the mask is left as it is. A method for manufacturing a semiconductor device, characterized in that the wiring layer thickness remaining during the wet etching is removed by dry etching to form a wiring having a step-like cross-sectional shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30522288A JPH02151033A (en) | 1988-12-01 | 1988-12-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30522288A JPH02151033A (en) | 1988-12-01 | 1988-12-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02151033A true JPH02151033A (en) | 1990-06-11 |
Family
ID=17942512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30522288A Pending JPH02151033A (en) | 1988-12-01 | 1988-12-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02151033A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009260322A (en) * | 2008-03-28 | 2009-11-05 | Semiconductor Energy Lab Co Ltd | Method of fabricating semiconductor device |
-
1988
- 1988-12-01 JP JP30522288A patent/JPH02151033A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009260322A (en) * | 2008-03-28 | 2009-11-05 | Semiconductor Energy Lab Co Ltd | Method of fabricating semiconductor device |
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