JPH08181115A - Method of manufacturing integrated circuit - Google Patents

Abstract

PURPOSE: To flatten the irregularities of a conductor film in arbitrary size and shape. CONSTITUTION: After the formation of Nb electrodes 1A, 2B in different width on an Si substrate an SiO2 film 3 is formed so as to form the first photoresist film 4A in the same film thickness so that the Nb electrodes 2A, 2B using as an inversion masks of the Nb electrode patterns. Next, after the formation of the second photoresist film 4B, the first photoresist film 4A is formed by etch-back step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor and a superconducting integrated circuit, and more particularly to a method for flattening an interlayer insulating film by etching back.

[0002]

2. Description of the Related Art With the high integration and miniaturization of circuits, disconnection of wiring and short circuit between wirings due to uneven steps on the element surface have become a serious problem. For this reason, eliminating uneven steps is an important issue in integrated circuit manufacturing technology. As a method for this, the planarization method by etchback is expected to be a very promising technology, and currently active research and development in various fields. Is being done. This will be described below with reference to the drawings.

FIG. 2 is a cross-sectional view for explaining a conventional flattening method by etching back in the order of steps. Particularly, a flattening step in a superconducting integrated circuit, that is, Nb (Niobium-containing superb) having a different size as a pattern to be flattened. This is a case where the concavities and convexities due to the (conductor) electrode are flattened by the SiO ₂ film.

First, as shown in FIG. 2A, Nb electrodes 2A and 2B having different sizes are formed on a Si substrate 1.
The size of the Nb electrode is, for example, 20 μm for the Nb electrode 2A.
m, the film thickness is 500 nm, the width of the Nb electrode 2B is 2 μm,
The film thickness is 500 nm, and the distance between the Nb electrodes is 5 μm. Next, as shown in FIG. 2B, the Nb electrodes 2A and 2B are formed.
The SiO ₂ film 3 having a film thickness equal to or larger than the above is formed on the entire surface of the substrate. Then, an organic film made of a photoresist is spin-coated on the entire surface of the substrate and baked to form a film shown in FIG.
A photoresist film 4 having a relatively flat surface as shown in (c) is formed. Then, the photoresist film 4 and the SiO ₂ film 3 are etched under the same etching rate to flatten the SiO ₂ film 3 as shown in FIG. 2D.

Through the above steps, the initial step difference of the insulating film can be reduced and a relatively flat structure can be realized.

[0006]

However, according to the above-described conventional flattening method by the etch-back, good flattening is possible when the width of the flattened pattern conductor film is about several microns or less. However, when the width of the conductor film is larger than this and the conductor films are separated by several microns or more, as shown in FIG. 2C, the upper surface of the photoresist film 4 is good. The flatness could not be obtained. The flatness of the photoresist film 4 largely depends on the pattern width of the conductor film, and flatness is hardly obtained with a pattern having a width of 10 μm or more. As a result,
As shown in (d), the Nb electrode 2 having a small pattern width
The upper surface of B is exposed, but Nb has a large pattern width.
Since the upper surface of the electrode 2A is not exposed, there is a problem that it is not possible to perform uniform flattening.

An object of the present invention is to provide a method of manufacturing an integrated circuit, which can eliminate such size dependency of a conductor film and easily flatten the unevenness due to the conductor film having an arbitrary size and shape. To do.

[0008]

A method of manufacturing an integrated circuit according to the present invention comprises a step of forming a plurality of conductor films having different widths on a substrate, and a step of forming a conductor film on the entire surface including the conductor film rather than the conductor film. A step of forming a thick insulating film, a step of forming a first organic film having the same thickness as that of the conductor film in a concave region on the insulating film other than an upper portion of the conductor film, the first organic film Forming a second organic film on the entire surface including the film, and etching at least the first and second organic films under the condition that the etching rates for the insulating film and the first and second organic films are equal.
And a step of removing the organic film.

[0009]

According to the present invention, after forming the insulating film having a film thickness equal to or larger than that of the conductor film, the first organic film having the same film thickness as the conductor film is formed in the concave portion of the insulating film. The unevenness can be formed only in the groove between the convex portion of the insulating film and the first organic film. The width of this groove can be set to a substantially constant small value (1 μm or less) regardless of the size and shape of the conductor film that is the pattern to be flattened. The organic film can be easily formed. As a result, uniform and good planarization can be performed on the conductor film having an arbitrary size and shape by etching back.

Further, the first organic film formed in the concave portion of the insulating film can be easily formed by using a reversal mask of a conductor film or a negative resist by an ordinary exposure technique. As described above, since the pattern formed in the concave portion of the insulating film is the organic film, it can be easily formed by a normal exposure technique.

[0011]

Next, the present invention will be described with reference to the drawings. 1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. This embodiment shows a flattening step used in the manufacturing process of a superconducting integrated circuit, that is, a step of flattening an Nb electrode which is a superconductor with a SiO ₂ film.

First, as shown in FIG. 1A, a thickness 500
An electrode film made of Nb of nm is formed on the Si substrate 1 by RF magnetron sputtering, an etching mask made of photoresist for defining the size of the pattern to be flattened is formed by a normal lithography technique, and dry etching is performed. Nb electrodes 2A and 2B having different widths are formed. The line width of the Nb electrode 2A is 20 μm.
The line width of B is 2 μm, and the distance between the Nb electrodes is 5 μm.

Next, as shown in FIG. 1B, SiO ₂ having a film thickness equal to or larger than the film thickness of the Nb electrodes 2A and 2B is formed on the entire surface of the substrate.
A film (film thickness 700 nm) 3 is formed.

Next, as shown in FIG. 1C, in the concave portion of the SiO ₂ film 3, a reversal mask of the Nb electrode (an exposure mask for lithography, black and white of the exposure mask used when the Nb electrode pattern was formed is reversed). Exposure mask manufactured by
By using a normal lithography technique, the Nb electrode 2
A first photoresist film 4A having the same film thickness as A and 2B is formed. As a result, the uneven step is only a small groove between the convex portion of the SiO ₂ film 3 and the first photoresist film 4A.

Next, as shown in FIG. 1D, a photoresist is spin-coated on the entire surface of the substrate and baked (for example, 120 ° C.) to form a second photoresist film 5 having a flat surface.

Next, as shown in FIG. 1E, the first photoresist film 4A and the second photoresist films 4B and S are formed.
Etching is performed until the upper surfaces of the Nb electrodes 2A and 2B appear under the condition that the etching rates of the iO ₂ film 3 are equal. The end point of etching can be detected by detecting the upper surface of the Nb electrode using emission analysis or the like. As the etching, for example, reactive ion etching using a mixed gas of CHF ₃ and O ₂ (gas pressure 3 Pa, high frequency power 1
00W) can be used.

As described above, according to the present embodiment, it is possible to uniformly perform good planarization with respect to the unevenness of the Nb electrode having an arbitrary width and shape with the upper surface of the Nb electrode exposed. effective. After the flattening, a conductive layer such as a wiring is directly formed, or an insulating film having a certain thickness is formed and then a conductive layer such as a wiring is formed, so that a multilayer structure can be easily realized. When a conductive layer such as a direct wiring is formed, the upper surface of the Nb electrode is already exposed, so that contact with the upper wiring can be easily obtained. In this embodiment, the etching back is performed until the upper surface of the Nb electrode is exposed. However, by forming the SiO ₂ film 3 to be thicker, even if the etching is finished without exposing the upper surface of the Nb electrode. A flat structure can be realized.

In the above embodiment, one manufacturing process of the superconducting integrated circuit is shown as an example. Therefore, although Nb which is a superconducting material is used as the conductor, A1 and Cu which are generally used in the semiconductor integrated circuit are used. , Polysilicon and alloys thereof may be used. Further, as the insulating film, SiO ₂ formed by the sputtering method is used.
It is also possible to use any insulating film such as O ₂ , SiO by vapor deposition, and MgO by sputtering.

Further, in the above embodiment, the inversion mask of the Nb electrode pattern is used for forming the first photoresist film 4A. However, the same exposure mask used at the time of forming the Nb electrode has a different polarity (for example, photoresist). If a positive photoresist is used when forming the Nb electrode, the first
Even if a negative photoresist is used when forming the photoresist film 4A, the first photoresist film 4A can be easily formed by a normal exposure technique, and the same good planarization can be performed. I can. Although the photoresist film is used as the second organic film, the same effect can be obtained even if any organic film is used as long as it is an organic film having good flatness at the time of coating, such as polystyrene. it can.

[0020]

As described above, according to the present invention, after the insulating film is formed on the conductor film, the first organic film is formed only in the concave portion of the insulating film, and then the second organic film is formed on the entire surface. The surface is completely flattened to form a film. Therefore, there is an effect that the unevenness due to the conductor film can be completely flattened by etching the first and second organic films and the insulating film at a constant rate.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional technique.

[Explanation of symbols]

1 Si Substrate 2A, 2B Nb Electrode 3 SiO ₂ Film 4 Photoresist Film 4A First Photoresist Film 4B Second Photoresist Film

Claims (2)

[Claims] 1. A step of forming a plurality of conductor films having different widths on a substrate, a step of forming an insulating film thicker than the conductor film on the entire surface including the conductor film, and a step of forming the conductor film. A step of forming a first organic film having the same film thickness as the conductor film in the concave region on the insulating film other than the upper part, and a step of forming a second organic film on the entire surface including the first organic film And the step of removing at least the first and second organic films by etching under the condition that the etching rates of the insulating film and the first and second organic films are equal to each other. Manufacturing method. 2. The method for manufacturing an integrated circuit according to claim 1, wherein the first organic film is formed by using an inversion mask of the mask used for forming the conductor film.