JPH0214818B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an error correction circuit for an information storage device or the like.

Conventional technology As shown in FIG. 2, this type of device conventionally includes a syndrome calculation circuit 2 that calculates a syndrome from an input encoded code 1, and an error position calculation circuit that calculates the position of an error from this syndrome information. 3 and an error size calculation circuit 4 that calculates the size of an error from the syndrome information and error position information, and a correction circuit 5 that receives the encoded code 1, error position information, and error size information corresponds to the correction circuit 5. So-called error correction was performed by outputting a predetermined information code. At this time, the error position calculation circuit 3 and error magnitude calculation circuit 4 calculate the error position and error magnitude by multiplication and division, respectively. a code conversion ROM 7 that converts information switched to power information; an adder circuit 8 that implements multiplication by adding powers; a subtracter circuit 9 that implements division by subtracting powers; and an adder circuit 8. A selector 10 is provided for switching the output between the subtraction circuit 9 and the subtraction circuit 9 .

Problems to be Solved by the Invention However, with such a configuration, as the number of constituent bits of the encoded code increases, the circuit scale of the addition circuit and subtraction circuit for performing multiplication and division becomes enormous. The problem was that the code conversion ROM was accessed each time to perform multiplication and division, resulting in slow processing speed.

The above problem arises for the following reasons. That is, first, multiplication and division processing necessary for decoding processing is realized by addition and subtraction processing of powers;
Code conversion to perform second power operation
The ROM is accessed every time to derive power information.

The present invention has been made in view of the above problems, and provides an error correction circuit that can perform high-speed decoding processing without increasing the circuit scale of the multiplication and division circuits required for decoding processing. The purpose is to provide

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides an arithmetic circuit with a first selection means and a second selection means, and multiplication processing is performed by a multiplier dedicated to Reed-Solomon codes. , the division process is realized by deriving the inverse element using the inverse element ROM, inputting the inverse element to the multiplier mentioned above, and multiplying the inverse element, so that the error position calculation path and It has a configuration in which multiplication processing and division processing are executed by an error magnitude calculation circuit.

Effects With the above-described configuration, the present invention does not perform multiplication and division processing necessary for decoding processing using conventional addition and subtraction of powers, thereby significantly reducing the increase in circuit scale due to addition circuits and subtraction circuits. In addition, whereas in the past, the code ROM was accessed every time a multiplication or division process was performed, in the present invention, the inverse element ROM is accessed only during a division process.
Furthermore, since the frequency of division processing is much lower than that of multiplication processing, it is possible to significantly increase the decoding processing speed.

Embodiment FIG. 1 shows a schematic configuration of a decoding processing circuit according to an embodiment of the present invention, in which 12 is a syndrome calculation circuit that calculates a syndrome from encoded code 1, and 13 is a syndrome calculation circuit that calculates the error position from the syndrome. 14 is an error size calculation circuit that calculates the size of the error from the syndrome and the error position information; 15 is the corresponding information from the encoded code 1, the error position information, and the error size information. A circuit that outputs a code and corrects an error; 16 is an error position calculation circuit 13 and an error magnitude calculation circuit 14;
18 is a ROM that outputs the inverse element during division processing, and 19 is a selector that switches the input of the multiplier according to multiplication processing and division processing.

The operation of the error correction circuit configured as described above will be explained below. When encoded code 1 in which an error has occurred is inputted by an information storage device or the like, syndrome information depending on the error that has occurred is calculated by the syndrome calculation circuit 12, and based on this syndrome information, the following is performed. Decryption processing will be performed. Next, information representing the erroneous position is calculated by the error position calculation circuit 13 from only the calculated syndrome information, and is input to the error magnitude calculation circuit 14. The error magnitude calculation circuit 14 calculates information representing the magnitude of the error from the syndrome information and the error position information. The arithmetic processing performed by the error position calculation circuit 13 and error magnitude calculation circuit ¹⁴ includes addition processing, multiplication processing,
Although division processing is required, addition processing can be realized with a very simple circuit, so both the error position calculation circuit 13 and the error magnitude calculation circuit 14 have built-in addition circuits. In order to perform multiplication processing and division processing, selectors 16 and 19, inverse element ROM 1
8. Multiplier 17 is required. In the case of multiplication processing, the information output from the error position calculation circuit 13 and the error magnitude calculation circuit 14 passes through the selector 16 and the selector 19, and is input as is to the multiplier 13, where multiplication processing is performed, and the result is an error. It is returned to the position calculation circuit 13 and error magnitude calculation circuit 14. In the case of division processing, it is realized in the form of multiplication of inverse elements, and the information output from the error position calculation circuit 13 and the error magnitude calculation circuit 14 is sent to the selector 16.
After passing through, the signal is input to the inverse element ROM 18, and the output thereof is input to the multiplier 17 to perform division processing. Since the processing of the error magnitude calculation circuit 14 is performed after the processing of the error position calculation circuit 13 is completed, the selectors 16, 19,
A situation in which the inverse ROM 18 and the multiplier 17 are used by the error position calculation circuit 13 and the error magnitude calculation circuit 14 at the same time does not occur. When the error position information and error size information are calculated through the above processing and input to the correction circuit 15, the error in encoded code 1 is corrected based on the error position information and error size information, and is converted into an information code. Output.

Effects of the Invention As is clear from the above description, the present invention uses a dedicated multiplier and an inverse ROM to perform the multiplication and division processing necessary for decoding Reed-Solomon codes. Multiplication processing and division processing can be executed by a common multiplier, and because conventional addition and subtraction of powers is not performed, and there is no need to access code conversion ROM, increases in circuit size are significantly reduced. At the same time, it has the effect of significantly increasing the decoding processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an error correction circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional error correction circuit. 12...Syndrome calculation circuit, 13...Error position calculation circuit, 14...Error magnitude calculation circuit, 1
5... Correction circuit, 16, 19... Selector, 17
... Multiplier, 18 ... Inverse element ROM.

Claims (1)

[Claims] 1. A syndrome calculation circuit that calculates the syndrome of encoded code information, an error position calculation circuit that inputs the syndrome information and calculates error position information, and inputs the syndrome information and the error position information and calculates error magnitude information. a correction circuit that inputs the encoded code information, the error position information, and the error size information to calculate correction information; and the error position calculation circuit or the error size calculation circuit. a first selection means for selecting and outputting either one of the information outputted from the inverter; an inverse element ROM in which an inverse element of a predetermined information is stored in advance; the error position calculation circuit; and the error size. a second selection means that selects the output from the first selection means when the calculation circuit executes multiplication, and selects and outputs the output from the inverse element ROM when the calculation circuit executes division; An error correction circuit comprising a multiplier that multiplies the information output from the second selection means and outputs the result to the error position calculation circuit or the error magnitude calculation circuit.