JPH01157129A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To remarkably reduce the extension of a circuit scale and to perform a fast decoding processing by performing a multiplication processing and a division processing required for a decoding processing by using a dedicated multiplier and an inverse element ROM. CONSTITUTION:When an encoding code 1 having an error is inputted, syndrome information which depends on the error is calculated at a syndrome calculation circuit 15. Next, information representing an error position is calculated by an error position detection circuit 16 based on calculated information, and the information representing the size of the error is calculated at an error size calculation circuit 17. The multiplication processing and the division processing are required in arithmetic processings performed in the circuits 16 and 17, however, in the multiplication processing, the output information of the circuits 16 and 17 are inputted to a multiplier 20 as they are via selectors 19 and 22, and the results are returned to the circuits 16 and 17. In the division processing, the output information of the circuits 20 and 17 are inputted to the inverse element ROM21 via a selector 19, and the output is inputted to the multiplier 20, then, the division processing is performed in a form of multiplication of inverse element. An information code in which the error is corrected is outputted from a correction circuit 18 based on the above processing information.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic device executed in an error correction circuit or the like of an information storage device.

2. Description of the Related Art Conventionally, as shown in FIG. 3, an error correction circuit of an information storage device includes a syndrome calculation circuit 2 that calculates a syndrome from an input encoded code 1, and a syndrome calculation circuit 2 that calculates the position of an error from this syndrome information. It has an error position calculation circuit 3 that calculates the error position, and an error size calculation circuit 4 that calculates the error size from syndrome information and error position information, and includes an encoded code 1, error position information, and error size. Correction circuit 6 inputting information
So-called error correction is performed by outputting a predetermined information code corresponding to the error code. At this time, the error position calculation circuit 3
The error position calculation circuit 3 and error size calculation circuit 4 calculate the error position and error size by multiplication and division, respectively. The calculation circuit 4 includes multipliers ea and ab and a divider 7a, respectively.

7b to perform multiplication or division processing.

However, the configuration shown in FIG. 3 requires two multipliers and two dividers, making the circuit complex and expensive. Therefore, as shown in FIG. 2, in order to perform the multiplication and division required by the error position calculation circuit 3 and the error size calculation circuit 4, a code conversion ROM 11 is provided that converts the information switched by the selector 10 into power information. An addition circuit 12 that realizes multiplication by addition of powers, a subtraction circuit 13 that realizes division by subtraction of powers, and a selector 14 that switches the outputs of the addition circuit 12 and the subtraction circuit 13 are provided to prevent errors. There is an apparatus in which the multiplication and division performed by the position calculation circuit 3 and the error size calculation circuit 4 are executed by a common circuit.

Problems to be Solved by the Invention However, even with this configuration, as the number of bits constituting the encoded code increases, multiplication becomes more difficult.

There are problems in that the circuit scale of the addition circuit and subtraction circuit for performing division is enormous, and that the processing speed is slow because the code conversion ROM is accessed each time to perform multiplication and division.

The above problem arises for the following reasons. That is, firstly, the multiplication and division processes necessary for decoding processing are realized by addition and subtraction processing of powers, and secondly, the code conversion ROM is accessed every time to perform power calculations and the power information is obtained. This is what is being brought out.

The present invention has been made in view of the above-mentioned problems, and is capable of correcting errors that can perform high-speed decoding processing without increasing the circuit scale of the multiplication and division circuits required for decoding processing. The purpose is to provide arithmetic devices used in circuits, etc.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a first selection means for inputting information to select either multiplication processing or division processing, and a first selection means for selecting multiplication processing or division processing. When selected, the information is input to an inverse element ROM that calculates and outputs an inverse element of the information, and when performing multiplication processing, inputs the information output from the first selection means and performs division. When executing the process, a second selection means inputs and outputs the information output from the inverse element ROM, and a multiplier executes a multiplication process on the information output from the second selection means. The multiplication process and the division process are executed by a common multiplier.

Effects of the Invention With the above-described configuration, the present invention does not perform multiplication and division processing necessary for decoding processing, etc., by conventional power-9 addition and subtraction, so that the increase in circuit scale due to addition circuits and subtraction circuits can be greatly reduced. In addition, whereas in the past, the code conversion ROM was accessed every time a multiplication or division process was performed, in the present invention, the inverse element ROM is accessed only during a division process, and moreover, the division process is a multiplication process. Since the frequency of decoding is very low compared to processing, it is possible to significantly increase the decoding processing speed.

Embodiment FIG. 1 shows a schematic configuration of an arithmetic device such as a decoding processing device according to an embodiment of the present invention, and 16 is a symbol for calculating syndromes from encoded code 1. 17 is an error position calculation circuit that calculates the error position from the syndrome; 17 is an error size calculation circuit that calculates the error size from the syndrome and the error position information;
18 is a circuit that outputs a corresponding information code from the encoded code 1, the error position information, and the error size information to correct the error; 19 is the error position calculation circuit 16 and the error size calculation circuit 17; Select which one uses the multiplier 2o, and use the multiplication process or the division process to calculate the inverse element R, which will be described later.
Selector 191 selects output to OM21 or selector 22. R selector 21 outputs the inverse element during division processing.
OM, 22 is a selector that switches the input of the multiplier by multiplication processing and division processing.

The operation of the arithmetic unit in the error correction circuit and the like configured as described above will be described below.

When encoded code 1 with an error is inputted by an information storage device or the like, the syndrome calculation circuit 16 calculates syndrome information depending on the error that has occurred, and performs the following decoding process based on this syndrome information. will be carried out. Next, information representing the erroneous position is calculated by the error position calculation circuit 16 from only the calculated syndrome information, and is input to the error 9 magnitude calculation circuit 17.

The error size calculation circuit 1a calculates information representing the size of the error from the syndrome information and the error position information. The arithmetic processing performed in the error position calculation circuit 16 and the error size calculation circuit 17 includes a Galois field (GF(2)
”) above) is the original addition process.

Although multiplication processing and division processing are required, since addition processing can be realized with a very simple circuit, both the error position calculation circuit 16 and the error size calculation circuit 17 include addition circuits. In order to perform multiplication processing and division processing, selectors 19 and 22, backlight ROM 21, and multiplier 2o are used.
Is required. In the case of multiplication processing, error position calculation circuit 1
e and the information output from the error magnitude calculation circuit 17 pass through the selector 19 and the selector 20 and are directly sent to the multiplier 2.
0 is input, multiplication processing is performed, and the results are returned to the error position calculation circuit 16 and the error size calculation circuit 17. In the case of division processing, it is realized in the form of multiplication of backlight, and the information output from the error position calculation circuit 2o and the error size calculation circuit 17 passes through the backlight R
This is input to the OM 21 and its output is input to the multiplier 20 to perform division processing.The processing of the n error size calculation circuit 17 is performed after the processing of the error position calculation circuit 16 is completed. , the selector 19.degree. 22, the backlight ROM 21, and the multiplier 2o are not used simultaneously by the error position calculation circuit 16 and the error magnitude calculation circuit 17. When the error position information and error size information are calculated through the above processing and input to the correction circuit 18, they are corrected based on the error position information and error size information of encoded code 1 and output as an information code. be done.

Effects of the Invention As is clear from the above explanation, the present invention uses a dedicated multiplier and a backlit ROM to perform the multiplication and division processing necessary for decoding Reed-Solomon codes, thereby improving the efficiency of conventional power Since there is no addition or subtraction of , and there is no need to access the code conversion ROM, it has the effect of significantly reducing the increase in circuit size and significantly increasing the decoding processing speed. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an arithmetic unit in an error correction circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of an arithmetic unit in a conventional error correction circuit. 15...Syndrome calculation circuit, 16...
...Error position calculation circuit, 17...Error magnitude calculation circuit, 18...Correction circuit, 20...
Multiplier, 21... Backlight ROM, 19.22...
····selector. Name of agent: Patent attorney Shigetaka Awano and 1 other person

Claims (1)

[Claims] a first selection means that inputs information and selects either multiplication processing or division processing; and when the first selection means selects division processing, inputs the information and calculates the inverse element of the information; inputting the inverse element ROM to be outputted, and the information output from the first selection means when executing the multiplication process, and inputting the information output from the inverse element ROM when executing the division process. an arithmetic device comprising: a second selection means for outputting the information; and a multiplier for performing multiplication processing on the information output from the second selection means.