JPS6248812A - System of calculating inverse element - Google Patents

System of calculating inverse element

Info

Publication number
JPS6248812A
JPS6248812A JP60188873A JP18887385A JPS6248812A JP S6248812 A JPS6248812 A JP S6248812A JP 60188873 A JP60188873 A JP 60188873A JP 18887385 A JP18887385 A JP 18887385A JP S6248812 A JPS6248812 A JP S6248812A
Authority
JP
Japan
Prior art keywords
register
circuit
inverse
input
inverse element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60188873A
Other languages
Japanese (ja)
Inventor
Mitsuo Oiso
大磯 充夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60188873A priority Critical patent/JPS6248812A/en
Publication of JPS6248812A publication Critical patent/JPS6248812A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724Finite field arithmetic
    • G06F7/726Inversion; Reciprocal calculation; Division of elements of a finite field

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To attain comparatively high speed processing and to improve the processing efficiency such as an error correction code and economy by providing a means using an element as the first input, outputting the square of the input and repeating the square calculation and a multiplication means. CONSTITUTION:When an element A from which an inverse element is to be obtained is set to a register 10, the content of the register 10 is squared by a square circuit 11 and replaced with the preceding content in the register 10. Further, the output of the circuit 11 is inputted to a multiplication circuit 12 and the product with the content of a register 13 is calculated and the result is replaced with the preceding content (1 at first) of the register 13. The value set in the register 13 as the result by repeating the operation above by (m-1) times is the inverse element of the element A. In selecting the unity being the initial input to the circuit 12 as an optional element B, a quotient B/A is obtained as the output in place of the inverse element. Thus, the calculation of the inverse element is processed in comparatively high speed and the processing efficiency such as error correction node and the economy are improved.

Description

【発明の詳細な説明】 〔概 要〕 拡大体G F (2’ ”)の逆元の計算方式である。[Detailed description of the invention] 〔overview〕 This is a calculation method for the inverse element of the extended field GF (2''').

元Aの逆元計算を、m−1回の2乗計算と、該2乗計算
の全出力の積による、単純な制御構成で求めることがで
きる。
The inverse element calculation of element A can be obtained with a simple control configuration using m-1 square calculations and the product of all outputs of the square calculations.

〔産業上の利用分野〕[Industrial application field]

本発明は、拡大体G F (2’″)の逆元の計算方式
拡大体GF(2”)の性質は、よく知られるように、例
えばその各元をmビットの2進数符号に対応させること
により、符号理論の研究に有効に応用されている。
The present invention provides a method for calculating the inverse element of the extension field GF (2''').As is well known, the properties of the extension field GF (2''') are such that each element corresponds to an m-bit binary code. As a result, it has been effectively applied to research on coding theory.

その結果、例えば誤り訂正符号の制御において、しばし
ば拡大体G F (2” )の元の逆元を求める計算が
必要になる。
As a result, in controlling error correction codes, for example, it is often necessary to calculate the inverse element of the extension field G F (2'').

〔従来の技術と発明が解決しようとする問題点〕拡大体
G F (2’ )における逆元の計算方法として、従
来法のような方法が知られている。
[Prior art and problems to be solved by the invention] A conventional method is known as a method for calculating the inverse in the extension field G F (2').

なお、以後の説明における拡大体GF(2”)の元に関
する演算は、元を2を法とする剰余で表される係数を有
する多項式として、多項式間の演算結果を既約多項式を
法とする剰余として表わす方式の演算とする。
In addition, in the following explanation, operations regarding the elements of the extended field GF(2'') are performed using the elements as polynomials having coefficients expressed as remainders modulo 2, and the results of operations between the polynomials being modulo the irreducible polynomial. The calculation is expressed as a remainder.

逆元を求めるべき拡大体G F (2’″)の元をAと
し、第1の方法においては、拡大体c F (2” )
の任意の元Aは、原始光をαとしてαJで表され、n=
2”−1として、α’=1となることから、元Aに原始
光αを繰り返し乗じて、j回の乗算で1を得たとき、即
ちA×α′=1になったときに、逆元I=αjを得る。
Let A be the element of the extension field G F (2'") for which the inverse is to be found, and in the first method, the extension field c F (2")
Any element A of is expressed as αJ, where α is the primordial light, and n=
2"-1, α'=1, so when element A is repeatedly multiplied by primitive light α and 1 is obtained by j multiplications, that is, when A×α'=1, Obtain the inverse element I=αj.

第2の方法では、各元に対する逆元のテーブルを予め準
備し、元Aをアドレスとして、その逆元テーブルを索引
することにより逆元を求める。
In the second method, an inverse element table for each element is prepared in advance, and the inverse element is obtained by indexing the inverse element table using element A as an address.

又、第3の方法では、いわゆるユークリッドの互除法を
使用する。公知のようにこの方法では、既約多項式Fと
元Aとの最大公約数(これは常に1である)をユークリ
ッドの互除法によって求める演算を行い、その過程の各
面を所定の方法で累算することにより逆元を得る。
In the third method, the so-called Euclidean algorithm is used. As is well known, in this method, the greatest common divisor (which is always 1) of the irreducible polynomial F and the element A is calculated using Euclidean algorithm, and each aspect of the process is cumulated using a predetermined method. Obtain the inverse by calculating.

以上の方法において、第1の方法は1〜2″″−1回の
乗算、平均して2@−1回の乗算を要するので、計算に
時間を要する。第2の方法は、単にテーブルの索引のみ
であるので処理時間は短いが、テーフ゛ルのために、少
なくとも(2” −1)  XIビットの記憶容量を要
し、mが大きくなると所要記憶容量の大きさが問題にな
る。
In the above method, the first method requires 1 to 2''-1 multiplications, 2@-1 multiplications on average, and therefore takes time to calculate. The second method requires only a table index, so the processing time is short, but it requires a storage capacity of at least (2" - 1) XI bits for the table, and as m increases, the required storage capacity increases. becomes a problem.

第3の方法によれば、第1、第2の方法の場合のような
計算時間及び記憶容量等の問題は少なくなるが、制御が
比較的複雑であるので、例えばマイクロプロセッサによ
る演算制御で実現することになり、比較的高価になると
いう問題がある。
According to the third method, problems such as calculation time and storage capacity as in the case of the first and second methods are reduced, but the control is relatively complicated, so it can be realized by arithmetic control using a microprocessor, for example. There is a problem in that it is relatively expensive.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は、本発明の原理構成を示すブロック図である。 FIG. 1 is a block diagram showing the principle configuration of the present invention.

図は拡大体G F (2”″)における逆元を計算する
回路の構成を示し、1−+ 、l−z〜1−s−1は2
乗回路、2−1.2−t〜2−s−+ は乗算回路であ
る。
The figure shows the configuration of a circuit that calculates the inverse in the extended field G F (2''''), where 1-+, l-z~1-s-1 is 2
Multiplication circuits 2-1.2-t to 2-s-+ are multiplication circuits.

即ち11個の2乗回路と乗算回路の対の直列接続で逆元
計算方式が構成される。
That is, an inverse element calculation system is constructed by connecting 11 pairs of squaring circuits and multiplier circuits in series.

0作 用〕 2乗回路1−.は図の左から入力される元Aを2乗して
、次に接続する2乗回路1−2及び乗算回路2−1へ入
力する。
0 action] Square circuit 1-. squares the element A input from the left side of the figure and inputs it to the next connected squaring circuit 1-2 and multiplication circuit 2-1.

2乗回路1−2は、入力を2乗した出力、即ちA4を、
2乗回路1−3と乗算回路2−2へ入力する。
The squaring circuit 1-2 outputs an output obtained by squaring the input, that is, A4.
It is input to the square circuit 1-3 and the multiplication circuit 2-2.

乗算回路2−8は、2乗回路1−3の出力であるA2と
、外部からの゛l′入力の積A2を、次の乗算回路2−
2へ入力するので、乗算回路2−tは2人力の積−とし
てA Z X A 4を出力する。
The multiplier circuit 2-8 applies the product A2 of the output A2 of the squaring circuit 1-3 and the l' input from the outside to the next multiplier circuit 2-8.
2, the multiplier circuit 2-t outputs A Z X A 4 as the product of the two human forces.

このようにして、図から明らかなように、乗算回路2−
1からはA2X八4×A8、乗算回路2−4がらはA2
 xA4 xA 8 ×AI &が出力され、このよう
にして、最後の乗算回路2−m−+からは、全2乗回路
の出力の積へ2×A4×A8×−・−・・A g @−
1が出力される。この出力は元Aの逆元に等しい。
In this way, as is clear from the figure, the multiplier circuit 2-
1 to A2x84xA8, multiplier circuit 2-4 is A2
xA4 xA 8 ×AI & is output, and in this way, from the last multiplier circuit 2-m-+, the product of the outputs of the total square circuit is 2×A4×A8×−・−・A g @ −
1 is output. This output is equal to the inverse of element A.

以上のように、簡単な構成の回路により、従来の前記第
3の方法と同等の演算時間によって、逆元の計算が可能
になる。
As described above, the inverse element can be calculated using a circuit with a simple configuration and in the same calculation time as the conventional third method.

〔実施例〕〔Example〕

第1図の構成は、そのま\又、一実施例構成トすること
ができる。第1図によって、入力元Aが11個の2乗回
路1−1〜1−s−1により、累積して2乗されるので
、最終出力はA2″−“となり、その間の2乗出力の積
が、逐次乗算回路2−0〜2−s−+によって計算され
、最終的に乗算回路2−pm−rがら全2乗出力の積A
”XA’XA”X−・・・・・A2”−”を得る。
The configuration shown in FIG. 1 can be used as is or can be configured as an embodiment. As shown in Fig. 1, the input source A is cumulatively squared by the 11 squaring circuits 1-1 to 1-s-1, so the final output is A2''-'', and the squared output between them is The product is calculated by the successive multiplication circuits 2-0 to 2-s-+, and finally the product A of the total square output from the multiplication circuit 2-pm-r
"XA'XA"X-...A2"-" is obtained.

前記のように、拡大体G F (2’″)の任意の元A
は、原始光をαとしてαjで表され、又n・2″I−1
として、α”=1となる。従って任意の元Aのn乗が1
になることは明らかである。
As mentioned above, any element A of the extension field G F (2''')
is expressed as αj, where α is the primitive light, and n・2″I−1
, α”=1. Therefore, the nth power of any element A is 1
It is clear that

こ\で、n−2” −1−1+2+4+8+−・−+2
”−’であるから、AII=AI×八Z xA4へX 
A8 X、−・×A2′″−′=1であり、従って元A
の逆元■は、 I  =1/A =A”XA’xA’x−−−xA”−
’と表すことができる。
Here, n-2" -1-1+2+4+8+-・-+2
“-”, so AII=AI×8Z x Go to A4
A8
The inverse ■ is I = 1/A = A"XA'xA'x---xA"-
'It can be expressed as.

即ち、第1図の回路の最終出力である、前記の全2乗出
力の積は元Aの逆元に他ならない。
That is, the product of the above-mentioned total square outputs, which is the final output of the circuit of FIG.

第2図は他の実施例構成を示すブロック図である。図に
おいて、最初に、逆元を求めるべき元Aがレジスタ10
に設定されると、レジスタ10の内容が2東回allに
よって2乗されて、レジスタ10の以前の内容と置き換
えられる。
FIG. 2 is a block diagram showing the configuration of another embodiment. In the figure, first, the element A for which the inverse element is to be found is in the register 10.
When set to , the contents of register 10 are squared by 2 times all, replacing the previous contents of register 10.

又、2乗回路11の出力は、乗算回路12にも入力され
て、レジスタ13の内容との積が計算され、該積によっ
て、レジスタ13の以前の内容を置き換える。レジスタ
13には、最初に“1′が入力されているものとする。
The output of the squaring circuit 11 is also input to the multiplication circuit 12 and multiplied by the contents of the register 13, which replaces the previous contents of the register 13. It is assumed that "1" is initially input to the register 13.

以上の演算をト1回反復すれば、その結果レジスタ13
に設定される値は、AZ X A 4 x 48 x・
−・x AZ−+、即ち元Aの逆元である。
If the above operation is repeated once, the result will be the register 13
The value set is AZ X A 4 x 48 x・
-.x AZ-+, that is, the inverse element of element A.

以上の説明の、乗算回路への最初の一方の入力である1
′を、任意の元Bとすれば、第1図及び第2図の出力と
して、逆元の代わりにB/Aの商を得ることは明らかで
ある。
In the above explanation, 1 is the first input to the multiplication circuit.
If ' is an arbitrary element B, it is clear that the output of FIGS. 1 and 2 is the quotient of B/A instead of the inverse element.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように、本発明によれば、拡大
体G F (2’″)における逆元の計算を、比較的簡
単な構成の回路によって、比較的高速に処理することが
できるので、誤り訂正符号等の処理効率及び経済性を改
善するという著しい工業的効果がある。
As is clear from the above description, according to the present invention, the calculation of the inverse element in the extension field G F (2''') can be processed at relatively high speed using a circuit with a relatively simple configuration. , has a significant industrial effect of improving the processing efficiency and economy of error correction codes and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理構成ブロック図、第2図は本発明
の一実施例構成ブロック図である。 図において、
FIG. 1 is a block diagram of the principle structure of the present invention, and FIG. 2 is a block diagram of the structure of an embodiment of the present invention. In the figure,

Claims (1)

【特許請求の範囲】 有限体GF(2)のm次の拡大体GF(2^m)の元の
逆元計算に際し、 該元を最初の入力として、該入力の2乗を出力し、該出
力を次の入力として2乗計算をm−1回反復する手段(
1−_1〜1−_m_−_1)を有し、該2乗計算の全
出力の積によって逆元を求めるように構成されているこ
とを特徴とする逆元計算方式。
[Claims] When calculating the inverse element of the m-th extension field GF(2^m) of the finite field GF(2), the element is used as the first input, the square of the input is output, and the square of the input is output. A means of repeating the square calculation m-1 times using the output as the next input (
1-_1 to 1-_m_-_1), and is configured to obtain an inverse element by the product of all outputs of the square calculation.
JP60188873A 1985-08-28 1985-08-28 System of calculating inverse element Pending JPS6248812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60188873A JPS6248812A (en) 1985-08-28 1985-08-28 System of calculating inverse element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60188873A JPS6248812A (en) 1985-08-28 1985-08-28 System of calculating inverse element

Publications (1)

Publication Number Publication Date
JPS6248812A true JPS6248812A (en) 1987-03-03

Family

ID=16231366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60188873A Pending JPS6248812A (en) 1985-08-28 1985-08-28 System of calculating inverse element

Country Status (1)

Country Link
JP (1) JPS6248812A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02155314A (en) * 1988-12-08 1990-06-14 Toshiba Corp Inverse element calculator on finite
EP0782070A1 (en) * 1995-12-28 1997-07-02 Daewoo Electronics Co., Ltd Finite field inverter
FR2754616A1 (en) * 1996-10-11 1998-04-17 Sgs Thomson Microelectronics Division of elements in Galois field
JP2008114805A (en) * 2006-11-07 2008-05-22 Yuhshin Co Ltd Air conditioning control device for vehicle

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022905A (en) * 1983-07-15 1985-02-05 Nippon Riken Kk Washing method of semipermeable membrane module

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6022905A (en) * 1983-07-15 1985-02-05 Nippon Riken Kk Washing method of semipermeable membrane module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02155314A (en) * 1988-12-08 1990-06-14 Toshiba Corp Inverse element calculator on finite
EP0782070A1 (en) * 1995-12-28 1997-07-02 Daewoo Electronics Co., Ltd Finite field inverter
FR2754616A1 (en) * 1996-10-11 1998-04-17 Sgs Thomson Microelectronics Division of elements in Galois field
US5890800A (en) * 1996-10-11 1999-04-06 Sgs Thomson Microelectronics Method and device for the division of elements of a Galois field
JP2008114805A (en) * 2006-11-07 2008-05-22 Yuhshin Co Ltd Air conditioning control device for vehicle

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