JPH0214796B2 - - Google Patents
Info
- Publication number
- JPH0214796B2 JPH0214796B2 JP62195440A JP19544087A JPH0214796B2 JP H0214796 B2 JPH0214796 B2 JP H0214796B2 JP 62195440 A JP62195440 A JP 62195440A JP 19544087 A JP19544087 A JP 19544087A JP H0214796 B2 JPH0214796 B2 JP H0214796B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- zirconium
- polyimide
- copper
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052726 zirconium Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052802 copper Inorganic materials 0.000 claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 60
- 239000004642 Polyimide Substances 0.000 abstract description 26
- 229920001721 polyimide Polymers 0.000 abstract description 26
- 239000000919 ceramic Substances 0.000 abstract description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 239000010931 gold Substances 0.000 abstract description 4
- 238000005219 brazing Methods 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract description 3
- 238000005304 joining Methods 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/032—Organic insulating material consisting of one material
- H05K1/0346—Organic insulating material consisting of one material containing N
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12736—Al-base component
- Y10T428/12743—Next to refractory [Group IVB, VB, or VIB] metal-base component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12771—Transition metal-base component
- Y10T428/12806—Refractory [Group IVB, VB, or VIB] metal-base component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
- Y10T428/12771—Transition metal-base component
- Y10T428/12861—Group VIII or IB metal-base component
- Y10T428/12903—Cu-base component
Abstract
Description
【発明の詳細な説明】
A 産業上の利用分野
本発明は、多層薄膜金属構造体にジルコニウム
を使用することに関連する。より詳しくは、ジル
コニウムを、セラミツクまたはポリイミド構造体
と、銅またはアルミニウム層の間の接着層として
使用することに関する。DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION The present invention relates to the use of zirconium in multilayer thin film metal structures. More particularly, it relates to the use of zirconium as an adhesive layer between ceramic or polyimide structures and copper or aluminum layers.
B 従来技術
VLSIに向けて集積回路密度が高まるにつれて、
入出力(I/O)線及び結線密度の増大により多
層チツプ・パツケージング技術にきびしい要求が
課せられるようになつてきた。各々が高いI/O
端子密度をもつ多数の集積回路(IC)チツプを
相互接続するためには、リード線のピツチが非常
に小さい微細かつ精密なパターンを形成する能力
が、将来のVLSIパツケージング技術の成功にと
つて次第に重要になりつつある。B. Prior art As integrated circuit density increases towards VLSI,
Increasing input/output (I/O) lines and interconnect densities have placed stringent demands on multilayer chip packaging technology. each with high I/O
To interconnect large numbers of integrated circuit (IC) chips with high terminal densities, the ability to form fine, precise patterns with very small lead pitches will be critical to the success of future VLSI packaging technologies. It is becoming increasingly important.
現在の厚膜多層セラミツク(MLC)技術は限
界に達してしまつている。というのは、シルク・
スクリーニング技術が、3ミル(0.0762mm)より
も小さい線幅をもつパターンを形成し得ず、焼結
処理が大きい寸法誤差を被るからである。厚膜
MCL技術自体は、先進のVLSIパツケージング技
術の必要条件をみたすには不十分である。 Current thick film multilayer ceramic (MLC) technology has reached its limits. Because silk
This is because screening techniques cannot form patterns with line widths smaller than 3 mils (0.0762 mm) and the sintering process suffers from large dimensional errors. thick film
MCL technology itself is insufficient to meet the requirements of advanced VLSI packaging technology.
チツプ間結線及びI/O相互結線を与えるため
の1つの方法として、慣用的なMLC基体の上面
で薄膜ポリイミド・パツケージを用いるものがあ
る。この構造は、電流を供給し機械的支持を与え
るための基体としてのMLC基板と、チツプ間結
線を与え且つ半導体チツプ接点を薄膜結線層にフ
アン・アウトするためにMLC基板上で処理され
た薄膜層とからなる。さまざまな材料をテストし
た結果として、微細パターニングされた高導電率
銅層の間の低誘電率絶縁層としてのポリイミドの
使用が最良の性能を達成することが分かつてい
る。 One method for providing chip-to-chip and I/O interconnections is to use a thin film polyimide package on top of a conventional MLC substrate. This structure consists of an MLC substrate as a substrate for supplying current and providing mechanical support, and a thin film processed on the MLC substrate to provide chip-to-chip interconnections and to fan out semiconductor chip contacts to the thin film interconnect layer. It consists of layers. After testing various materials, it has been found that the use of polyimide as a low dielectric constant insulating layer between finely patterned high conductivity copper layers achieves the best performance.
しかし、銅を微細結線のために使用する際の問
題として、純粋の銅のポリイミドに対する接着性
が、後の処理に耐え得るほどには十分でないとい
うことがある。それゆえ、銅とポリイミド基板の
間の接着性を高めるための技術が要望される。 However, a problem with using copper for microinterconnects is that the adhesion of pure copper to polyimide is not sufficient to withstand subsequent processing. Therefore, there is a need for techniques to enhance adhesion between copper and polyimide substrates.
C 発明が解決しようとする問題点
この発明の目的は、ポリイミド層に対する銅の
接着性を高めるための多層薄膜メタラージを提供
することにある。C Problems to be Solved by the Invention It is an object of the invention to provide a multilayer thin film metallage for improving the adhesion of copper to polyimide layers.
この発明の他の目的は、銅層をセラミツク層に
接合するための薄膜メタラージを提供することに
ある。 Another object of the invention is to provide a thin film metallage for joining copper layers to ceramic layers.
この発明のさらに他の目的は、セラミツク基板
と、ポリイミド誘電体層によつて隔てられた複数
の薄膜金属層を含む集積回路パツケージを提供す
ることにある。 Yet another object of the invention is to provide an integrated circuit package that includes a ceramic substrate and a plurality of thin film metal layers separated by polyimide dielectric layers.
D 問題を解決するための手段
本発明によれば、ポリイミド層と銅層の間の接
着層としてジルコニウムの薄膜が使用される。ジ
ルコニウムとポリイミドの間の接続強度は、クロ
ムやチタンなどの他の接着層よりも優れている。
さらに、ジルコニウムの場合、ポリイミド表面の
スパツタ・クリーニングは不要である。尚、被膜
付着の開始時点で、ジルコニウムと銅を共時付着
することもできる。D Means for Solving the Problem According to the invention, a thin film of zirconium is used as an adhesive layer between the polyimide layer and the copper layer. The bond strength between zirconium and polyimide is superior to other adhesive layers such as chromium and titanium.
Additionally, with zirconium, no spatter cleaning of the polyimide surface is required. Note that zirconium and copper can also be simultaneously deposited at the beginning of film deposition.
さらに、ポリイミドがパツケージングに不要で
あるような応用技術の場合、ジルコニウムを、セ
ラミツク基板に対する直接の接着層として使用す
ることができる。ジルコニウムに続いて銅が付着
され、その後、反応障壁層と、金などの濡れ可能
な表面層が付着される。このタイプの構造は、ピ
ンのろう付け、チツプ接合、またはワイヤ接続に
使用することができる。 Furthermore, for applications where polyimide is not required for packaging, zirconium can be used as a direct adhesive layer to the ceramic substrate. Following the zirconium, copper is deposited, followed by a reactive barrier layer and a wettable surface layer such as gold. This type of construction can be used for pin brazing, chip bonding, or wire connections.
E 実施例
第1図には多層セラミツク(MLC)基板10
が図示されている。MLCは、複数の薄いセラミ
ツク・シートを、半導体デバイスのための回路接
続を形成するように、整合し焼結されたものとし
て知られている。セラミツクの材料としては、ア
ルミナ・セラミツク(Al2O3)、またはアルフ
ア・コージライトとして知られる形態のガラス・
セラミツク・タイプのものがある。基板10の層
12内には、基板を横切つて電気信号を搬送する
ために使用される導電体が含まれている。これら
の導電体のうちのいくつかはバイア14,16及
び18として図示されており、これらは、基板1
0が他の素子と接続される基板10の上下面の間
で信号を搬送するために使用される。E Example FIG. 1 shows a multilayer ceramic (MLC) substrate 10.
is illustrated. MLC is known as multiple thin ceramic sheets aligned and sintered to form circuit connections for semiconductor devices. Ceramic materials include alumina ceramic (Al 2 O 3 ) or glass in the form known as alpha cordierite.
There is a ceramic type. Contained within layer 12 of substrate 10 are electrical conductors that are used to convey electrical signals across the substrate. Some of these conductors are illustrated as vias 14, 16 and 18, which are connected to the substrate 1.
0 is used to convey signals between the top and bottom surfaces of the substrate 10 to which it is connected to other devices.
バイア14,16及び18との電気的接続を形
成するために、薄いジルコニウム層を含む多層金
属構造体がすぐれた機械的且つ電気的性質を呈す
る。多層メタラージの実際の構造は、相互接続の
タイプに応じて異なるけれども、ジルコニウム層
を使用することはすべての構造に共通している。
例えば、ピン24を、バイア18、設計変更パツ
ド28、及び表面パツド31に接続するために使
用される多層パツド22は4つの層からなる。ま
た、バイア14及び16に接続される補獲
(carture)パツド26は3層金属構造からなる。 To form electrical connections with vias 14, 16, and 18, a multilayer metal structure including a thin zirconium layer exhibits excellent mechanical and electrical properties. Although the actual structure of the multilayer metallage varies depending on the type of interconnect, the use of zirconium layers is common to all structures.
For example, multilayer pad 22 used to connect pin 24 to via 18, redesign pad 28, and surface pad 31 consists of four layers. The carture pad 26 connected to vias 14 and 16 is also comprised of a three layer metal structure.
第1図にはまた、ポリイミド層36,37,3
8からなる3層ポリイミド構造が示されている。
このポリイミド構造は、再分配
(redistribution)、チツプ間結線27及び、基板
10と半導体チツプ34の間の相互接続のために
使用される。さらに、ポリイミド層内の結線は、
1つの半導体チツプを他のチップに直接接続する
ためにも使用することができる。 Also shown in FIG. 1 are polyimide layers 36, 37, 3
A three-layer polyimide structure consisting of 8 is shown.
This polyimide structure is used for redistribution, chip-to-chip connections 27, and interconnections between substrate 10 and semiconductor chips 34. Furthermore, the connections within the polyimide layer are
It can also be used to directly connect one semiconductor chip to another.
4層メタラージ
回路相互接続のためにろう付けまたははんだ付
けされる金属パツドには、ジルコニウム接続層
と、銅層と、反応障壁層と、濡れ可能な層からな
る4層構造が好ましい。4層構造を必要とするタ
イプのパツドの例は、ピン24をろう付けされる
パツド22と、設計変更パツド28と、半導体チ
ツプ34上ではんだボール34が接続される表面
パツド31である。Four-Layer Metallurgy For metal pads to be brazed or soldered for circuit interconnection, a four-layer structure consisting of a zirconium connection layer, a copper layer, a reactive barrier layer, and a wettable layer is preferred. Examples of pads of the type that require a four-layer structure are pad 22 to which pins 24 are brazed, redesign pads 28, and surface pads 31 to which solder balls 34 on semiconductor chips 34 are connected.
第2図を参照すると、パツドをメタライズする
シーケンスは、マスク(図示しない)を、材質が
セラミツクでも、有機物でも、金属でもよい基板
40と整合させることから始まる。使用されるマ
スクのタイプは、金属でも、プラスチツクでも、
ポリマでも、フオトレジストでも、本発明に重要
でなく、一般に使用されている任意のタイプのも
のを使用することができる。もし誘電体層として
ポリイミドを使用しないなら、多層薄膜パツド4
2の形成は、ジルコニウム44の薄層の付着で始
まる。ジルコニウム44は、電子銃蒸着、スパツ
タリング、イオン・プレーテイングまたは他の知
られている技術を用いて付着することができる。
ジルコニウム層44の厚さは好適には30〜2000オ
ングストロームの範囲にある。 Referring to FIG. 2, the pad metallization sequence begins by aligning a mask (not shown) with a substrate 40, which may be ceramic, organic, or metallic. The type of mask used can be metal or plastic.
Any commonly used type, whether polymer or photoresist, is not critical to the invention and may be used. If polyimide is not used as the dielectric layer, a multilayer thin film pad 4
The formation of 2 begins with the deposition of a thin layer of zirconium 44. Zirconium 44 can be deposited using electron gun evaporation, sputtering, ion plating or other known techniques.
The thickness of zirconium layer 44 is preferably in the range of 30 to 2000 Angstroms.
次に、銅、アルミニウムまたは金の層46が、
同一のマスク付着技術を用いて付着される。層4
6もまた上述の付着技術を用いて付着することが
でき、これの好適な厚さは2〜20μmの範囲にあ
る。 Next, a layer 46 of copper, aluminum or gold
Deposited using the same mask deposition technique. layer 4
6 can also be deposited using the deposition techniques described above, and its preferred thickness is in the range 2-20 μm.
後の製造処理の間に層46がはんだまたはろう
と反応するのを防止するために、厚さ0.5〜3.0μ
mの範囲にある反応/拡散障壁層48が付着され
る。この反応障壁層は、ジルコニウム、チタン、
クロム、コバルト、タングステン、モリブデンま
たはニツケルである。 A thickness of 0.5 to 3.0 microns to prevent layer 46 from reacting with solder or wax during subsequent manufacturing processing.
A reaction/diffusion barrier layer 48 in the range m is deposited. This reaction barrier layer consists of zirconium, titanium,
Chromium, cobalt, tungsten, molybdenum or nickel.
最後に、多層膜のはんだまたはろう付けに対す
る濡れ性を高めるために、濡れ可能な表面50が
付着される。これには、0.3〜10μm厚の範囲の金
が有効であることが分かつている。 Finally, a wettable surface 50 is applied to enhance the solder or braze wetting of the multilayer film. Gold in the range of 0.3 to 10 μm thick has been found effective for this purpose.
もしポリイミド層が多層メタラージに使用され
るなら、上述の処理は、追加のステツプを含むよ
うに変更される。第3図を参照すると、基板60
が示されている。基板60はセラミツクでもよ
く、あるいは前もつて付着されたポリイミドの層
でもよい。ポリイミドの層62は約5.0μmの厚さ
でスプレーまたはスピン被覆されたものである。
この層に続いて、可溶性ポリイミドからなる第2
の層64が付着される。層64は、金属付着後の
リフト・オフ層として使用されることになる。 If polyimide layers are used in multilayer metallurgy, the process described above is modified to include additional steps. Referring to FIG. 3, the substrate 60
It is shown. Substrate 60 may be ceramic or may be a predeposited layer of polyimide. Layer 62 of polyimide is sprayed or spin coated to a thickness of approximately 5.0 μm.
This layer is followed by a second layer of soluble polyimide.
A layer 64 of is deposited. Layer 64 will be used as a lift-off layer after metal deposition.
次に、フオトレジスト層66が付着されて乾燥
され、メタライゼーシヨン・パターンがリソグラ
フ的に画成され、現像される。この現像されたフ
オトレジスト・パターンをエツチング・マスクと
して使用することにより、層64及び62が、
O2またはO2/CF4混合ガスを用いた反応性イオ
ン・エツチング・チエンバ中でエツチングされ、
バイア68が形成される。次に、前述した方法で
金属層が付着される。リフト・オフは、基板60
をn−メチルピロリドン(NMP)のような、可
溶性ポリイミド64を溶解し得る溶剤中に浸漬す
ることによつて達成される。 A layer of photoresist 66 is then deposited and dried, and the metallization pattern is lithographically defined and developed. By using this developed photoresist pattern as an etch mask, layers 64 and 62 are
etched in a reactive ion etching chamber using O 2 or O 2 /CF 4 gas mixture;
A via 68 is formed. A metal layer is then deposited in the manner described above. Lift off the board 60
This is achieved by soaking the soluble polyimide 64 in a solvent, such as n-methylpyrrolidone (NMP), which can dissolve the soluble polyimide 64.
もしそのメタラージが前に付着された金属層の
一部を覆うべきならば、追加の多層構造を付着す
る前に、金属表面に形成されているかもしれない
酸化物を除去するために、その表面をスパツタ清
浄化する必要があろう。 If the metallage is to cover part of a previously deposited metal layer, the surface should be It will be necessary to clean the spatter.
第1図に示すような多層結線構造を形成するの
に必要な回数だけこれと同一の処理を繰り返すこ
とができる。 This same process can be repeated as many times as necessary to form a multilayer interconnect structure as shown in FIG.
3層メタラージ
捕獲パツド26などのように、ろう付けまたは
はんだ付けの応力にさらされない金属パツドまた
は線の場合、次の相違点以外は上述の処理に従
う。すなわち、(1)反応障壁層はそれほど厚くなく
ともよく(30〜2000オングストロームで十分であ
る)、(2)濡れ可能な表面層は不要である。その他
の処理ステツプは同一である。For metal pads or lines that are not exposed to the stress of brazing or soldering, such as 3-layer metallage capture pad 26, the process described above is followed with the following differences. That is, (1) the reaction barrier layer does not need to be very thick (30-2000 angstroms is sufficient), and (2) a wettable surface layer is not required. Other processing steps are the same.
F 発明の効果
以上説明したように、本発明によれば、セラミ
ツク、ポリイミドなどの絶縁体と、その絶縁体上
に配置すべき銅などの金属層の間に、接着層とし
てジルコニウムを介在させることにより、金属層
と絶縁体との接着性が高まるという効果が与えら
れる。F Effects of the Invention As explained above, according to the present invention, zirconium can be interposed as an adhesive layer between an insulator such as ceramic or polyimide and a metal layer such as copper to be placed on the insulator. This provides the effect of increasing the adhesion between the metal layer and the insulator.
第1図は、多層ポリイミド構造をもつ多層セラ
ミツク構造の断面図、第2図は、4層メタラージ
の断面図、第3図は、ポリイミド層と金属構造を
もつ基板の断面図である。
44……ジルコニウム層。
FIG. 1 is a sectional view of a multilayer ceramic structure with a multilayer polyimide structure, FIG. 2 is a sectional view of a four-layer metallage, and FIG. 3 is a sectional view of a substrate with a polyimide layer and a metal structure. 44...Zirconium layer.
Claims (1)
ニウム及び銅の群から選択された金属の層と、 (c) 上記金属の層上に付着された、ジルコニウ
ム、チタン、クロム、コバルト、タングステ
ン、モリブデン及びニツケルの群から選択され
た反応障壁層を含む、 多層金属構造体。Claims: 1. (a) a layer of zirconium deposited on a substrate; (b) a layer of a metal selected from the group of aluminum and copper deposited on said zirconium layer; (c) a layer of metal selected from the group of aluminum and copper; A multilayer metal structure comprising a reactive barrier layer selected from the group of zirconium, titanium, chromium, cobalt, tungsten, molybdenum and nickel deposited on a layer of metal.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/919,530 US4751349A (en) | 1986-10-16 | 1986-10-16 | Zirconium as an adhesion material in a multi-layer metallic structure |
US919530 | 1986-10-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63110697A JPS63110697A (en) | 1988-05-16 |
JPH0214796B2 true JPH0214796B2 (en) | 1990-04-10 |
Family
ID=25442258
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62195440A Granted JPS63110697A (en) | 1986-10-16 | 1987-08-06 | Multilayer metallic structure |
Country Status (4)
Country | Link |
---|---|
US (1) | US4751349A (en) |
EP (1) | EP0264134B1 (en) |
JP (1) | JPS63110697A (en) |
DE (1) | DE3781234D1 (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4847445A (en) * | 1985-02-01 | 1989-07-11 | Tektronix, Inc. | Zirconium thin-film metal conductor systems |
JPH0732158B2 (en) * | 1988-04-08 | 1995-04-10 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Multi-layer metal structure for electronic components |
US5183973A (en) * | 1989-08-14 | 1993-02-02 | Santa Barbara Research Center | Flexible cable for interconnecting electronic components |
JP2738600B2 (en) * | 1991-05-27 | 1998-04-08 | 京セラ株式会社 | Circuit board |
US5436412A (en) * | 1992-10-30 | 1995-07-25 | International Business Machines Corporation | Interconnect structure having improved metallization |
JP4428832B2 (en) * | 1999-08-27 | 2010-03-10 | 富士通株式会社 | Metal wiring structure, semiconductor device, and manufacturing method of semiconductor device |
US6800815B1 (en) * | 2001-01-16 | 2004-10-05 | National Semiconductor Corporation | Materials and structure for a high reliability bga connection between LTCC and PB boards |
JP4448702B2 (en) * | 2004-01-30 | 2010-04-14 | 日東電工株式会社 | Method for manufacturing suspension board with circuit |
KR100857365B1 (en) * | 2007-02-28 | 2008-09-05 | 주식회사 네패스 | Bump structure for semiconductor device |
EP2767616A1 (en) * | 2013-02-15 | 2014-08-20 | Alstom Technology Ltd | Turbomachine component with an erosion and corrosion resistant coating system and method for manufacturing such a component |
US10453817B1 (en) * | 2018-06-18 | 2019-10-22 | Texas Instruments Incorporated | Zinc-cobalt barrier for interface in solder bond applications |
US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
IT201900006736A1 (en) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | PACKAGE MANUFACTURING PROCEDURES |
IT201900006740A1 (en) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | SUBSTRATE STRUCTURING PROCEDURES |
US11931855B2 (en) | 2019-06-17 | 2024-03-19 | Applied Materials, Inc. | Planarization methods for packaging substrates |
US11862546B2 (en) | 2019-11-27 | 2024-01-02 | Applied Materials, Inc. | Package core assembly and fabrication methods |
US11257790B2 (en) | 2020-03-10 | 2022-02-22 | Applied Materials, Inc. | High connectivity device stacking |
US11454884B2 (en) | 2020-04-15 | 2022-09-27 | Applied Materials, Inc. | Fluoropolymer stamp fabrication method |
US11400545B2 (en) | 2020-05-11 | 2022-08-02 | Applied Materials, Inc. | Laser ablation for package fabrication |
US11232951B1 (en) | 2020-07-14 | 2022-01-25 | Applied Materials, Inc. | Method and apparatus for laser drilling blind vias |
US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
US11521937B2 (en) | 2020-11-16 | 2022-12-06 | Applied Materials, Inc. | Package structures with built-in EMI shielding |
US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
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JPS4838112A (en) * | 1971-09-10 | 1973-06-05 | ||
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US3423821A (en) * | 1965-03-18 | 1969-01-28 | Hitachi Ltd | Method of producing thin film integrated circuits |
US3461524A (en) * | 1966-11-02 | 1969-08-19 | Bell Telephone Labor Inc | Method for making closely spaced conductive layers |
US3621442A (en) * | 1968-11-07 | 1971-11-16 | Allen Bradley Co | Terminal connection of electronic devices |
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-
1986
- 1986-10-16 US US06/919,530 patent/US4751349A/en not_active Expired - Fee Related
-
1987
- 1987-08-06 JP JP62195440A patent/JPS63110697A/en active Granted
- 1987-10-15 DE DE8787115097T patent/DE3781234D1/en not_active Expired - Lifetime
- 1987-10-15 EP EP87115097A patent/EP0264134B1/en not_active Expired - Lifetime
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Publication number | Priority date | Publication date | Assignee | Title |
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Also Published As
Publication number | Publication date |
---|---|
DE3781234D1 (en) | 1992-09-24 |
JPS63110697A (en) | 1988-05-16 |
US4751349A (en) | 1988-06-14 |
EP0264134A3 (en) | 1988-09-21 |
EP0264134B1 (en) | 1992-08-19 |
EP0264134A2 (en) | 1988-04-20 |
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