JPH02146870A - Facsimile equipment - Google Patents

Abstract

PURPOSE:To process the detection, encoding of a change point and the decoding of a picture signal in parallel and to quicken the processing of an MH code and an MR code determined as the international standards by applying encoding and decoding processing to a picture signal read from document information in parallel for each of plural bits. CONSTITUTION:An MPU IF 2100 interfacing a microcomputer with input and output signals a-1-a-10 and a video bus interface VBUS I/F 2800 interfacing a picture signal with input and output signals d-1-d-10 are connected by using an internal control BUSb and an external control BUSc, Then a control section 2200 comprising a microprogram giving a timing selectively, an arithmetic section 2300 comprising a register group, an address generating section 2400 supplying a video address signal, a table section 2500 having an encoding and decoding function, a detection section 2600 fetching a picture signal in the unit of words and detecting the position of a change pint and a decoding section 2600 decoding the picture signal in the unit of words are connected to these BUSes.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses the MH code (Modified tluffman C), which is defined as an international standard for high-speed facsimile.
ode) and MR code (Modified RE A
The present invention relates to a facsimile machine capable of encoding and decoding (D), an encoding system, and a facsimile machine capable of high-speed processing.

[Conventional technology]

FIG. 1 is a block diagram schematically showing a facsimile. In a facsimile, a reading unit 1000 scans a document and generates five image (Video Data: V D ) signals. The image signal (hereinafter referred to as image signal VD or simply VD) is converted into a code (Codeυord) by the encoding/decoding device 2000, further converted into the frequency of the transmission line band by the modulation/demodulation device 3000, and then sent to the network control device 400o. transmitted over the transmission line. On the receiving side, the code is converted into an image signal using the reverse procedure as described above, and a hard copy is obtained in the recording unit 5000. In FIG. 1, a description of a control section (usually a microcomputer is used) that controls the entire system is omitted.

Journal of the Institute of Image Electronics Engineers '77, VoQ6. Na3 and '78.
Vo Q7. Na1 and Journal of the Institute of Image Electronics Engineers” 80.

VoQ9. As described in documents such as Nα1, the encoding/decoding device 2000 uses international standard MH codes and MR codes.
Symbols are often used.

The MH code is the distance in bit length (Run Length) between two adjacent bit change points (points where the pixel color changes, for example, white or black) on the same scan line.
:RL) as a "code". M
R code calculates the bit change points on two adjacent lines, and calculates the relative change points between the line that has already been encoded and transmitted (reference line) and the line that is about to be encoded (encoded line). This converts the difference in bit positions as a "sign". The conventional encoding/decoding device is
During encoding, multiple lines of memory were prepared to store one bit of the image signal as one word, and the memory was serially scanned to find points of change. Also, during decoding, R
The image signal was serially restored from L using a counter or the like.

[Problem to be solved by the invention]

For this reason, the conventional technology described above has the disadvantage that it requires a large amount of hardware and requires high-speed operation of memory and the like.

Furthermore, since the MH code and the MR code are advanced encoding systems, they are usually processed by a combination of software and hardware using a microcomputer. However, signal processing by software is slow, and there is a limit to processing speed for high-speed encoding. Furthermore, even in the case of a configuration in which processing is performed using only hardware, there is a problem in that the scale of the hardware becomes large and the hardware is dedicated to the processing, resulting in a lack of flexibility. Furthermore, a memory for storing image signals (for example, normally 8 bits is 1
Some devices reduce the amount of hardware by connecting bits (which become words), but the bit change points within a word are
Because it uses a method of serial detection, there still remained problems with speeding up the process.

When processing encoding/decoding processing, separate the image to be processed into processing units (pixels, changing points, lines, pages),
If each separated process is defined as a processing hierarchy, the differences between the present invention and the prior art are shown in FIG.

In conventional devices, hardware performs pixel-by-pixel processing to serially scan image signals and detect change points, and software using a microcomputer handles processing after each change point to generate a code from change point information. There are many examples of this. In this example, although flexibility is high, the burden on the microcomputer is high, and a high-speed line (for example, 48 Kb) is required.
/s or higher), there was a problem that it was difficult to apply.

In addition, even if you try to make minor changes to the encoding and decoding algorithms in image processing, it may be difficult because the hardware is specialized, or the advantages of using a microcomputer (for example, the interface with the bus connection) It has been difficult to build a flexible system that takes advantage of the ease of use, etc.), and it has not been possible to easily provide scalability.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a facsimile machine capable of high-speed processing of encoding and decoding image signals by solving the problems of the prior art described above.

[Means to solve the problem]

In order to achieve the above object, the present invention incorporates means for encoding or decoding an image signal read from one document information in parallel for each plurality of bits.

[Effect]

The present invention detects change points in parallel word by word, with multiple bits of an image signal as one word, and restores the image signal from this change point information, converts the change point information into a code, and converts the code into a change. Convert to point information,
It performs flexible encoding and decoding processing at high speed by specifying operating parameters given by a microcomputer.

〔Example〕

Embodiments of the present invention will be described with reference to FIG. 3 and the following drawings.

FIG. 3 shows a coding/decoding device (Code) according to the present invention.
c) is an overall block diagram. MPU I/F210
0 interfaces with a microcomputer, and signals a-1 to a-10 are input and output. Signal a-1 is the chip select (Chip 5elec) when the microcontroller accesses the Codec.
t: CS) signal. The signal a-2 is a timing (Data 5trobe: DS) signal when data is transferred between the microcomputer and the codec. Signal a-3 is a read/write signal that controls reading or writing from the microcomputer to the Codec.
Write: R/W) signal. Signals a-1 to signal a-3 are connected to the control bus (Co) of the microcomputer board.
Input from ntrol Bus: CB u s ). Signal a-4 is the address (Add
ress: A) A signal. Signal a-1 to signal a-
4, a signal C (referred to as an external control signal) for accessing each register inside the Codec from the microcomputer is generated. Signal a-5 is a signal (Data: D) for exchanging data between the microcomputer and the codec, and is directly connected to the data bus (Data Bus: DBus) of the microcomputer. Signal a-6 is a direct memory access controller (Direct Memory Access
Direct Memory Access (Direct Memory Access), which directly transfers data between an external circuit (usually memory) and the memory within the codec,
DMA Requests
t: DRQT) signal. Signal a-7 is DRQT
DMA Acknowledgment:
DACK) signal. Godec is
When the DRQT signal is output, it waits for the signal to return to the DAC, and after the DACK signal is returned, data input/output is performed in accordance with the timing of the DS signal. The signal a-8 is
Interrupt request (Interrupt) to the microcontroller
Request: I RQ), and is used, for example, when processing for one line is completed. Signal a-9 is the reset (RESET) signal, C
The inside of odec is in its initial state. Signal a-10 is a clock (CLK) signal and serves as a timing source for processing within the Codec.

An example of interfacing with a microcomputer using these signals is usually found in a commercially available LSI that is directly connected to a microcomputer, so further explanation will be omitted here. In this way, Godec has the MPU I/F 2100 and can be directly connected to the microcomputer bus, which has the effect of making the system configuration easy and downsized.

The control unit 2200 is a part that supplies timing to each piece of hardware in the codec via an internal control bus b, and also inputs the status of each piece of hardware to determine what to do next. It is mainly composed of.

This will be explained in detail using FIG. 4.

The arithmetic unit 2300 has an ALU (Arithmeti
c LogicUnit: Consists of an arithmetic/logical operation unit) and a group of registers, etc., and calculates the run leg RL from the address of the change point, calculates the relative difference in position from the change between the reference line and the encoded line, and vice versa. This is the part that does this. This will be explained in detail using FIG. 5.

Video Address:
VA) generation unit 2400 generates a video address (Video Address) for a video memory (V M ) that stores one image signal.
: VA) This is the part that generates the signal d-10. This will be explained in detail using FIG. 6.

The table section 2500 consists of an encoding table and a decoding table for the MH code and MR code, and uses the RL and relative difference from the calculation section 23oO and the control section 220.
This is a part that inputs a mode signal starting from 0 and converts it into an MH code or MR code, and vice versa. This will be explained in detail using FIG. 8 and Tables 1 to 3 of FIG. 9.

The change point detection unit 2600 takes in image signals of reference lines and encoded lines in units of words from a memory that stores multiple bits as one word, and determines the position of a change point within a word (referred to as a bit address). This is the part that detects by parallel processing. This will be explained in detail using FIG. 10 and Table 4 of FIG. 11.

The image signal restoring unit 27oO stores bit addresses of two changing points adjacent to each other on the decoding line, information as to whether there is a difference in word address between the two changing points, and information on the image signal between the changing points. This circuit restores image signals in parallel word by word from color information. This is shown in Figure 12.
This will be explained in detail using FIG. 13 and Table 5.

Video Bus Interface
2800 is an interface signal for a VM that stores image signals, and a video bus (VBUS I/F) 2800.
B u s ) and signals to control D
Signals for transferring image signals are input and output in the MA.

Signal d-1 is VBus when the Codec uses VBus.
Request for the right to use the Bus (Video Bus Re
The request (BRQT) signal is output when there is a device other than the Codec that has the right to use the VBus.

Signal d-2 is a confirmation (Vi
Deo Bus Acknowledgment: B
ACK) signal.

Signal d-3 indicates that the codec's VBus is in use (Vid
This is a signal indicating eo Bus Enable (VBE).

Signal d-4 corresponds to the transfer timing (V
ideo Data 5trobe: VDS
) is a signal.

Signal d-5 is used to transfer data from the Codec to the external device (when data is transferred between the Codec and the external device).
write) or transfer data from an external device to Codac (
Video Bus Read/Write:
VR/W) signal.

The signal d-6 is a request for transferring an image signal to the VM (Tras.
port Data DMA Request: T
D RQ T ) signal.

Signal d-7 is a confirmation (Tran) for the TDRQT signal.
sport data DMA Acknotzled
ge: TDACK) signal.

Signal d-8 is a request to receive one image signal (Re
receive Data DMA Request:
RD RQ T ) signal.

Signal d-9 is a confirmation for RDRQT (RDRQT
Acknowledgment: RD ACK) signal.

Signal d-10 is Codec for video memory VM.
Word address from (Video Memory
lord Address: V A ) signal.

Signal d-11 is a video data bus (Vide) that transfers image signals in units of words between VM and Codac.

Data Bus: VDB u s ).

FIG. 4 is a diagram illustrating the configuration of the control section 2200 in detail. Instruction register
star: I R) 2210 is an external control device (
This is a register that receives macro instructions such as MH encoding instructions from a microcomputer (usually a microcomputer). Matuping ROM (Read
0nly Memory) 2200 generates, from the macroinstruction stored in the instruction register 1R2210, the start address of the ROM 2240 that stores the microprogram to decode and execute the macroinstruction. The sequencer 2230 is a microprogram ROM
2240 address, interrupt control,
Performs subroutine control, jump address generation, etc. Pipeline register 2250 is microprogram R
This is a register that stores microinstructions from the OM2240. The output of pipeline register 2250 is supplied to each piece of hardware as an operation command via internal control bus b.

A part of it is also fed back to the sequencer 2230, and the sequencer 2230 is also controlled, for example, by enabling/disabling interrupts. Status Register (Status Register: S R) 2
260 is a register that stores the internal state of the codec, such as the completion state of processing and the data buffer register (
Data Buffer Register: D
BR) Notifies the microcontroller of the ready status of the 2280. System Control Register:
SCR) 2270 is a register that stores signals that control the Codec system, and is written by the microcomputer. For example, this controls whether the codec monopolizes the VBus, puts the codec in a wait state, and controls whether processing is performed in units of one line or in units of multiline (Page Mode). Done at the register. Multiplexer (MP
X) 2290 is.

The codec is in an idle state (there is no processing to do),
This switch connects a part of the external control bus C to the internal control bus b in the Wait state, and connects the signal from the pipeline register 2250 to the internal control bus b in other states. This allows the microcomputer to access the registers in Codac that are controlled by internal control bus b.

DBR2280 connects VDBus signal d-11 and DBu
This is used to transfer data between the IR2210 and the system bus (System bus).
When receiving a data transfer command between Bus: 5Bus) and VBus, for example, when transferring from VBus to 5Bus, image signal VD is set to DBR2280 and 5R2
260's DBR ready flag to notify the microcontroller. The microcomputer reads DI'1R2280 to obtain VD. The same applies when the transfer direction is reversed. This operation will be explained in detail later.

In this way, since the control section 2200 uses a microprogramming control method, flexible processing is possible, and since the timing is centrally controlled in this section, L
This has the effect that the design at the time of SI is easy.

FIG. 5 shows a detailed explanation of the calculation unit 23oO. The register file 2310 is, for example, a 2-port RAM.
(2Port Random Access Memo
ry), etc., and stores various signals.

Hereinafter, the explanation will be made assuming that 1 word = 1 byte. The register file 2310 contains a virtual address register multichannel (Virtual A
ddress Register Achannal
: VARA), virtual address register B channel (VARB) which is the address of the reference line, line (
virtual address register C, which is the address of the transfer line)
A temporary storage address register A (Temporal Address Regi) that stores the channel (VARC), the position of the encoded line or the change point of the encoded line.
ster A: T A RA), temporary storage address register B that stores the address of the change point of the reference line.
There is (TARB). The addresses stored in these registers are virtual addresses with the starting end of the line as a virtual zero address. It also stores both word addresses and bit addresses. The calculation unit 2300 uses this virtual address for all operations. By adopting the virtual address method, there is an effect that the relative address difference between the change point of the reference line and the change point of the encoded line can be determined at high speed.

Furthermore, since it is sufficient to have a capacity that can store only the address area in the horizontal direction, the register file can be made smaller, and the ALU 2350 can also be made smaller. In addition, since both bit addresses and word addresses are stored in one register, the distance between two changing points can be determined quickly in bit units even though the image signal is handled in word units. effective. In addition to this, the register file 2310 includes terminal registers A and B channels that store the number of pixels in one line.
B Channel: TRAB), terminal register C channel (TRC), and horizontal pixel number register (Horizontal) that stores the number of pixels in the horizontal direction of the screen.
WidthRegister: HWR) and the line number register (Lin) that stores the number of lines to be processed.
e Number Register: LNR) and
Minimum Code Length Register that stores the minimum number of code bits for one line.
ister: MCL R) and Codec working register A (General Regis
ter A: GRA), register B (Gene
ral Register B (GRB). Details of how to use these register groups will be given when the microprogram flow is explained.

A latch 232o and B latch 2330 are for latching outputs from the A port and B port of register file 2310. A mask 2341 and B mask 2
342 are A latch 2320 and B latch 233, respectively.
This controls whether to mask the bit address of the output from 0 to zero or to pass the bit address without masking.

The MPX 2344 selects whether the output from the A port of the ALU 2350 (7) is the output of the A5 switch 2320 or the output of the table section 2500. M.P.
X2343 is.

B latch 2330 outputs to B port of ALU2350
8 or 8.

The ALU 2350 operates on data input from the A port and the B port, and outputs A-B, for example. ALUSR2360 is ALU2350
A register that stores the state of the operation result, such as a zero flag, overflow flag, and underflow flag. Equivalence comparator 2370 is a circuit that determines whether the output of ALU 2350 and the output of B latch 2330 are equivalent. For example, it latches the contents of VARA in A latch 2320, latches TRAB in B latch 2330, and
Input the masked output of A latch 2350 to A port of 350.

When you input 8 to the B port and execute (A port + B port) to increment the word address of VARA, you can determine whether it matches TRAB or not, and the line end is Can be judged.

The MPX 2381 selects whether the lower three bits of the data written to the register file 2310 are to be used as the output of the ALtJ 2350 or as the change point bit address from the change point detector 2600. This has the effect that the bit address of the change point can be stored in the register file 2310 at high speed. The MPX 2382 selects whether to write data to the register file 2310 as DBus data or as the output of the ALU 2350. This allows TRAB.

TRC, HWR, LNR, and MCLR can be set as parameters directly from the microcomputer. For this reason, Codec
allows for flexible processing. For example, set the value of TRAB to T
If it is set smaller than the value of RC, a part of the image signal from the reading section can be encoded. A more detailed explanation of these will be given when the microprogram flow is explained.

FIG. 6 explains the video address generation section 2400 in detail. The register file 2410 includes a start address register A (Start
Address Register: SARA
)and.

It consists of a start address register B (SARB) that stores the real word address of the VM at the start end of the reference line, and a start address register C (SARC) that stores the real word address of the VM at the start end of the transfer line. Adder 2
420 is the line start address in the register file and the virtual word address (V
virtual Word Address) to get the VM's real word address (video address: Vid
eo Address). This video address is latched into address latch 2430 and V A
It is output to Bus. Start address (Star
tAddress) and virtual address (Virtual
Any video address can be generated by MPX2450 has register file 241o
It is possible to select whether the data to be written to is a signal on VABUSd-11 or a signal on DBUSA-5. Every time one line of processing is completed,
In a mode in which control is transferred to the microcomputer (called line mode), the start address is directly set by the microcomputer for each line. On the other hand, in a mode that continuously processes the number of lines set in the LNR (called page mode), the microcontroller only receives the start address setting at the beginning of the page, and then the line C every
Page mode processing can be achieved by the odec adding the start address of register file 2410 and the contents of HWR in register file 2310 and storing this as the next start address.

In this case, the microcomputer only sets the start address once per page, and the rest is done by the Codec, which has the effect of reducing the load on the microcomputer. Also, H
By setting appropriate values for WR, LNR, TR, and SAI+, any rectangular area within one screen can be processed at high speed using the Codec. FIG. 7 shows this. In the figure, HW is the width of the screen in the horizontal direction and is set to HWR. LN is the number of lines to be processed and is set to LNR. T is the number of pixels to be processed in one line and is set to TR. SA is the VM at the top of the page
Set in SAR with the start address of .

After that, when receiving a macro command from the microcontroller,
The codec can continuously process the shaded area in FIG.

FIG. 8 explains details of the encoding table section of the table section 2500. The latch 2501 is
It latches the calculation results of the LU 2350. The mode determination circuit 2502 determines the mode at the time of encoding based on the calculation result of the ALU 2350 (for example, when MH encoding is performed, RL is 6
4 or more or less).

Inform the sequencer 2230. Address generation circuit 250
3 is a signal from the internal control bus and a latch circuit 250
An appropriate address for the encoding table ROM 2504 is generated based on the operation result of the ALU latched to 1. The output of the encoding table ROM 2504 is loaded into a shift register 2505, shifted in 1-bit units, and sequentially converted into serial/parallel data.
l:S/P) is sent to converter 2507. S
When 8 bits are generated in /P converter 2507, first in/first out
tOut: FIFO) is written to memory 2508. G of the calculation unit 2300 counts the number of 8-bit codes generated in the S/P converter 2507.
RB and ALt12350. In this way, since it does not have a counter and counts using ALU and registers,
This has the advantage that timing can be centrally managed and timing control is easy.

The termination detection circuit 2506 includes the shift register 25
05 is detected, and this will be explained in detail later. FIFO memory 2508 is for increasing code transfer efficiency. FIF○ memory 2
When the code is set in 508, DRQT is output via the external control bus. If DMAC is connected.

FIFO memory 2508 is safely accessed by DACK. If the DMAC is not connected, the microcontroller directly reads the F1FO memory 2508.
You can get the sign. In this way, the code is directly DB
Since the data is output on the US network, system design is facilitated. Furthermore, since the codes are transferred in parallel, the timing is easy and fast.

Table 1 describes the encoding table ROM 2504. The RL and difference in the address field are ALU235
The operation result of 0 is the address.

The other portions are generated by the address generation circuit 2503 based on signals from the internal control bus.

In this way, since the calculation result of the ALU 2350 directly becomes the address of the table, the encoding table can be drawn at high speed.

Table 2 takes the code (1011), which is an MH code and has an RL of 4, as an example, and shows a method of encoding it using a table, sending it to the S/P converter 2507, and detecting the end of the code with the termination detection circuit 2506. This is to explain. white R
The calculation result that L is 4 (=(100h)) is AL
When obtained from U2350, the address of the table is (00
0000100) z. At this time, table 250
4 contains (10111000000
It contains the data 000)2.

These upper 4 bits are the sign, and the next D9 bit is “1”.
” indicates the end of the code. shift register 2
505 is loaded with this value.

This shift register 2505 is of a type that fills the least significant bit with rOJ when a shift pulse is input. Each time the shift register 2505 is shifted, the most significant bit of the shift register 2505 is shifted to the S/P converter 2507.

Shifting 4 times (10000000000000)2
However, this pattern is detected by the termination detection circuit 250.
6, it is detected as Terminate and the sequencer is notified of this. The number of shifts is counted by the GRA of the arithmetic unit 2300, and is stored in the GRA when the encoding process for one line is completed. The number of fill codes can be controlled by comparing the total number of code bits for one line with the minimum number of code bits of MCLR.

FIG. 9 explains the decoding table section in detail. FIFO 2510 is a code receiving buffer. A parallel/serial (P/S) converter 2511 sequentially converts codes received in 8-bit units to line ends (En
d of Line: EOL) detection circuit 251
2 and the address generation circuit 2513. The counter function necessary for the P/S converter 2511 is executed by the GRB of the calculation unit 2300. For this reason,
A counter with its own timing is not required. E.O.
The L detection circuit 2512 includes a 12-bit S/P converter,
The output of the S/P converter is (000000000001)2
It consists of a gate that detects whether the received code pattern matches EOL or not. E
By independently providing the OL detection circuit 2512, there is an effect that EOL can be detected reliably and at high speed even if a transmission line error occurs and a break in a code word is mistakenly recognized. The address generation circuit 2513 generates an address for the decoding table ROM 2514, and creates the first address of the decoding table ROM 2514 and the next address from the received code and the output of the decoding table ROM 2514. The decoding method uses a tree search method, which is described in detail in Japanese Patent Application No. 174592/1982, so only a brief explanation will be given here using Table 3. The latch 2515 is the decoding table R
This is to temporarily store the output of OM2514.

Table 3 describes the decoding table ROM 2514, and is created to be suitable for decoding using the tree search method. The decoding table ROM 2514 has addresses divided into three main parts. That is, the MH white code part, the MH black code part, and the MR
This is the sign part. The contents of the decoding table ROM 2514 are part of the address to be accessed next when the decoding is not completed, that is, when the code word is in the middle, and when the code word is completed and the decoding is finished, the contents are the information of the code. It is.

The sequencer 2230 searches the decoding table ROM 2514 once per code bit, and learns the meaning of the decoded code from its output. The information of the decoded code is sent directly to the ALU 2350 (7) via the MPX 2344.
) Since it is in the A port, the position of the change point can be determined at high speed.

FIG. 10 explains the change point detection section 2600 in detail. It consists of a reference line change point detector 2610 and an encoded line change point detector 2620, and since these two operations are almost the same, the reference line change point detector 2610
The 6MPX 2614 to be described selects one of data +VD from the VDBus, data VD obtained by inverting the data from the VDBus, and data from the launch 2617. The mask circuit 2616 is M
The data input from PX2614 is transferred to bit address B.
The details of the circuit that fills in "1" up to the bit indicated by A will be explained using FIG. 11. The latch 2617 is.

The output from the mask circuit 2616 is temporarily stored. Priority encoder 2618 is latch 261
This is to detect the position of the lowest rQJ existing in the data input from 7. If [0] exists in the data, the reference line change point flag is set to "1" to notify the sequencer 2230 that a change point exists. Also, rQJ
The position at which ``existed'' is used as the change point bit address in the arithmetic unit 2.
300. Since this bit address is directly input to the register file 2310, there is an effect that the bit address of the change point can be stored at high speed.

Further, this change point bit address is outputted to the mask circuit 2616 via the MPX 2619 as a bit address BA. The MPX2619 receives the B port bit address (B-Po
rt Bit Address) and the change point bit address from the priority encoder 2618. When you want to set the detection start bit address of the change point of the reference line from the bit address of the change point of the encoded line (this (called reference line address return)
Only the B port bit address is selected. This will be explained in detail in the microprogram flow.

Exclusive OR (EXOR) 2611 is the encoding starting point (ao
) and the change point of the reference line (there are bl and bz, bt is the change point of the opposite color to aO to the right of aQ,
b1/bz select whether to detect bl or bz among the changing points of the same color as ao to the right of bl)
It receives the signal and controls l'1PX2614. gate 2
612 is only when the change point flag is "1" and the reference line address return is rQJ.

The OR gate 2613, which uses the input data of the MPX 2614 as the output of the launch 2617, enables the mask circuit 2616 when the change point flag is "1" or the address return is "1". 11th
The figure explains the mask circuit 2616 in detail, including the decoder 2616-1 and the NAND gates 2616-2 to 2.
Consisting of 616-9.

Table 4 shows an example of the operation of this change point detector. As an initial condition, V D = (00111000)
z, ao color=O, bx/bz=o, reference line change point flag=O1 reference line address return 20.

When latching for the first time, EXOR2611 is set based on the initial condition.
Since the outputs of gate 2612 and 2612 are both rO'',
The input data to the mask circuit 2616 is VD. Furthermore, since the mask circuit enable signal E is "0",
The output of the mask circuit 2616 is.

It is simply the inverted version of the input data. Therefore, latch 2
(11000111)z is latched in 617.

Therefore, the output of the priority encoder 2618 is the reference line change point flag=“1” and the reference line change point bit address=3. At the second latching time, the reference line change point flag is "1", so the gate 26
12 becomes "1", and the input data to the mask circuit 2616 is the output data of the launch 2617 (1100011
1) Becomes z. Since the mask circuit enable signal E is "1", the mask circuit 2616 inverts the input data and fills it with "1" up to the bit position indicated by the reference line change point bit address (001111
11) Output 2. Therefore, change point bit address 6 is obtained. The changing point bit address can be obtained by repeating latching in the same manner until there are no changing points. As is clear from the above explanation, this changing point detector can detect the bit address of a changing point at any position within 8 bits with a single latch, and uses a method of checking each bit after latching. This method has the effect of being able to detect change points at a faster speed. Further, since a counter is not used to check the bit address of the change point, all timing control can be performed by the control unit 2200, which has the advantage of being easy to design and suitable for LSI.

FIG. 12, FIG. 13, and Table 5 show the image signal restoration unit 270o.
will be explained in detail.

The image signal restoration circuit 2701 inputs the bit addresses of the restoration start point and end point to the A port and B port from the calculation unit 2300.
It inputs from the bit address of the port, and inputs the word address difference between the restoration start point and end point from the calculation result of ALU2350, and generates restoration data. Figure 13 shows its detailed circuit, and Table 5 shows its truth. This is a value table. What is the word address difference?

Latch the address of the restoration start point in the parachute 232o,
Latch the address of the restoration end point in the B latch 2330,
Turn on A mask 2341 and B mask 2342,
Input these two addresses to ALU2350 and (B-
This can be obtained by determining whether the result of executing A) is zero or not.

In this way, the circuit 2342 that masks the bit address
．． By providing 2343 in the arithmetic unit 2300, the presence or absence of a word address difference can be determined at high speed with a single operation result, even though both bit addresses and word addresses are stored in the file register 2310. effective. FIG. 13 is a detailed circuit diagram of the image signal restoration circuit 2701, which consists of decoders 2701-1 and 2701-2 and an AND gate. The operation of this circuit is as shown in the truth table shown in Table 5.

Table 5 1: Either rQJ or "1" is fine. In other words, if the color of ao is "0", all outputs are "O".
”, and if the color of ao is “1” and there is no word address difference, then if the value of the A port bit address is x and the value of the B port bit address is y, then up to Dx-Dy-1 is assumed to be “1”. , others are rQJ, and if the color of ao is "1" and there is a word address difference, up to D x - D 7 is "1".
", and the others are "0". From this, the restored image signal within a word can be generated by one operation. This has the advantage of being faster and easier to control timing than a system in which each bit is generated using a counter. The -time storage register 2702 stores the most recently restored image signal, and is cleared when one word of the restored image signal is written to the memory. The OR circuit 2703 outputs the output of the image signal restoration circuit 2701 and the temporary storage register 2.
The logical sum of the outputs of 702 is calculated, and thereby the image signals within one word can be restored one after another. Latch circuit 270
4 latches the 1-word restored image signal from the OR circuit 2703 and outputs the restored image signal to vDBus. The restored image signal is written to the VM word by word. As detailed above, the image signal restoration unit 2700
Since the image signal is restored completely in parallel, the image signal can be restored at high speed.

Above, using Figures 3 to 13 and Tables 1 to 5,
The details of the codec's hardware configuration and the outline of its operation have been explained. Next, using Figures 14 to 16, Cod
The operations of ec in various processing modes will be explained using state transition diagrams.

FIG. 14 is a state transition diagram in encoding and decoding processing modes. Sl represents an idle state.

In the Ss state, if a macro command (for example, an MH encoding command) is input after receiving appropriate parameter settings from the microcomputer, the state transitions to -SL. Sl is in a state where a predetermined process is being executed for one line, and the details of the operation at this time will be explained when the microprogram flow is explained.

Processing continues in the Sl state until processing for one line is completed. When processing for one line is completed, if you are not in page mode, turn on the processing end flag and press S+
Return to state. In page mode, move to Sz state, add the contents of SAR and HWR, and add this to SAR.
The start address is updated by storing it in , and the page end is determined by decrementing LNR. If the content of LNR is not zero, the page edge (Page
It is determined that the state is not End) and moves to the Sl state. When at the end of the page, return to Sr. In this way, the microcomputer only needs to issue a macro command once per line or page, so the load on the microcomputer can be reduced.

FIG. 15 is a state transition diagram in line mode when a VM read macro command is issued. This command connects the microcontroller's system bus.

Issued when the microcontroller accesses a VM on the video bus when the video bus is separated. Condition S!
is idle. At this time, when appropriate parameters are set and a VM read command is received from the microcomputer, the state shifts to state Sl.

If the VBus exclusive right exclusive-dec has the SL, the process immediately moves to state S2. If the VBus exclusive right is occupied in state S1, the BRQT signal is output and the BACK signal is waited for. When the BACK signal is returned, the state moves to state S2. In state S2, the contents of SAR and VAR are added to output a video address, VR/W and VDS are output, VD is input from VM, latched to DBH, DBR ready flag is turned on, and BRQT is turned on. It is canceled and the process moves to state S3.

In state S8, DBH is read from the microcomputer or D
Waits for DACK signal input from MAC. When DBR is accessed, turns off DBR ready flag and increments VAR. At this time, the line end (LineEn
If it is d), it moves to Sl, and if it is not the end of the line, it moves to Sl. In this way, the microcomputer can access memory on the VBus via the DBR. Moreover, since the video address is output by the codec, a microcomputer with a small address space can also access a large-scale memory. Furthermore, since the video address is automatically incremented by the Codec, there is an effect that the VM can be accessed at high speed.

FIG. 16 is a state transition diagram when data is transferred between a reading section, a recording section, etc. and a VM. This data transfer is not executed by a macro command from the microcomputer, but by TDRQT or R from the reading section or recording section.
Performed by DRQT. Since these signals enter the sequencer 2230 as interrupts, data transfer is possible even while the operation shown in FIG. 20 or 21 is being executed. State Sr is a state in which the transfer end flag is on. At this time, when the 5ARC receives the setting of the starting address of the VM from the microcomputer, the state shifts to state S1. State Sl is a state in which TDRQT or l11DRQT can be accepted. In state S1, the TDRQT signal or RD
When the RQT signal is input, the process moves to state S2. State S2 has no meaning if the codec has exclusive VBus rights, and the state immediately moves to state S3. Codec
If the VBus exclusive right is not occupied, the BR is in state S2.
It issues a QT signal and remains in this state until a BACK signal is returned. When the BACK signal is returned in state S2, state S3
Move to. In state S3, the TDACK signal or RDA
A CK signal is output to notify the reading section, recording section, etc. of the start of data transfer, and the process moves to state S4. In state S4,
VD by outputting video address, VR/W, and VDS
After transferring, BRQT is released and the process moves to state S5. In state S3, VARC is incremented. At this time, if it is not the end of the line, the process moves to state S1. If it is at the end of the line and not in page mode, the transfer end flag is turned on and the state is S! Return to If it is at the end of the line and in page mode, the process moves to state S6. In state S6, the start address is updated and LNR is decremented. At this time, if the page is not at the end, the process moves to state Sl. If it is the end of the page, the transfer end flag is turned on and the process returns to state Sr. As detailed above,
For example, since data transfer can be performed even during encoding processing, there is an effect that high-speed processing can be performed. Furthermore, since the data transfer is completely parallel transfer, there is an effect that data can be transferred at high speed using a low-speed memory.

Next, the internal operation of the Codec will be explained in more detail using the microprogram flow of MR encoding and decoding processing. First, the MR code system will be briefly explained using FIG. 17.

FIG. 17 explains the MR code system. (
b) explains the definition of change point.

It represents the state of pixels on the reference line and the encoded line.

Pixels with diagonal lines represent black pixels. In the figure, a
o is the encoding start point, al, a2 is the change point of the encoding line, sbo is the point on the reference line directly above ao, bl
represents the change point of the first reference line to the right of bo and of the opposite color to ao, and b2 represents the change point of the first reference line of the same color as ao to the right of bl. MR codes are broadly divided into: The mode is divided into a pass mode (abbreviated as P mode), a vertical mode (abbreviated as V mode), and a horizontal mode (abbreviated as H mode). (b) shows the case of P mode. P mode is a case where bl and b2 appear before al appears. When P-mode encoding is performed, the new ao is immediately below b2.

(b) is an example of vertical mode. This is a case where the mode is not P mode and the absolute value of the distance between al and bl (also called relative address difference or difference) is 3 or less. When the difference between at and bl is "0", it becomes ■ (0) sign, when al is to the left of bs, it is VL (difference) sign, and when al is to the right of bl, it is VR (difference) It becomes a sign. In the case shown, it is encoded as VR(2). After encoding, al becomes ao.

(d) is an example of horizontal mode, not P mode and al
If the difference between and bl exceeds 3, after outputting the H code, ao and 81
MH encode the RL between at and 82, and then encode the RL between at and 82 with M
H encode. After encoding, al becomes the new ao.

Table 6 Table 6 shows the function of each register during MR encoding. VARA stores the virtual word address and bit address of the encoded line currently being scanned.

VARB stores the virtual word address and bit address of the scanning point of the reference line. TARA is a
It stores the virtual word address and bit address of Q or al. TARB stores the virtual word address and bit address of bl. GR
A is for counting the total number of code bits in one line. GR
B is for the 8-bit count of the S/P converter 2507. 5ARA is V that stores encoded line data.
This is the real word address of the scanning start point of M. 5ARB is the real word address of the scan start point of the VM that stores the data of the reference line.

FIGS. 18 to 23 are part of the flow of a microprogram during MR encoding. It is assumed that the terminal has exclusive rights to VBus. When the Codec receives an MR encoding macro command from the microcomputer to the IR 2210, the sequencer 2230 outputs an address for executing process 6101 and starts the MR encoding process. The microprogram ROM 2240 outputs the bit pattern of the microprogram that performs the process 6101 accessed by the sequencer 2230 to the pipeline register 2250,
Processing begins. Processing 6101 is initialization, for example, setting the output of the ALU 2350 to zero, writing the output of the ALU to VARA, and clearing VARA.

The color of ao should be white. In processing 6102, b1
Set to detection mode. This means that the signal b1/bz to the EXOR 2611 is set to O (white=0). Processing 61031? is VARB A latch 232
0, add 5ARB and the output of A latch 2320, latch it to address launch 2430, and add this to VA
Output to Bus, make VR/W signal lead, and connect to VDS
is output, VM is accessed, and VD is latched into the latch 2617.

This series of operations will be referred to as the VD large input of the reference line. Similarly, in process 6104, the VD of the encoded line is input and latched into the launch 2624. Judgment 61
05 is for determining whether or not a change point exists.

Priority encoders 2618 and 2625 notify the sequencer if there is a change point in the input VD. Therefore, the sequencer can determine the presence or absence of a change point and can jump to each processing block. If there is no change point, the process moves to process 6106, and if there is a change, judgment 6109 is made.
d move. Process 6106 increments the word addresses of VARA and VARB. For example, VARA
In this case, latch this to the A latch 2320, turn on the A mask 2341, input this output to the A port of the ALU 2350, input 8 to the B port, execute (A+B), and output the ALU 2360. Write to VARA. As a result, the word address of VARA is incremented and the bit address of VARA is cleared. Also, when VARA is latched into A latch 2320, TRAB is latched into B latch 2330 at the same time.

When VARA is incremented, the equivalence comparator 2370 simultaneously determines whether it is the end of the line.

VARB is incremented in a similar manner.

In determination 6107, the end of the line is determined, and Line E
If it is not nd, that is, if the line end flag of the equivalence comparator 2370 is not turned on, the sequencer returns to process 6103 and repeats the process described above. If it is a line end, the V(0) sign output subroutine is called in process 6108, and then the process moves to line end processing. Line end processing is Fill control, etc., and will be omitted here. In determinations 6109 and 6110, the state of the change point is determined.

If there is a change point only in the encoded line, process 6201
If there is a change point only on the reference line, jump to process 6301, and if there is a change point on both lines, jump to process 6401. In this way, since the video address of the encoded line and the video address of the reference line are output alternately and scanned, even if the encoded line and the reference line exist in the same VM, it is as if the encoded line and the reference line are This has the same effect as scanning simultaneously and at the same relative position. If a method is adopted in which the change point of the encoded line is detected and then the change point of the reference line is detected, the encoding of the pass mode becomes slow. Furthermore, when detecting a changing point on the encoded line after detecting a changing point on the reference line, if b+ exists far to the right of al, encoding will be delayed.

In process 6201, the bit address of the change point of the encoded line is stored. This transfers the VARAO contents to A latch 2
Latch to 320 and 1. To input this to the A port of the ALU 2350, execute A+O) and file register 231.
MPX so that the lower 3 bits input to 0 become the encoded line change point bit address from the change point detection unit 2600.
This can be achieved by controlling 2381 and writing to VARA. As a result, only the bit address of VARA becomes the change point bit address of the encoded line, the word address remains unchanged, and the position of at is stored in VARA. Processing 6202 increments the word address of VAR13. In determination 6203, it is determined whether the reference line is at the end of the line.

If it is the end of the line, the process moves to step 6207 and stores the incremented value in TARB as bl.

If it is not the end of the line, the process moves to process 6204, where the VD of the reference line is input.In 0 determination 6205, it is determined whether bl exists on the reference line. If there is no change point, the difference between al and bz is 8 or more, so we move on to H encoding processing. In this way, since the encoded line and the reference line can be scanned in parallel, it is possible to determine the H mode before detecting the change point of the reference line. If there is a change point, the process moves to process 6206, and the position of bl is stored in TARB. This can be achieved in the same way as when al is stored in VARA. In processing 6208, (bzat=difference)
Execute. This latches VARA into the A latch 2320, latches TARB into the B latch 2330, and turns off the mask to route these outputs to A and B of the ALU 2350.
This is achieved by inputting the command to the port and executing (B-A).

The output of ALυ2350 is latched into latch 2501,
The mode determination circuit 2502 determines whether the difference is 3 or not. If the difference is within 3, the process moves to VL encoding; if the difference exceeds 3, the process moves to H encoding.

If there is a change point only on the reference line in judgment 6110,
The process moves to process 6301. In process 6301, bl is T A
RB Memorize. Processing 6302: Set the TEb2 detection mode. In process 6303, the V of the reference line input in process 6103 is changed by outputting a latch pulse to the latch 2617 of the reference line change point detector 2610.
It is detected whether bl exists in D in addition to bl. This operation will be referred to as intra-word change point detection. This operation has been explained in detail using FIGS. 10 and 11 and Table 4. In determination 6304, it is determined whether bl exists. If bl exists, b before a1
This means that both l and bl exist, and the process moves to P encoding processing. If bl does not exist, the process moves to process 6305. In processing 6305 and processing 6306, the word addresses of VARB and VARA are incremented. In determination 6307, the line end is determined, and if it is the line end, the process moves to process 6319, and if it is not the line end, the process moves to process 6308. Processing 6
308 and processing 6309, the VD of the reference line and the VD of the encoded line are input to the change point detector 2600 and bl
and detect al. If there is no change point, the process moves to process 6305. If there is a change point only on the reference line, b before a1
This means that a change point between l and bl exists, and the process moves to P encoding processing. If a change point exists only in the encoded line, the process moves to process 6313. In process 6313, the bit address of at is stored in V A RA . Processing 6314teVA
By taking the difference between RA and TARB (a+ bt=
Find the difference). In determination 6315, it is determined whether the difference is 3 or less. If the difference is 3 or less, the process moves to VRR encoding processing, and if it exceeds 3, it moves to H encoding processing. If there is a change point in both the reference line and the encoded line in determinations 6310 and 6312, the process moves to process 6316. In processing 6316, V
Store A RA near t and store bl in VARB. In process 6317, (VARB-VARA) is executed to detect the positional relationship between al and bl. If (bl-al) is negative, that is, the ALU 2350 has caused an underflow, it is determined that bl is to the left of al, and the process moves to P encoding processing. If underflow has not occurred, process 63
Move on to 14.

When it is determined in determination 6307 that it is the end of the line, processing 63
Move on to 19. In process 6319, the address at the end of the line is regarded as the position of al, this address is stored in VARA, and (VARA-TARB) is executed to obtain (al bt=difference). If the difference is 3 or less, the VR code deer subroutine is called in process 6327, and then the process moves to line end processing. If the difference exceeds 3, the process moves to process 6321. In process 6321, the code output subroutine is called.

In process 6322, (VARA-TAR, A) is executed to obtain (az-ao=RL). This RL is latch 250
It is latched to 1. In process 6323, the MH code output subroutine is called. In process 6324, the color of ao is inverted. By setting the output of the ALU 2350 to zero in process 6325 and causing the latch 2501 to latch it (R
Create L=O). In process 6326, the MH code output subroutine is called to encode (RL=0), and the process moves to line end processing. If it is determined in determination 6110 that there is a change point in both the encoded line and the reference line, the process moves to process 64o1.

In process 6401, al is stored in VARA, and in process 6402
Store bl in TARB. In processing 6403 (VAR
A-TARB) and calculate (ar-bt=difference). When the difference is zero, the process moves to V(0) encoding processing. If the difference is positive, it means that 81 is present to the right of bl, and therefore it is necessary to detect whether bl is present at 荊 from al. Therefore, the process moves to process 6407, where the b2 detection mode is set, and in process 6408, a change point within the word of the reference line is detected. If there is a change point, the process moves to process 6412, otherwise the process moves to process 6410. In process 6412, bl is VA
RB Memorize. In processing 6413 (VARB-VA
RA) to find (bz at=difference). If the difference is negative, it means that bl exists to the left of al, and the process moves to P encoding processing.

If the difference is not negative, it means that bl exists after al, and the process moves to process 6410. In process 6410, since bl does not exist to the left of al, it can be determined that the mode is not P mode,
Execute (VARA-TARB) to find (ar bt=difference). If the difference is 3 or less, the process moves to VL encoding, and if it exceeds 3, the process moves to H encoding. Judgment 6406
If the difference is negative, this means that bl exists to the right of al, and the process moves to step 6415. In processing 6415, (TARB
-VARA) to obtain (bt-a1=difference). If the difference is 3 or less, the process moves to VR encoding processing, and if it exceeds 3, the process moves to H encoding processing. With the above, V
After completing the part of scanning M to detect a change point and determine the mode, we will now move on to a description of the encoding process for each mode.

The H encoding process starts from process 6501. Processing 650
1 calls the H code output subroutine. Processing 650
2, execute (VARA-TARA) to get (a 1-
ao=RL) is obtained, and this is stored in the encoding table section 25.
It is latched into the latch 2501 of 00. In process 6503, the M H code output subroutine is called. Processing 650
Step 4 inverts the color of ao. In process 6505, the contents of VARA are moved to TARA, and al is stored in TARA. Process 6506 detects change points within the words of the encoded line. If there is a change point, the process moves to process 6513. If there is no change point, the process moves to process 6508. In processing 6508, VARA
Increment the word address of.

At this time, if Lin E++d, the process moves to process 6511.

If it is not the Line End, the process moves to process 6510, where the VD of the encoded line is input, the presence or absence of a change point is detected, and the process moves to process 6507. In process 6511, the point at the end of the line is set to a
As z, execute (VARA-TARA) and (ax-
at=RL). In process 6512, the MH code output subroutine is called and the process moves to line end processing. If a change point exists in determination 6507, the process moves to process 6513.

In process 6513, the position of az is stored by storing the bit address of the change point of the encoded line in VARA. Process 65141', (VARA-TARA) is executed to obtain (ax-at=RL). In process 6514, the MH code output subroutine is called. Processing 6522
Processing 6527 is post-processing to scan the reference line and the encoded line in parallel again and move on to mode determination processing. First, in process 6522, the color of az is inverted.

By moving the contents of VARA to TARA in process 6523, al or az is newly stored as ao.

In process 6524, the contents of TARA are converted to VAR in order to restore the scanning address deviation between the reference line and the encoded line.
By moving to B, the positions of ao and bo are matched.

In process 6525, the b1 detection mode is set. In step 6526, the contents of TARA are latched into the B latch 2330.
The contents of VARB are latched into the A latch 2320, the reference line address return of the reference line change point detector 2610 is turned on, and the VD of the reference line is latched into the latch 2617. As a result, the mask circuit 2616 operates, and B
The VD of the reference line input up to the bit address of launch 2330, that is, the pit address of aO, is masked and latched into latch 2617. This results in a.

A change point directly above bo, that is, to the right of bo can be detected.

The process 6526 has the effect that the scan start addresses of the reference line and the encoded line can be matched bit by bit accurately and at high speed.

In process 6527, a change point detection operation within the word of the encoded line is performed, and the process moves to determination 6105 to start mode determination again. Next, the VLL encoding process will be explained. The VLL encoding process starts at process 6521. In process 6521, a VL code deer subroutine is called, and the process moves to process 6522.

The processes following process 6522 have already been described.

Next, VR encoding processing will be explained. First, process 6531
Call the VR code output subroutine and perform process 6522.
Move to. Process 6522 and subsequent steps have already been described.

Next, the process moves to V(0) encoding processing. First, process 6541
Process 6: Call the v(0) sign output subroutine with
542 and subsequent steps are post-processing for moving on to mode determination processing again. (2) In the case of (0), the scanning points of the reference line and the encoding line match, so no special processing is required to match the scanning points. In process 6542, the color of ao is inverted. In process 6543, the contents of VARA are
4. : By moving, al becomes a new ao.

Process 6544 detects change points within the word of the reference line. In process 6545, a change point within the word of the encoded line is detected, and the process returns to determination 6105 to continue the mode determination process again.

Next, the P encoding process will be explained. In process 6551, the P code output subroutine is called. In processing 6552, V
The location of bz is determined by writing the bit address of bz to the bit address of ARB.

It is stored in VARB as the position of . In processing 6553, V
By moving the contents of ARB to TARA, ao and b
Match O and change the position of bz to a.

It is stored in TARA as . In process 6555, the br detection mode is set, and in process 6556, a change point detection operation in the word of the reference line is performed, and the process returns to determination 6105.

This concludes the explanation of the encoding process for each mode. Next, the code output subroutine of each mode will be explained. All codes are output by operating the coding table section 2500. That is, the address generation circuit 2503 generates a specific address based on the output of the ALU 2350 latched to the launch 2501, that is, RL or the difference, and the mode signal from the control unit 2200 that has made the mode determination, and the encoding table ROM 2504 is accessed. This is realized by Here, the (0) code output subroutine will be explained as an example, and the others will be omitted.

(0) The code output subroutine starts with process 6601. In process 6601, V is applied to the address generation circuit 2503.
(0) Address where the code is stored (1000000
00) Generates 2. In process 6602, the contents of the encoding table ROM 2504 are loaded into the shift register 2505. ■(0) Since the code is defined as "1", the shift register 2505 has (1100000000)
0000)2 will be loaded.

The most significant bit is the v(0) code, and the second bit "1" is for end detection. In judgment 6603, shift register 2
The output of 505 is (10000000000000) z
Terminate (Termi) by detecting whether or not
Termination is determined based on the termination flag from the termination detection circuit 2506 that detects the termination state. Return if finished. If not finished, process 6604
Move to. In process 6604, a shift pulse is output to the shift register 2505 and the S/P converter 2507, and the most significant bit of the shift register 2505, in this case, "
1'' is shifted into the S/P converter 2507. In process 6605, the GRA of the file register 2310 is latched into the A latch 2320, the A mask 2341 is turned off, inputted to the ALU 2350, the ALU 2350 executes (A+1), and this output is sent to the GR.
Increment GRA by writing to A;
Performs a count of the total number of code bits. In process 66o6, G RB , (7) contents are decremented using the same method as in process 6606. GRB is an S/P converter 250
7, it is determined whether an 8-bit code has been generated. In decision 6607, it is determined whether the contents of GRB are zero. If it is zero, it can be determined that an 8-bit code has been generated in the S/P converter 2507, and the process moves to determination 6608.

At decision 6608, it is determined whether FIFO memory 2508 is ready for input. If input is not ready, wait (υa
it). If input is ready, the process moves to process 6609.

In process 6609, the FIFO 2508&, -S/P converter 2507 (7) code 8 bits is loaded, and in process 66
10, input 8 to the B boat of ALU2350, and (○
+B) and writes this output to ORH, setting ORH to 8. Next, the process moves to determination 6603. In determination 6603, in this case, shift register 250
Since the content of 5 is (10000000000000)z, it is determined that the process has ended and the process returns. That's all, M
This concludes the detailed explanation of the microprogram flow of R encoding processing.

Next, regarding the MR decoding process, Table 7 and Figures 24 to 27
This will be explained using figures.

Table 7 explains the function of each register during MR decoding processing. VARA is the virtual word and bit address of the location where the restored data is written to the VM of the decoding line. VARB is the virtual word and bit address of the scan position of the reference line. TARA is a virtual word and bit address of al or am. G.R.B.
is for the 8-bit count of the P/S converter 2511.

5ARA and 5ARB are the real word addresses at the beginning of the decoding line and the reference line, respectively.

TRAB is the number of pixels in one line (in word units).

In parallel with the decoding process, the VD can be transferred between the recording unit and the VM, but this includes VARC.

TRC, 5ARC are assigned. VARC is the virtual word address of the transfer line, and TRC is the number of pixels to be transferred, in units of words. 5ARC is the real word address at the beginning of the transfer line. 5ARA and 5ARC and TR
By arbitrarily choosing the values of AB and TRC, the restored V
Any part of D in word units can be transferred to the recording unit.

24 to 27 are microprograms for MR decoding processing. Processing 7102 and the processing in the range A are the parts that decode the MR code and determine the mode.

Process 7101 is initialization at the beginning of the line. For example, this is processing such as clearing VARA and VARB. In process 7102, the address generation circuit 2513 of the decoding table section shown in FIG. 19 is caused to generate a start address for MR code decoding. Decoding table ROM25
14 has the configuration shown in Table 3, so A
In 0 judgment 7103, in which r 10000000 J occurs in e'' A 1, it is judged whether or not the contents of ORB are zero. If it is zero, it can be judged that there is no code in the P/S converter 2511, and in judgment 7104 If the FIFO 251 is not zero, the process moves to process 7107.
Determine whether a sign exists in 0.

If the code does not exist, wait. If the code exists, the process moves to process 7105. In process 7105, P/S converter 2511
Load the output of FIFO 2510 into . Processing 7106
Then, set 8 to GRB in the same way as in process 6610,
It is stored in the P/S converter 2511 that there are 8 bits of code. In process 7107, a shift pulse is output to the P/S converter 2511, and the first code of the P/S converter 2511 is output to the EOL detection circuit 2512 and the address generation circuit 25.
13. In process 7108, the P/S converter 25
To remember that the sign of 11 has decreased by 1 bit,
Decrement GRB. In determination 7109, EOL is determined. This is performed by EOL detection circuit 2512.

The EOL detection circuit 2512 determines whether the code sequence input from the P/S converter 2511 is roooooooooooolJ.

It can be configured with an S/P converter and a gate. If it is EOL, the process moves to line end processing, and if it is not EOL, the process moves to process 7110. In process 7110, the decoding table ROM 2514
and latches its output into latch 2515. In decision 7111, it is determined whether the code is completed. This is because the decoding table ROM 2514 is configured as shown in Table 3, so the least significant bit of the content of the decoding table ROM 2514 latched in the latch 2515 is 1.
It can be judged by whether it is O or O. If the code is not complete,
The process moves to process 7112. In process 7112, latch 2515
Of the contents of the decoding table ROM 2514 latched in , D l-D 7 is fed back to the address generation circuit 2513 and used as 81 to A7. Next, judgment 71
The process returns to step 03 and continues processing the range indicated by A until the code is completed. When it is determined in the determination 7111 that the code is completed, the decoding table l? The mode of the MR code is determined from the contents of 0M2514, and the process moves to the decoding processing program for each mode.

First, the P decoding process will be explained. In process 7201, the VD of the reference line is input, and the change point b1 to the right of ao is
Detect. This process is the same as the technique detailed when describing process 6526. If a change point exists, the process moves to process 7206. If there is no change point, process 72
Move to 03.

In process 7203, the word address of VARB is incremented. In determination 7204, when the value obtained by incrementing the word address of VARB and the value of TRAB match, that is, the end of the line, the process moves to error processing. If it is not the end of the line, the process moves to process 7205. In process 7205, the VD of the reference line is input, bt detection is performed, and judgment 7 is made.
Return to 202.

If bl is detected, the process moves to process 7206. Processing 7206
Then, a change point bZ in the word of the reference line is detected. If a change point exists in determination 7207, the process moves to process 7211,
If it does not exist, the process moves to process 7208. In processing 7208,
Increment the word address of VARB. In judgment 7209, the end of the line is determined, and if it is the end of the line, the process moves to error processing.

If it is not the end of the line, the process moves to process 7210. Processing 7210
Then, the VD of the reference line is input, bz detection processing is performed, and the process moves to determination 7207. In process 7211, the word address of VARB and the change point bit address of the reference line are TA
Write to RA. In process 7212, the image signal restoration subroutine is called, and the process returns to process 7102. The image signal restoration subroutine is a program that restores the image signal from the position indicated by VARA to the position indicated by TARA, and will be described in detail later. This completes the P decoding process.

Next, v(O) decoding processing will be explained. In processing 7213,
Input the VD of the reference line and detect the change point b1 to the right of aQ. In determination 7214, the presence or absence of a change point is determined. If a change point exists, the process moves to process 7218, and if it does not exist, the process moves to process 7215. In process 7215, the word address of VARB is incremented.

The end of the line is determined in determination 7216, and if it is the end of the line,
The line end is set as bl and the process moves to process 7218.

If it is not the end of the line, the process moves to process 7217. Processing 7217
Then, the VD of the reference line is input, bx detection is performed, and the process returns to determination 7214. If bl exists, the process moves to process 7218, writes the word address of VARB and the change point bit address of the reference line as at to TARA, and processes 7218.
In step 219, an image signal restoration subroutine is called. In process 7220, the color of ao is inverted, and the process returns to process 7102. This completes the v(0) decoding process.

Next, VL decoding processing will be explained. In process 7301, the VD of the reference line is input, and bl to the right of aQ is detected. If a change point exists in judgment 7302, process 7306
If it does not exist, the process moves to step 7303 d. Processing 7
At 303, the word address of VARB is incremented. In determination 7304, the line end is determined, and if it is the line end, the line end is set as bl and the process moves to process 7325. If it is not the end of the line, the process moves to step 7305, and the V of the reference line is
D is input, bl is detected, and the process moves to determination 7302. If there is a change point, the process moves to step 7306, and by storing the change point bit address of the reference line in VARB, the position of bz is stored in VARB. In process 7325, latch 25
The difference between BL and AL lunched on 15 is ^LU235
Input the value of 0 to A port 2, and input the value of VARB to B latch 233.
0, turn off the B mask 2342, and turn off ALU2.
350 and executes (B-A) to obtain (bl-difference=a1), which is stored in TARA. In this way, the output of the decoding table is directly
Since it is included in U2350, there is an effect that the position of at can be determined at high speed. At decision 7326, A
If the calculation result of the LU 2350 is negative, it is determined that there is an error. In determination 7307, (TARA-VARA) is performed, and if the result is negative, it is determined that there is an error. In process 7308, an image signal restoration subroutine is called. In processing 7309, V
By writing the contents of ARA to VARB, a new a.

Match the positions of and bo. In process 7310, the color of ao is inverted, and the process returns to process 7102. This completes the VL processing.

Next, VR decoding processing will be explained. In process 7311, the VD of the reference line is input, and a change point b1 to the right of ao is detected. If the change point exists in the determination 7312, the process moves to process 7315, and if the change point does not exist, the process moves to process 7322.

In process 7322, the line end is determined by 0 determination 7313 in which the word address of VARB is incremented, and if it is the line end, the process moves to error processing. If it is not the end of the line, the process moves to process 7314. In processing 7314, the reference line VD
is input, bl is detected, and the process moves to determination 7312. If a change point exists, in process 7315, the bit address of the reference line change point is stored in VARB. In process 7316, the difference from the decoding table and VARB are added and stored in TARA as al. If the result of the addition is an overflow in determination 7317, the process moves to error processing. If there is no overflow, the image signal restoration subroutine is called in process 7318, and the contents of TARA are converted into VARB in process 7319.
, and match the new ao and bo.

In process 7320, the color of ao is inverted, and the process returns to process 7102. This is the end of the VR decoding process.

Next, H decoding processing will be explained. In process 7401, the address generation circuit 2513 generates a start address for decoding the MH code. If the configuration is as shown in Table 3, if the color of aQ is white, A e ~ A 1 is r 0O
OOOOOOOOJ, and if the color of ao is black, it is rolo
It should be oooooooJ. In process 7402, the area indicated by A is processed to find the MH code. At determination 7403, the D7 bit of the decoding table ROM 2514 latched by the latch 2515 is determined, and if it is "O", the end code (Tet+linatin) is determined.
g Code), and the process moves to process 7406. "1"
Make up code
It is determined as e) and the process moves to process 7404.

In process 7404, the outputs D1 to D7 of the latch 2515 are set to bits 2B to 211 of the RL, and the ALU of the ALU 2350
input to the port, add it to the contents of TARA, and add this to the TA
In 0 determination 74o5 for writing to RA, it is determined whether the added result is an overflow or not, and if it is an overflow, the process moves to error processing, and if it is not an overflow, the process moves to process 7401.

When the end code is detected, the process moves to step 7406, where the outputs D1 to DB of the latch 2515 are inputted to the A port of the ALU 2350 as bits 20 to 26 of RL.

Add the contents of TARA and write the result to TARA. In determination 7407, it is determined whether or not the added result is an overflow. If it is an overflow, the process moves to error processing, and if not, the process moves to process 7408. Processing 740
8 calls the image signal restoration subroutine and performs processing 740.
Step 9 inverts the color of aO. In process 7410, the area indicated by B is processed. In process 7411, the contents of TARA are VA
Move to RB, match new ao and bo, process 7
Moving on to 102. This concludes the explanation of the decoding process in all modes.

Next, the image signal restoration subroutine will be explained.

Here, ao is stored in VARA and ai is stored in TARA.
is memorized. Therefore, it is necessary to use the color aQ from VARA to the position indicated by TARA. In process 7412, the word address difference between VARA and TARA is detected.

This latches VARA into A latch 2320 and TA
Latch RA to B latch 2330 and A mask 2341
and B mask 2342 are turned on, input to ALU 2350, and B-A is executed. If the result is zero, there is no word difference. In this way, since there is a circuit that masks the bit address, there is an effect that the word address difference can be determined at high speed. Also, at this time, since the word difference presence/absence signal and the bit addresses of the write start and end points are supplied to the image signal restoration circuit 2701, the process 7413
By simply outputting a latch pulse to the latch circuit 2704 and temporary storage register 2702, the image signal within a word can be restored at high speed. In judgment 7414, it is determined whether there is a word address difference, and if there is no word address difference, the image signal has been restored to the point al indicated by TARA, and the process returns. If there is a word address difference, the process moves to process 7415. If there is a word address difference, 1
Since the word image signal has been restored to the latch circuit 2704, the output of the latch circuit is converted into (VAR
The image signal is restored to the decoding line by writing to the address indicated by the word address A+5ARA). Processing 7
At 416, the temporary storage register 2702 is cleared. In process 7417, the word address of VARA is incremented. This is done by latching the contents of VARA into the parachute 232o, latching the contents of TRAB into the B latch 2330, turning on the A mask 2341, inputting it to the A port of the ALU 2350, and inputting 8 to the B port of the ALυ 2350 (A+B ) and write the result to VARA, at the same time as the word address of VARA is incremented, the bit address of VARA is cleared and the equivalence comparator 2
This has the advantage that the end of the line can be detected using the 370.

In determination 7418, it is determined whether it is the end of the line. If it is not the end of the line, the process returns to step 7412 and continues the image signal restoration process. If it is the end of the line, the process moves to judgment 7419 and the VARA
It is determined whether or not TARA and TARA match. If they do not match, proceed to error processing; if they match, proceed to line end processing.

This concludes the explanation of the microprogram flow of the MR decoding process.

Figures 28 and 29 show Godec, microcontroller, etc.
This is an example of a facsimile configuration.

FIG. 28 is an example in which the VBus of Codec 2000 and the system bus of microcomputer 8010 are shared. The microcontroller 8010 can be a general-purpose microcontroller such as Intel's 8085 or Motorol's 6800.
0 issues appropriate parameter settings and macro commands to Codac 2000. For example, in the case of encoding processing, a scanning command is first issued to the reading unit 1000. Upon receiving a scanning command from the microcomputer 801o, the reading unit 1000 scans a document and generates an image signal (VD). and C
Output TDRQT to odec2000. Co
dec2000 uses the method explained using FIG.
The VD from the reading unit 1000 is transferred to the video memory (V
M) Transfer to 8020. When the transfer for one line is completed, the Codec 2000 outputs an interrupt request (IRQ) to the microcomputer 801O. In this way, the microcontroller 8010 can process the Codec for I Line once.
Just by setting parameters to 2000, one line of VD can be transferred. In addition, the microcontroller 8010 uses Cod
When a macro command for encoding processing is issued to the EC 2000, the Codec 2000 inputs the VD from the VM, performs the encoding processing, and outputs the code to the DBus of the microcomputer 8010. Microcomputer 8010 stores the code in code memory 8030. Further, the microcomputer 8010 outputs the code in the code memory to the modulation/demodulation device 3000.

In this way, a facsimile transmitter can be easily constructed.

A receiver can also be configured with this system. Furthermore, the system bus of the microcomputer 8010 and the video bus of the Codec are shared. The VM 8020 and the code memory 8030 can be the same chip, which has the effect of reducing the size and cost.

Figure 29 shows the system bus of the microcontroller 8010 and the Cod
This is an example of a system that is separated from the EC 2000 video bus.0 image signals are transferred on the VBus, and codes are transferred on the system bus, which has the effect of enabling high-speed encoding and decoding processing. Also, there is DMA on the system bus side.
C8060 is used, and the code is transferred using this DMAC8060.
Microcontroller 8010
This has the effect of reducing the load on Also, VM80
20 has no relation to the address space of the microcontroller 8010, so it has the advantage of being able to have a large-scale VM without being limited to the 64 kilobyte (K byte) address space that is the general address space of an 8-bit microcontroller. There is 1
For example, the VA room space of the Codec 2000 can be made 16 megabytes (M bytes) simply by making the hardware in the VA generator 2400 a 24-bit configuration.

Although the present invention has been described using an example of a case where the present invention is used in facsimile, any system that handles MH codes, MR codes, or both may be used (for example, it can be applied to an image file system, etc.).

Furthermore, by providing a circuit that generates refresh timing and a register that stores refresh addresses, a refresh RAM can be used in the VM.

〔Effect of the invention〕

According to the present invention, since change point detection, encoding, and image signal restoration can be processed in parallel, a facsimile machine capable of high-speed processing can be realized.

[Brief explanation of the drawing]

Figure 1 is an overall block diagram of a facsimile, Figure 2 is an explanatory diagram of the hierarchical structure of encoding and decoding processing, and Figure 3 is a code diagram.
FIG. 4 is a block diagram of the control section, FIG. 5 is a block diagram of the calculation section, FIG. 6 is a block diagram of the video address generation section, FIG. 7 is an explanatory diagram of page mode processing, and FIG. Fig. 8 is a block diagram of the encoding table section, Fig. 9 is a block diagram of the decoding table section, Fig. 10 is a block diagram of the change point detection section, and Fig. 11 is a detailed circuit diagram of the mask circuit in the change point detection section. , Fig. 12 is a block diagram of the image signal restoration section, Fig. 13 is a detailed circuit diagram of the image signal restoration circuit, Fig. 14 is a state transition diagram of the Codec during encoding/decoding processing, and Fig. 15 is a diagram of the microcomputer. A state transition diagram of the Codec when accessing a VM via the Codec, Figure 16 is a state transition diagram of the Codec during image signal transfer, Figure 17 is an explanatory diagram of the MR encoding method, and Figures 18 to 23. The figure shows the microprogram flow of MR encoding processing, from Figures 24 to 27.
The figure shows the microprogram flow of MR decoding process, the second
8 and 29 are block diagrams of facsimile systems using Codec. 2100...MPUI/F, 2200...control unit,
2300... Arithmetic unit, 2400... Video address generation unit, 2500-.
・Table section, 2600--change point detection section, 2700 Distance Hop between modes alb1 vs. value 3 Absolute value of distance between alJ〉3 H+M14 (a oa +) 1 MH (a la 2)
Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures Figures

Claims (1)

[Claims] 1. A facsimile machine with built-in means for encoding and decoding an image signal read from document information in parallel for each plurality of bits.