JPS6282769A - Coding device - Google Patents

Abstract

PURPOSE:To speed up a processing speed by providing a microprogram sequencer, a code discriminating means counting a run length and detecting a code mode and a run length code generating means generating a run length code corresponding to the run length. CONSTITUTION:A run length count 2-dimension mode detection circuit 201 starts the operation when a signal RLGO is outputted from a microprogram sequencer 300. When the signal RL/MODE outputted from the microprogram sequencer 300 is in the state of a signal RL of logical level H, every time a run length is discriminated, a signal RLRDY is replied to the microprogram sequencer 300. When the signal RL/MODE is in a signal MODE of logical L level, every time the code mode is discriminated, the signal RLRDY is replied and a mode data DM representing the code mode is outputted to the microprogram sequencer 300. Thus, high speed processing is attained.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to an encoding device that encodes image data.

[Prior Art] In recent years, facsimile machines that use public telephone lines as transmission lines have become popular.
Many of the facsimile machines comply with the recommendations of CCITY (International Telegraph and Telephone Consultative Committee), and among them, the group 3 (03) facsimile machine specified in Recommendation 7.4 has the highest transmission efficiency.

This 63 facsimile device uses the MH (Modified Huffman) method, which is a one-dimensional encoding method, or the MR (Modified REA) method, which is a two-dimensional encoding method.
Using the D) encoding method, the image signal is encoded and compressed to shorten the transmission time. Generally, a two-dimensional encoding method has higher coding compression efficiency than a one-dimensional encoding method, so a facsimile machine that can select a two-dimensional encoding method has higher transmission efficiency.

This type of encoding processing involves a system that uses a general-purpose microcomputer system or a microprogram sequencer, for example, because the amount of data to be processed is extremely large and the processing speed can match the transmission speed of a facsimile machine. This is done using a dedicated encoding device.

By the way, in the two-dimensional encoding method according to the above-mentioned CCITT Recommendation T, 4, in order to limit the part disturbed by transmission errors, after one line is one-dimensional encoded, a maximum of 11 consecutive lines are encoded. is determined to be two-dimensionally encoded, and the one-dimensionally encoded line data is used as a reference line for the two-dimensionally encoded line. Further, the value of the parameter is set to 2 for standard resolution and 4 for high resolution.

In this way, one-dimensional encoding processing is also performed when performing image compression using the two-dimensional encoding method. Also,
In the two-dimensional encoding process, depending on the state of the image signal, encoding is performed in a horizontal mode using MH codes.

For this reason, the encoding device was equipped with separate processing units (processing routines) for realizing the one-dimensional encoding method and processing units (processing routines) for realizing the two-dimensional encoding method. , the processing program size increases,
Additionally, there was a problem that the processing speed was not very fast.

[Objective] The present invention has been made in order to solve the problems of the prior art described above, and it is an object of the present invention to provide an encoding device that can increase processing speed.

[Configuration] In order to achieve this object, the present invention includes a microprogram sequencer that executes encoding procedure processing and generates a two-dimensional code, a code discriminator that performs run length counting and code mode detection, and a run length The function is divided into run-length code generating means that generates a run-length code corresponding to Processing speed is improved by branching to the routine and generating the corresponding code.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows an encoding device 1 according to an embodiment of the present invention. This embodiment is applied to a facsimile machine, etc. equipped with a control device configured with a microcomputer system having a 16-bit width data bus, and therefore both the image data to be processed and the encoded data after processing are 16 bits wide. It has been formatted into bits.

In the figure, an encoding device 1 includes an input/output unit 100 for inputting and outputting data to and from a data bus, and a data generation unit that determines the run length and encoding mode (described later) of input image data and generates an MH code. 200, and a microprogram sequencer 300 that executes encoding procedure processing and other control processing and generates MR codes.

The input/output unit 100 includes a latch circuit 101 that inputs image data DI formatted into 16 bits, an image data interface circuit 102 that controls the input timing of the image data DI. It is composed of a serial/parallel converter 103 that formats output encoded data DC into 16 bits and an encoded data interface circuit 104.

The data generator 200 counts the run length of the image data DI input from the latch circuit 101, and also counts the run length of the image data DI input from the latch circuit 101.
A run-length counting two-dimensional mode detection circuit 201 that determines the coding mode based on the correlation with the reference line when the dimensional coding mode is set. M)I encoding ROM (read only memory) 202 that generates MH code data DMH corresponding to the run length data DRL output from the run length counting two-dimensional mode detection circuit 201, MH code data DMH or microprogram sequencer a gate circuit 203 for selecting one of the MR code data DMR output from 300;
204, and a parallel/serial converter 205 for once accumulating variable length code data outputted via gate circuits 203 and 204 and then transmitting it to the serial/parallel converter 103.

The run-length counting two-dimensional mode detection circuit 201 starts its operation when the signal RLGO is output from the microprogram sequencer 300. Then, the signal RL/ which is output from the micro program sequencer 300 is
When MODE is in the signal RL state of logic level H, it responds with the signal RLRDY to the microprogram sequencer 300 every time the run length is determined, and outputs the signal RL.
When /MODE is in the signal MODE state of logic level L, the signal RLRDY is output every time the code mode is determined.
At the same time, the code mode is output to the microprogram sequencer 300 as mode data DM. Furthermore, when the processing of one line of image data DI is completed, the signal LH is output to the microprogram sequencer 300.

The microprogram sequencer 300 includes a microprogram ROM 301 that stores 1024 words of a 21-bit microprogram to be executed, a 21-bit pipeline register 302 that stores execution instructions output from the microprogram ROM 301, and a 21-bit pipeline register 302 that stores execution instructions to be executed in the next microcycle. A 10-bit pipeline register 303 that stores the address of the instruction to be executed, and an incrementer 304.1' that stores the output of the incrementer 304 to generate the address of the instruction to be executed in the second microcycle from that point. microprogram counter register 3051; stack 306 for storing the return address to the main routine after finishing the subroutine when transitioning to a subroutine due to a conditional call, etc.;
Stack pointer 30 pointing to the top of the stack 306
7. Open mode data output from run length counting two-dimensional mode detection circuit 201, pipeline register 30
The branch address output from 2, the output of the stack 306, and the output of the microprogram counter register 305 are applied to input terminals A, B, C, and D, respectively.
A multiplexer 308 that outputs one of them from the output terminal Y. 2-bit sequencer command sC output from pipeline register 302.

A 2-bit selection signal SL that sets the selection of the multiplexer 308 and a 2-bit selection signal SL that controls the stack 306 and the stack pointer 307 correspond to the 1-bit test data TD output from the multiplexer 309 and the upper 3 bits of the branch address. Bit active signal A
The instruction decoder 310 outputs T.

In this way, the microprogram sequencer 300
It has a two-level pipeline configuration.

Further, the multiplexer 309 has 6 bits of the output of the pipeline register 301 added as a selection signal, selects one of the 64 input terminals, and outputs it to the instruction encoder 310 as test data. The signals input to the multiplexer 309 include, for example, the signals LE and RLRDY output from the run length counting two-dimensional mode detection circuit 201.

Incidentally, in this microprogram sequencer 300, a 21-bit microprogram is divided into four modes according to its upper two bits, and the relationship between the states of these upper two bits and each mode is shown in Table 1 below.

(Left below) The sequence command SC added to the instruction encoder 310 is data of bits 18 and 17, which are common to each mode.

Here, Table 2 shows the relationship between the sequence command SC and the output of the instruction encoder 310.

Mode 0 is a mode in which a conditional jump is performed depending on the state of data output from multiplexer 309, and bits 16 to 0 are assigned as shown in Table 1. (Margins below) Here, the upper three bits of branch addresses A, ~A0 are all set to 1 in the conditional jump mode.

Also, the most significant bit of the test address indicates that the condition is met.
This is used to set whether to judge whether it is true (T) or false (F). For example, it becomes the other signal when exclusive ORing is performed with the output inside the multiplexer 309, and the result of that exclusive ORing is set. is output from the output terminal of multiplexer 309.

Mode 1 is a mode in which constant data such as code data is set as an output, and bits 16 to 0 are assigned as shown in Table 4.

Here, the address corresponds to the output destination of the constant data, and is used, for example, as an enable signal for a latch circuit (not shown) that latches the signal RLGO. The constant data also includes a signal RL/MODE. Also, in mode 1, gate 2 is input from pipeline register 301.
MR code data DMR is outputted to the serial/parallel converter 205 and latched to the serial/parallel converter 205. Note that in this mode 1, bit 4 is not used.

Mode 2 is for transferring data between registers and resetting flag flip-flops (hereinafter referred to as F/F), and bits 16-0 are as shown in Table 5 below.
It is assigned as follows.

Here, T/F is a signal for selecting the terminating code and makeup code of the MH encoded ROM 202. A of the F/F control signals.

B, C, and D indicate the F/F address, and R and S indicate the reset signal and set signal. Also, when inverting the color of pixel a0, which will be described later, the color of this pixel a0 is retained. Apply a set signal and a reset signal to the F/F at the same time to invert it. S, ADR, Tori, ADR, is,
They each represent the data source and destination addresses of the registers that transfer data. Note that in this mode 2, bits 16 and 15 are not used.

Mode 3 is a mode in which the serial/parallel converter 103 and the parallel/serial converter 205 are shifted, and a counter that stores the shift number of the serial/parallel converter 103 and the parallel/serial converter 205 is enabled. Yes, bits 16-0 are as shown in Table 6 below.
It is assigned as follows.

Here, bits 16 and 17 are gate circuits 203 and 204.
, and connect the parallel/serial converter 205
Select the data to be set. Other control signals include a counter enable signal and shift signals for the serial/parallel converter 103 and parallel/serial converter 205.

Each of these modes is appropriately selected to appropriately execute the microprogram.

Next, encoding processing by this encoding device will be explained. Note that in the following explanation, processing will be explained not at the microprogram level but at a higher level.

Here, some terms related to encoding processing used in the following explanation will be explained. Please note that these terms are used by CCI
It is defined in Recommendation T.4 of the TT.

(i) Change pixel The change pixel a0 is the reference or starting point change pixel on the encoding line, and at the beginning of the encoding line is the change pixel a. is placed on the virtual white change pixel immediately before the first pixel of the line, and during encoding of the encoded line, the position of the change pixel a0 is defined by the previous encoding mode.

The changed pixel a1 is the first changed pixel to the right of the changed pixel a0 on the encoding line.

The changed pixel a2 is the first changed pixel to the right of the changed pixel a1 on the encoding line.

The changed pixel b0 is the changed pixel a on the reference line to the right of the changed pixel a0. is the first change pixel with the opposite color.

The changed pixel S is the first changed pixel to the right of the changed pixel b0 on the reference line.

(ii) Code (encoding) mode The pass mode is defined by the existence of the changed pixel b2 on the left side of the changed pixel a1. When this mode is encoded, in preparation for the next encoding, change pixel a0 is changed to change pixel b2.
Set on the pixel on the encoding line directly below.

In the vertical mode, the position of the changed pixel a1 is encoded as a relative position from the changed pixel b1. The relative distance at bx has seven values vO, each with a different sign.

VRl, VH2, VH2, VshiLvL2. Vj3(7)
Takes either l or N value.

Subscripts R and L indicate whether the changed pixel a1 is on the right or left side of the changed pixel b1, and the subscripts O to 3 indicate the distance a
indicates a value of 1. After vertical mode encoding, change pixel a
The position of 0 is moved onto the changed pixel a1.

In horizontal mode, run length a. Both a and ala are encoded using the old code M(aI, ax)4M(ataz). The signs +'t (an at ) and M (at at ) are the run lengths a,
This is a code indicating the length and color (white or black) of al and ala, and consists of the corresponding MH code. After encoding this mode, the position of the changed pixel aI is shifted onto the changed pixel a2.

Each code in each of these code modes takes the values shown in Table 7 below.

Further, such a two-dimensional code mode is detected by a run-length counting two-dimensional mode detection circuit 201.

When the run-length counting two-dimensional mode detection circuit 201 detects each mode, it outputs mode data DM having values as shown in Table 8.

Note that H in the mode data column is a hexadecimal number, and the lower 10 digits are output as the mode data frame.

On the other hand, address 00 of the microprogram ROM 301
10H,0011H,00128,00131(,00
14H, 0015H, 0016H.

0017H, 0018H, 0019H (lower 10
(valid only for digits), a jump instruction is placed to move to the processing that generates the code of the corresponding mode. Therefore, when the mode data DM is input as address data, the jump instruction is placed immediately after that to move to the processing that generates the code of the corresponding mode. Branching enables high-speed processing.

FIG. 2 shows an outline of the main routine of the one-line encoding process in this embodiment.

In this one-line encoding process, one line of image data D
Before actually encoding I, line start end processing 101 is performed.

In this line start end processing 101, first, a line synchronization code EOL, which separates lines, is set in the parallel/serial converter 205 so that the upper bits are filled with the line synchronization code EOL, and the parallel/serial converter 205 is 205 and the serial/parallel converter 103, and set the line synchronization code EOL to the serial/parallel converter 103 so that it is filled from the lower bit.

Next, the TAG bit (1 bit) that identifies whether it is a one-dimensional encoded line or a two-dimensional encoded line is packed from the lower bit of the serial/parallel converter 103 by the same process as the line synchronization code EOL. .

If the encoding method set at that time is a one-dimensional encoding method, the signal RL/MODE is set to the signal RL state of logic level H, and in the case of a two-dimensional encoding method, the signal RL/MODE is set to the signal RL state of logic level H. Set the signal MODE state to logic level L. Immediately after outputting this signal RL/MODE, the signal RLGO is output to activate the run length counting two-dimensional mode detection circuit 201.

Next, the state of the line end flag FEL, which is set when the encoding process for one line is finished, is determined (determination 1
02). Immediately after finishing the line start end process 101, the line end flag FEL is not turned on, so this judgment 10
The result of 2 is No.

When the result of judgment 102 is NO, it is judged that the run-length counting two-dimensional mode detection circuit 201 outputs a signal RLRDY indicating that any mode has been detected. Then, it is determined whether a signal LH indicating that the encoding process of one line of image data DI has been completed is output from the run length counting two-dimensional mode detection circuit 201 (determination 104). ).

When the result of determination 104 is YES, processing 105 is executed to turn on the line end flag FEL. Also, 1
If the encoding process for the line has not been completed and the result of judgment 104 is No, the instruction decoder 310 selects the input terminal A of the multiplexer 308, and the mode data DM is input as the microprogram address (processing 106).

As a result, the branch instructions stored in the addresses of the microprogram ROM 301 are executed in accordance with each code mode, branching to the corresponding encoding processing routine, and codes corresponding to each are generated (process 107).
).

By executing this main routine once, one piece of encoded data is formed and output, and by repeatedly executing it, one line of image data is sequentially encoded. Then, when the encoding process is completed, the signal LH is responded, so the result of judgment 104 becomes YES, and in process 105, the line end flag FEL is turned on. Therefore, at the next execution, the result of decision 102 will be YES,
Line termination processing 108 is performed.

In this line termination processing 108, it is checked whether the encoded data of the completed line has more than the minimum number of compensation bits for one line set at that time, and if it is less than that, fill pits are compensated.

In this way, encoding processing for one line is performed,
This is repeated for the total number of lines, and the encoding process for one page's worth of image (image information) is executed.

Incidentally, the branch instruction in process 107 of the main routine described above is set to a microprogram address corresponding to the value of mode data DM, as shown in Table 9, for example.

Here, the numerical value in the address field is a hexadecimal number, and each operand of the branch instruction is a label name attached to the start address of the branch destination routine.

That is, the main body of the horizontal mode encoding processing routine is placed from the label TXHORZ, and the main body of the vertical mode encoding processing routine is placed from the label TXV(X).
The main body of the bus mode encoding processing routine is placed from the label TXPASS, and 1 is placed from the label TXID.
Contains the main body of the dimensional mode encoding processing routine. Note that the X in TXV(x) stands for one or two characters following TXV.

FIG. 3 shows these encoding processing routines.

Note that a corresponding label name is attached to the beginning of each routine, and each routine will be called by that label name below.

(a) of the same figure shows the horizontal mode encoding processing routine TXH.
It shows ORZ. In this routine TXHORZ,
First, convert horizontal mode code H to parallel/serial converter 2.
After setting to 04, parallel/serial converter 20
A subroutine T that shifts out the data of No. 4 to the serial/parallel converter 103 and further generates the MH code.
Call the Set it in the parallel converter 103.

Next, the color of the changed pixel d0 is inverted, and the run length a,
Output signals RL and RLGO to detect a2.

The run length counting two-dimensional mode detection circuit 201 is activated and waits until the signal RLRDY is responded.

When the signal RLRDY is responded, subroutine T is executed again.
X MH is called to set the MH code corresponding to the run length a1aZ in the serial/parallel converter 103.

Then, in order to invert the color of the changed pixel a0 and detect the primary sign, after outputting the signals MOD[E and RLGO, the process jumps to point A and returns to the main routine of FIG.

As a result, the code H0M (ao at )+M (a
t az ) is formed and output.

In subroutine TXMH, first, run length count 2
The MH code corresponding to the contents of the run length counter of the dimensional mode detector 201 is read from the MH encoding ROM 202, and the read MH code is set in the parallel/serial converter 204, and then the data of the parallel/serial converter 204 is Serial/parallel converter 103
Shift out. As a result, an H code is set in the serial/parallel converter 103 at %.

FIG. 4(c) shows the encoding processing routine TXV(X) in the vertical mode (2). Note that this encoding processing routine TXV (x) is the encoding processing routine TXV (x).
L3.

TXVL2. TXVLI, TXVO, TXVRI, TX
It is hailing on behalf of VR2 and TXVR3.

In this encoding processing routine TXV(X), first, the vertical mode code V(x) is sent to the parallel/serial converter 20.
4, and its contents are shifted out to serial/parallel converter 103. After inverting the color of the changed pixel a0, the signals MODE and RLGO are output to activate the run length counting two-dimensional mode detection circuit 201. Note that the vertical mode code V(x) is a code corresponding to each vertical mode.

The same figure (d) shows the encoding processing routine TX in pass mode P.
It shows PASS. This encoding processing routine TXP
In the ASS, first, the bus mode code P is set in the parallel/serial converter 204 and its contents are shifted out to the serial/parallel converter 103.

Then, the signal RLGO is output to activate the run length counting two-dimensional mode detection circuit 201.

The figure (e) shows the one-dimensional mode encoding processing routine TX.
It shows the ID. In this encoding processing routine TXID, first, the subroutine TXMH is called, and the MH code corresponding to the run detected by the run length counting two-dimensional mode detection circuit 201 is set in the serial/parallel converter 103, and the changed pixel is After inverting the color of a0, output the signals RL and RLGO and count the run length 2.
The dimensional mode detection circuit 201 is activated.

In each of the above processing routines, from the parallel/serial converter 201 to the serial/parallel converter 10
3, the shift operation is temporarily interrupted when the serial/parallel converter 103 is full, and at that time, the serial/parallel converter 10
The 16-bit data stored in the code data interface circuit 104 is output to the outside (for example, a pass line). Then, when the serial/parallel converter 103 becomes empty, shifting is started. The full state of this serial/parallel converter 103 is
This is detected by a counter (not shown) that counts up in synchronization with this.

Further, when the 16-bit data stored in the latch circuit 101 has been completely encoded by the run-length counting two-dimensional mode detection circuit 201, the operation of the run-length counting two-dimensional mode detection circuit 201 is temporarily interrupted, and the image data interface Circuit 102 requests the next 16 bits of data from the external device.

Then, when the data is stored in the latch circuit 101, the operation of the run length counting two-dimensional mode detection circuit 201 is restarted.

In this way, one piece of code data is generated.

In addition, each step in the routine mentioned above.

It is realized by a combination of multiple microprograms.

Incidentally, in the embodiments described above, the present invention is implemented as a means for encoding image data, but the present invention may also be implemented as a decoding means for restoring encoded image data to original image data. It is possible. In that case, it is possible to realize an encoding/decoding device that performs both high-speed encoding processing and decoding processing.

Further, the present invention is not limited to an encoding device for a facsimile machine, but can be applied to other devices as long as it encodes one image data.

[Effects] As explained above, according to the present invention, a microprogram sequencer that executes an encoding process procedure and generates a two-dimensional cylinder code, a code discriminator that performs run length counting and code mode detection, and a run The function is divided into a run-length code generation means that generates a run-length code corresponding to the length, and furthermore, when a code mode is detected, the mode signal output from the code discrimination means is input as a microprogram address, and the corresponding Since the code is branched to the processing routine and the corresponding code is generated,
This provides the advantage of faster encoding processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an encoding device according to an embodiment of the present invention, FIG. 2 is a flowchart showing the main routine of encoding processing, and FIG. 3(a) is a horizontal mode encoding processing routine. FIG. 3B is a flowchart showing a subroutine; FIG. 1C is a flowchart showing a vertical mode encoding processing routine
FIG. 5D is a flowchart showing the encoding processing routine in the pass mode, and FIG. 3E is a flowchart showing the encoding processing routine in the one-dimensional mode. 100... Input/output section, 200... Data generation section, 2
01...Run length counting two-dimensional mode detection circuit, 2
02...MH encoding ROM, 300...Micro program sequencer. ,/−” ” ,,. Agent Patent Attorney Crest 1) Makoto )-・' Figure 7 1゛yo. Proceedings 1) (Voluntary) November 12, 1985

Claims (1)

[Claims] A microprogram sequencer that executes encoding procedure processing and generates a two-dimensional code, a code discriminator that counts run lengths based on input image signals and detects a code mode, and outputs from the code discriminator. The microprogram sequencer includes run-length code generation means for generating a run-length code corresponding to the run-length, and the microprogram sequencer inputs a mode signal output from the code discrimination means when a code mode is detected as a microprogram address. , an encoding device that branches to a corresponding processing routine and generates a corresponding code.