JPH06164945A - Facsimile equipment - Google Patents

Abstract

PURPOSE:To attain flexible and high speed decoding processing by providing a code memory storing a sent coding signal, a decoding means generating a picture signal from the code and a picture memory storing it, and connecting the code memory and the picture memory with other signal bus. CONSTITUTION:The facsimile equipment is formed by separating a system bus of a microcomputer 8010 and a video bus of a CODEC 2000. A picture signal is transferred on a V bus and the code is transferred on the system bus. Thus, the coding and decoding processing are quickened. Furthermore, a DMAC 8060 is used for the system bus and the code is transferred thereby to relieve the load of the microcomputer 8010. Since the VM8020 is independently of an address space of the microcomputer 8010, a large sized VM is provided without limitation a space of 64k bytes being a general address space of the 8-bit microcomputer. That is, a change point is detected and a picture signal is decoded in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MH code (Modified Huffman Co.) defined as an international standard for high speed facsimile.
De) and MR code (Modified READ) decoding and a facsimile equipped with a coding / decoding device for decoding.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing an outline of a facsimile. In the facsimile, the reading unit 1000 scans a document to generate an image (Video Data: VD) signal. Image signal (hereinafter, image signal VD, or simply V
Called D. ) Is converted into a code (Code Word) by the encoding / decoding device 2000, and further, the modulation / demodulation device 3000.
Is converted to a frequency in the transmission line band by the network controller 4
000 over the transmission line. On the receiving side,
By the procedure reverse to the above, the code is converted into the image signal, and the recording unit 5000 obtains a hard copy. In FIG. 1, description of a control unit (normally a microcomputer is used) for controlling the whole is omitted.

The Institute of Image Electronics Engineers, '77, Vol 6, No. 3 and '78, Vol 7, No. 1 and the Institute of Image Electronics Engineers, "80, V.
As described in documents such as ol9, No. 1 and the like, the encoding / decoding device 2000 often uses MH code and MR code of international standards. In the MH code, the bit length distance (Run Length: RL) between two adjacent bit change points (points at which pixel color changes, for example, white or black) on the same scan line is defined as “code”. It is to convert. The MR code is a line that has already been encoded and transmitted after finding the bit change points on two lines that are adjacent to each other.
The difference between the relative bit positions of the change points of the (reference line) and the line to be encoded (encoding line) is converted as "code". In the conventional encoding / decoding apparatus, a memory for storing one bit of an image signal as one word is prepared for a plurality of lines at the time of encoding, and the memory is serially scanned to obtain a change point. Moreover, at the time of decoding, the image signal is serially restored from the RL using a counter or the like.

[0004]

For this reason, the above-mentioned prior art has drawbacks in that the amount of hardware is large and that high-speed operation of a memory or the like is required. Also, the MH code and M
Since the R code is an advanced coding system, it is usually configured to process by combining software and hardware by a microcomputer. However, signal processing by software is slow, and the processing speed is limited for high-speed encoding. Further, even when the processing is performed only by hardware, there is a problem that the hardware becomes large in scale and the hardware is dedicated to the processing, so that it lacks flexibility. Further, although there is one in which the amount of hardware is reduced by connecting a memory for storing an image signal (for example, 8 bits are usually 1 word) on the system bus of a microcomputer, the bit change point in the word Has a problem in speeding up because it uses a method of serial detection.

In the case of processing the encoding / decoding processing, the processing unit (pixel, change point, line, page) of the image to be processed is separated, and each separated processing is a processing hierarchy. The difference from the technology is shown in Fig. 2.

The conventional apparatus uses a microcomputer to perform processing in pixel units for serially scanning an image signal to detect a change point and to generate a code from the change point information. In many cases, software is shared. In this example, the flexibility is high, but the load of the microcomputer is overlapped, and a high-speed line (for example, 4
There is a problem that it is difficult to apply it to 8 Kb / s or more). In addition, even if a slight change is made to the encoding and decoding algorithms in image processing, it is difficult because the hardware is dedicated, and the advantage of using a microcomputer (for example, interface by bus connection) However, it was difficult to build a flexible system that takes advantage of the above (ease of the above), and it was not possible to easily provide expandability.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art and to provide a facsimile equipped with a device for encoding and decoding image signals at high speed.

[0008]

In order to achieve the above object, the present invention employs the following technical means.

Coding and decoding having reading means for reading an original to generate an image signal, coding means for converting the read image signal into a code signal, and decoding means for decoding the code signal into an image signal Apparatus, an image memory for recording the image signal generated by the reading means and the image signal decoded by the encoding / decoding apparatus, and recording means for calling and recording the decoded image signal from the image memory An image bus for connecting the encoding / decoding device, the image memory, the reading means and the recording means to pass the image signal, a microcomputer for controlling the system, and a transmitting / receiving means for transmitting / receiving the code signal to / from the outside. A code memory for recording the received code signal and the code signal of the encoding / decoding device, and a code bus for flowing the code signal and the program. It is obtained by the facsimile apparatus.

[0010]

According to the present invention, a code memory for recording the transmitted encoded signal, a decoding means for generating an image signal from the encoded signal, and the decoded image signal are recorded. An image memory is provided, and high speed data transfer is possible by connecting the code memory and the decoding means and the decoding means and the image memory by different signal buses, respectively, and a plurality of decoding means are provided. One bit is one word, the change point is detected in parallel in word units, the image signal is restored from the change point information, and the decoding process is performed flexibly and at high speed by specifying the operation parameter given from the microcomputer. Is.

[0011]

Embodiments of the present invention will be described with reference to the drawings with reference to FIG.

FIG. 3 is an overall block diagram of an encoding / decoding device (Codec) according to the present invention. MPUI / F210
Reference numeral 0 denotes an interface with a microcomputer, and signals a-1 to a-10 are input / output. The signal a-1 is a chip select (CS) signal when the microcomputer accesses the Codec. The signal a-2 is a timing (Data Strobe: DS) signal when data is transferred between the microcomputer and the Codec. The signal a-3 is a read / write (Read / Writ) that controls reading or writing of the Codec from the microcomputer.
e: R / W) signal. The signals a-1 to a-3 are
Microcomputer board control bus (Control Bus: C
Bus). The signal a-4 is an address (Address: A) signal from the microcomputer. Signals a-1 to
The signal a-4 produces a signal C (referred to as an external control signal) for accessing each register in the Codec from the microcomputer. The signal a-5 is a signal (Data: D) for exchanging data between the microcomputer and the Codec, and is directly connected to the data bus (Data Bus: DBus) of the microcomputer. Signal a-6
Direct Memory Access Controller (Direct M
emory Access Controller: Direct memory access (Direct) that directly transfers data between the external circuit (usually a memory) and the memory inside the Codec for the DMAC
Memory Access (DMA) DMA request (DM)
A Request: DRQT) signal. The signal a-7 is
Acknowledgment for DRQT (DMA Acknowledge: DAC
K) It receives a signal. When the Codec outputs the DRQT signal, it waits for the DACK signal to return,
After the signal is returned, Data is synchronized with the timing of the DS signal.
Input and output. The signal a-8 makes an interrupt request (IRQ) to the microcomputer and is used, for example, when the processing for one line is completed. The signal a-9 is a reset (RESET) signal, and the inside of the Codec is in an initial state. The signal a-10 is a clock (CLK) signal, which serves as a timing source of processing in the Codec. An example of using these signals to interface with a microcomputer is an LSI that is directly connected to a commercially available microcomputer, so a further description will be omitted here. In this way, the Codec has the MPU I / F 2100 and can be directly connected to the bus of the microcomputer, so that the system configuration is easy and the size can be reduced.

The control unit 2200 is a part that supplies timing to each piece of hardware in the Codec via the internal control bus b and also inputs the state of each piece of hardware to determine what to do next. , Composed mainly of microprograms. This will be described in detail with reference to FIG.

The arithmetic unit 2300 is an ALU (Arithmetic L
ogic Unit: arithmetic / logical operation unit) and a register group, etc., and calculates the run leg RL from the address of the change point, the relative difference in position from the change between the reference line and the encoding line, and vice versa. Is the part to do. This will be described in detail with reference to FIG.

Video Address (VA)
The generation unit 2400 sends a video address (Vi) to a video memory (VM) that stores an image signal.
deo Address: VA) This is a part for generating the signal d-10. This will be described in detail with reference to FIG.

A table unit 2500 is composed of an encoding table and a decoding table of MH code and MR code, and controls the RL and relative difference from the arithmetic unit 2300 and the control unit 22.
This is a part for inputting a mode signal from 00 and converting it to MH code or MR code, and vice versa. For this,
A detailed description will be given with reference to FIGS. 8 and 9 and Tables 1 to 3. The change point detection unit 2600 takes in the image signal in units of words from a memory that stores the image signals of the reference line and the encoded line as a plurality of bits in one word, and changes the position of the change point in the word (called a bit address). ) Is detected by parallel processing. About this,
1 and Table 4 will be described in detail.

The image signal restoration unit 2700 uses the bit addresses of two adjacent change points on the decoding line and 2
It is a circuit that restores the image signal in parallel on a word-by-word basis based on the information indicating whether there is a difference in word address between the two changing points and the color information of the image signal between the changing points. This will be described in detail with reference to FIGS. 12, 13 and Table 5. Video Bus Interface (VBU)
The SI / F 2800 is an interface signal for the VM storing the image signal and a video bus (Video Bu).
s: VBus) control signal and DM from an external device
A signal for transferring the image signal is input and output at A.

When the Codec uses the VBus, the signal d-1 is a request for the right to use the VBus (Video Bus Request: BR).
QT) signal is output when there is a VBus usage right other than the Codec.

The signal d-2 is a confirmation (Video Bus Acknowledge: BACK) signal for the BRQT signal d-1.

The signal d-3 is a signal indicating that the VBus of the Codec is being used (Video Bus Enable: VBE).

The signal d-4 is a transfer timing (Video Data Strobe: VDS) signal when the image signal is transferred between the Codec and the external device (normal memory).

When the data is transferred between the Codec and the external device, the signal d-5 indicates whether the data transfer (write) from the Codec to the external device or the data transfer (read) from the external device to the Codec is performed by the external device. Video bus read out /
This is a write (Video Bus Read / Write: VR / W) signal.

The signal d-6 is a transfer request (Trasport Data DMA Request: TDRQT) signal of an image signal from the image signal generating unit (a reading unit in a normal facsimile) to the VM.

The signal d-7 is a confirmation (Transport Data DMA Acknowledge: TDACK) signal for the TDRQT signal.

The signal d-8 is a device for receiving an image signal.
This is an image signal reception request (Receive Data DMA Request: RDRQT) signal from a recording unit (usually a recording unit in a facsimile). Signal d-9 is a confirmation for RDRQT (RDRQT
Acknowledge: RDACK) signal.

The signal d-10 is a word address (Video Memory Word Ad) from the Codec for the video memory VM.
dress: VA) signal.

The signal d-11 is a video data bus (Video Data Bus) for transferring an image signal in word units between the VM and the Codec.
ta Bus: VD Bus).

FIG. 4 is a diagram for explaining the configuration of the control unit 2200 in detail. Instruction Register (Instruction Registe
r: IR) 2210 is an external control device (usually a microcomputer)
It is a register for receiving a macro instruction such as an MH coded instruction. Mapping ROM (Read Only Memory) 220
0 generates a start address of the ROM 2240 which stores a micro program for decoding and executing the macro instruction stored in the instruction register IR2210. The sequencer 2230 generates an address of the microprogram ROM 2240 and performs interrupt control, subroutine control, jump address generation, and the like. The pipeline register 2250 is a register for storing the micro instruction from the micro program ROM 2240. The output of the pipeline register 2250 is supplied to each hardware as an operation command via the internal control bus b. Further, a part thereof is also fed back to the sequencer 2230, and the sequencer 2230 is also controlled, for example, interrupt enable / disable. A status register (Status Register: SR) 2260 is a register for storing the internal status of the Codec. The status of processing and the data buffer register (Data Buffer Register: DB).
R) Notifies the microcomputer of the ready state of 2280. System Control Register (System Control R
egister: SCR) 2270 is a register for storing a signal for controlling the Codec system and is written by the microcomputer. For example, whether the Codec is monopolizing the VBus, whether the Codec is in a wait state, or 1
Line-by-line processing or multi-line (Page mode: Pa
Control of processing in units of ge Mode) is performed in this register. The multiplexer (MPX) 2290 connects a part of the external control bus C to the internal control bus b when the Codec is in the idle state (no processing is performed) or in the Wait state,
In other states, the switch connects the signal from the pipeline register 2250 to the internal control bus b. As a result, the microcomputer can access the register in the Codec controlled by the internal control bus b. The DBR2280 transfers data between the VDBus signal d-11 and the DBus signal a-5. The microcomputer 22R2210 sends a system bus (SBus) and V
When receiving a data transfer command between Buses, for example, VB
When transferring from us to SBus, the image signal VD is set to DBR228.
Set to 0 and turn on the SR2260 DBR ready flag (O
N) and inform the microcomputer. The microcomputer reads DBR2280 to obtain VD. The same applies when the transfer direction is the opposite. This operation will be described later in detail.

As described above, since the control unit 2200 uses the microprogramming control method, it is possible to perform flexible processing, and since the timing is centrally controlled in this portion, the design at the time of LSI implementation is easy. There is an effect that.

FIG. 5 illustrates the calculation unit 2300 in detail. The register file 2310 can be composed of, for example, a 2-port RAM (2Port Random Access Memory),
It stores various signals. Hereafter, the description will be made assuming that 1 word = 1 byte. The register file 2310 has a virtual address register A channel (V) that serves as an address of an encoding line at the time of encoding and a decoding line at the time of decoding.
ARA), a virtual address register B channel (VARB) which becomes an address of a reference line, a reading unit and a recording unit, and V
Virtual address register C that becomes an address of a line (transfer line) when an image signal is DMA-transferred between M channels, a temporary storage address register A that stores a position of a coding line or a change point of the coding line.
(Temporal Address Register A: TARA) and a temporary storage address register B (TARB) for storing the address of the change point of the reference line. The addresses stored in these registers are virtual addresses in which the start of the line is virtually zero. It also stores both word addresses and bit addresses. Arithmetic unit 2
All the virtual addresses are used in 300. By adopting the virtual address method, there is an effect that the relative address difference between the change point of the reference line and the change point of the encoding line can be obtained at high speed. Also, since it is sufficient to have the capacity to store only the address area for the horizontal direction, the register file can be made smaller and the AL
This has the effect of making U2350 smaller. Moreover, since both a bit address and a word address are stored in one register, the distance between two transition points can be obtained at high speed in bit units, even though the image signal is handled in word units. effective. In addition to this, the register file 2310 also stores terminal registers A and B channels (Terminal R) for storing the number of pixels of one line.
egister A, B Channel: TRAB, terminal register C channel (TRC), and horizontal pixel number register (Horizontal Width Register) that stores the number of pixels in the horizontal direction of the screen.
gister: HWR), a line number register (LNR) for storing the number of lines to be processed,
A minimum code length register (MCLR) for storing the minimum code bit number of one line,
Codec working register A (General Register
A: GRA), register B (General Register B: GR)
There is B). Details of how to use these register groups will be given when the microprogram flow is described. The A latch 2320 and the B latch 2330 latch the outputs from the A port and the B port of the register file 2310. A mask 2341 and B mask 234
2 masks the bit address of the outputs from the A latch 2320 and the B latch 2330 to zero, or
Alternatively, it controls whether to pass the bit address without masking. The MPX2344 uses the output to the A port of the ALU2350 as the output of the A latch 2320 or the table unit 2
This is to select whether to output 500. MPX2343
Selects whether the output to the B port of the ALU2350 is the output of the B latch 2330 or 8. ALU2
Reference numeral 350 is for calculating data input from the A port and the B port, for example, for outputting A-B. The ALUSR2360 is a register that stores the state of the operation result of the ALU2350, and is, for example, a zero flag, an overflow flag, an underflow flag, or the like. Equivalent comparator 2370
Is a circuit that determines whether the output of the ALU2350 is equivalent to the output of the B latch 2330. For example, the contents of VARA are latched in the A latch 2320, TRAB is latched in the B latch 2330, and the A port of the ALU2350 is Input the masked output of the latch 2350, input 8 to the B port,
When (A port + B port) is executed and the word address of VARA is incremented, it can be determined whether or not it matches with TLAB, and the line end can be determined. The MPX2381 uses the lower 3 bits of the data written to the register file 2310 as the output of the ALU2350,
The change point detector 2600 selects whether to use the change point bit address. As a result, the bit address of the change point can be stored in the register file 2310 at high speed. MPX2382 is the register file 231
Whether to write data to 0 as DBus data or ALU2
It is to select whether to output 350. As a result, TLAB, TRC, HWR, LNR, and MCLR can be set as parameters directly from the microcomputer. Therefore Co
dec enables flexible processing. For example, if the value of TRAB is set smaller than the value of TRC, part of the image signal from the reading unit can be encoded. A more detailed description of these will be given when describing the microprogram flow.

FIG. 6 illustrates the video address generator 2400 in detail. Register file 2410
Is a start address register A (St which stores the actual word address of the VM at the start of the encoding or decoding line.
art Address Register (SARA), a start address register B (SARB) that stores the actual word address of the VM at the start of the reference line, and a start address register C that stores the actual word address of the VM at the start of the transfer line.
(SARC). The adder 2420 is for the start address of the line in the register file and the arithmetic unit 230.
The virtual word address (Virtual Word Address) from 0 is added, and the real word address (video address:
Video Address) is generated. This video address is latched by the address latch 2430 and output to VABus. An arbitrary video address can be generated by using the start address (Start Address) and the virtual address (Virtual Address). MPX2450 is a register file 2410
Write data to VABUSd-11 signal or D
This is to select whether to use the signal on BUSa-5.
When the control is transferred to the microcomputer each time the processing for one line is completed (called a line mode), the start address is directly set from the microcomputer for each line. On the other hand, in the mode (called Page mode) in which the number of lines set in the LNR is continuously processed, the start address is only set from the microcomputer at the beginning of the page, and the line For each codec, the start address of the register file 2410 and the register file 231
The page mode processing can be realized by adding the content of HWR in 0 and storing it as the next start address. In this case, since the microcomputer does all the setting after setting the start address once per page, the load on the microcomputer is reduced.
Also, by setting appropriate values for HWR, LNR, TR, and SAR, it is possible to process any rectangular area in one screen at high speed using Codec. FIG. 7 shows this. In the figure, HW is the width of the screen in the horizontal direction and is set to HWR. LN is set to LNR by the number of lines to be processed. T is the number of pixels to be processed in one line and is set to TR. SA is the VM at the top of the page
Set to SAR with the start address of. After that,
When receiving a macro command from the microcomputer, the Codec can continuously process the shaded area in FIG.

FIG. 8 explains the details of the encoding table section of the table section 2500. Latch 25
01 latches the operation result of the ALU2350.
The mode determination circuit 2502 uses the calculation result of the ALU2350 to determine the mode at the time of encoding (for example, RL is 64 at the time of MH encoding).
It is determined whether it is greater than or less than) and notifies the sequencer 2230. The address generation circuit 2503 generates an appropriate address for the encoding table ROM 2504 based on the signal from the internal control Bus and the operation result of the ALU latched by the latch circuit 2501. The output of the encoding table ROM2504 is
It is loaded into the shift register 2505, and is shifted bit by bit in order of serial / parallel (Serial / Paralle).
l: S / P) converter 2507. S / P converter 2
When 8 bits are generated in 507, first in first out (FIFO) memory 25
Written at 08. The operation unit 23 counts the generation of the 8-bit code in the S / P converter 2507.
00 GRB and ALU2350. In this way, since it does not have a counter and counts with the ALU and the register,
The timing can be centrally managed, and the timing control is easy. Termination detection circuit 2506
Detects the end of the code entered in the shift register 2505, which will be described in detail later. FIFO
The memory 2508 is for improving code transfer efficiency. When the code is set in the FIFO memory 2508, DRQT is output via the external control Bus. When the DMAC is connected, the FIFO memory 2508 is accessed by DACK. When the DMAC is not connected, the microcomputer can directly read the FIFO memory 2508 to obtain the code. In this way, since the code is directly output to DBus, there is an effect that system design becomes easy. Further, since the codes are transferred in parallel, there is an effect that the timing is easy and the speed is high.

[0033]

[Table 1]

Table 1 describes the encoding table ROM 2504. For the RL and difference in the address column, the calculation result of the ALU2350 is the address. The other part is generated by the address generation circuit 2503 by a signal from the internal control Bus. Like this ALU2350
Since the calculation result of is directly the address of the table, the encoding table can be pulled at high speed.

[0035]

[Table 2]

Table 2 shows the code (1
011) as an example, encoding is performed using a table, and S /
A method of sending to the P converter 2507 and detecting termination of the code by the termination detection circuit 2506 will be described.
The calculation result that the white RL is 4 (= (100) ₂ ) is AL
When obtained by U2350, the address of the table becomes (000000100) ₂ as shown in Table 2 (a). At this time, table 25
In 04, data of (10111000000000) ₂ is stored in order from the upper bit. The upper 4 bits are a code, and the subsequent D ₉ bit "1" indicates the end of the code. This value is loaded into the shift register 2505. The shift register 2505 is of a type that fills "0" in the least significant bit when a shift pulse is input. Every time shifting is performed as shown in Table 2 (b), the most significant bit of the shift register 2505 is the S / P converter 2507.
Will be shifted to. If you shift four times (1000000000000
0) ₂ , but this pattern is the termination detection circuit 2
When it is input to 506, it is detected that the termination (Terminate) has occurred, and the sequencer is notified to that effect. The number of shifts is counted by the GRA of the arithmetic unit 2300 and stored in the GRA at the end of the encoding process for one line. The number of fill codes can be controlled by comparing the total number of code bits for one line with the minimum number of code bits of MCLR.

FIG. 9 illustrates the decoding table section in detail. The FIFO 2510 is a code reception buffer.
The parallel / serial (P / S) converter 2511 sequentially receives the code received in 8-bit units bit by bit at the line end (En
It is supplied to the d of line (EOL) detection circuit 2512 and the address generation circuit 2513. P / S converter 2
The function of the counter necessary for the 511 is the calculation unit 23.
00 GRB executes. Therefore, a counter having its own timing is unnecessary. EOL detection circuit 251
2 includes a 12-bit S / P converter and a gate that detects whether or not the output of the S / P converter matches (000000000001) _2, and determines whether the received code pattern is EOL or not. It is a thing. By providing the EOL detection circuit 2512 independently, there is an effect that the EOL can be detected reliably and at high speed even when a transmission line error occurs and a code word break is erroneously recognized. Address generation circuit 251
3 generates the address of the decryption table ROM2514, and creates the start address of the decryption table ROM2514,
The next address is created from the received code and the output of the decoding table ROM2514. The decoding method uses a tree search method, which has been described in detail in Japanese Patent Application No. 55-174592, and therefore only a brief explanation will be given here using Table 3. The latch 2515 is a decoding table ROM 2514.
The output of is temporarily stored.

[0038]

[Table 3]

Table 3 describes the decoding table ROM 2514, which is created so as to be suitable for decoding by the tree search method. The decoding table ROM 2514 is roughly divided into three parts with addresses. That is, the MH white code portion, the MH black code portion, the MR
This is the part of the code. The contents of the decryption table ROM2514 are
When the decoding is not completed, that is, when the codeword is in the middle, it is a part of the address to be accessed next. When the codeword is completed and the decoding is completed, it is the information of the code. The sequencer 2230 searches the decoding table ROM 2514 once for each code bit, and knows the meaning of the decoded code from its output. The information of the decoded code is MPX2344
Since it directly enters the ALU2350's A port via, the position of the change point can be obtained at high speed.

FIG. 10 illustrates the change point detection unit 2600 in detail. Reference line change point detector 2610
And a coded line change point detector 2620.
Since the two operations are almost the same, the reference line change point detector 2610 will be described. MPX2614 is VDBus
Data → VD from, and selects the data VD obtained by inverting the data from VDBus, one of the data from the latch 2617. The mask circuit 2616 is
A circuit that fills data input from the MPX2614 to "1" up to the bit indicated by the bit address BA will be described in detail with reference to FIG. The latch 2617 is provided in the mask circuit 26.
The output from 16 is temporarily stored. The priority encoder 2618 detects the position of the lowest "0" existing in the data input from the latch 2617. If "0" exists in the data, the reference line change point flag is set to "1" to inform the sequencer 2230 that there is a change point. In addition, the position where “0” exists is output to the operation unit 2300 as a change point bit address. This bit address is the direct register file 23
Since it is input to 10, there is an effect that the bit address of the change point can be stored at high speed. Further, this change point bit address is output as a bit address BA to the mask circuit 2616 via the MPX2619. The MPX2619 has a calculation unit 230.
The B port bit address (B-Port Bit Address) from the B latch 2330 of 0 and the change point bit address from the priority encoder 2618 are selected, and the detection start bit address of the change point of the reference line is set to the encoding line. The B port bit address is selected only when it is desired to start from the bit address of the change point of (this is referred to as reference line address return). This will be described in detail in the microprogram flow. Exclusive OR (EXO
R) 2611, the color of the encoding start point (referred to as a _0), there is a change point of the reference line (b ₁ and b _2, b ₁ is the opposite color and right a ₀ from just above a ₀ change point, b ₂ receives b ₁ / b ₂ signal for selecting whether to detect the or b ₂ detects a b ₁ of the right a ₀ and the same color change point) than b _1, MPX2614
To control. The change point flag of the gate 2612 is “1”.
And the reference line address return is "0", MPX2
The input data of 614 is used as the output of the latch 2617. The OR gate 2613, when the change point flag is “1” or the address return is “1”, the mask circuit 261.
6 is enabled. FIG. 11 illustrates the mask circuit 2616 in detail.
-1 and NAND gates 2616-2 to 2616-9.

[0041]

[Table 4]

Table 4 shows an operation example of this change point detector. As an initial condition, VD = (00111000) ₂ ,
a ₀ color = 0, b ₁ / b ₂ = 0, reference line change point flag =
0, reference line address return = 0. At the time of the first latch, the outputs of the EXOR 2611 and the gate 2612 are both “0” from the initial condition, so the input data to the mask circuit 2616 is VD. Further, since the mask circuit enable signal E is "0", the output of the mask circuit 2616 is simply an inversion of the input data. Therefore, (11000111) ₂ is latched in the latch 2617. Therefore, the output of the priority encoder 2618 is the reference line change point flag = “1” and the reference line change point bit address = 3. Since the reference line change point flag is "1" at the time of the second latch, the output of the gate 2612 is "1" and the input data to the mask circuit 2616 is the output data (11000111) ₂ of the latch 2617. Become. Since the mask circuit enable signal E is "1", the mask circuit 2616 inverts the input data and outputs the data (00111111) ₂ which is filled with "1" up to the bit position indicated by the reference line change point bit address. To do. Therefore, the change point bit address 6 is obtained. Similarly, the change point bit address can be obtained by repeating the latch until the change point disappears. As is clear from the above description, this change point detector can detect the bit address of the change point at an arbitrary position within 8 bits by one-time latching, and after latching, it is possible to check every bit. Compared with this, there is an effect that the change point can be detected at high speed. Also,
Since the counter is not used to check the bit address of the change point, the timing control can be entirely performed by the control unit 2200, which has an effect of being easy to design and suitable for an LSI.

FIGS. 12 and 13 and Table 5 describe the image signal restoration unit 2700 in detail.

The image signal restoration circuit 2701 receives the bit addresses of the restoration start point and end point from the arithmetic unit 2300.
Inputting from the bit address of port and B port, inputting the word address difference between the restoration start point and the restoration point from the operation result of ALU2350, and generating the restoration data. Fig. 13 shows the detailed circuit, and Table 5 shows It is the truth table. As for the word address difference, the address of the restoration start point is latched in the A latch 2320, the address of the restoration end point is latched in the B latch 2330, and the A mask 2341 and the B mask 234.
It can be obtained by turning on 2 and inputting these two addresses into the ALU2350 and executing (BA) whether or not the result is zero. As described above, by providing the circuits 2342 and 2343 for masking the bit address in the operation unit 2300, even if both the bit address and the word address are stored in the file register 2310, one operation is performed. As a result, there is an effect that the presence or absence of the word address difference can be determined at high speed. FIG. 13 shows the image signal restoration circuit 27.
In the detailed circuit diagram of 01, decoders 2701-1 and 270
It consists of 1-2 and an AND gate. The operation of this circuit is as in the truth table shown in Table 5.

[0045]

[Table 5]

That is, when the color of a ₀ is "0", all outputs are "0", and when the color of a ₀ is "1" and there is no word address difference, the value of the A port bit address is changed. x and B port bit address values are y, D _{x to} D
up to _y-1 is "1", the other is "0", when the color of a ₀ there is a word address difference "1", "1" to D _x to D _7, and the other is "0" Becomes As a result, the restored image signal in the word can be generated by one calculation. This has an effect that the timing is faster and the timing control is easier than the method of generating every bit by using the counter.
The temporary storage register 2702 stores the image signal restored immediately before, and is cleared when the restored image signal of 1 word is written in the memory. OR circuit 2703
Is a logical sum of the output of the image signal restoration circuit 2701 and the output of the temporary storage register 2702, whereby the image signals in one word can be restored one after another. Latch circuit
Reference numeral 2704 latches the restored image signal of 1 word from the logical sum circuit 2703 and outputs the restored image signal to VDBus. The restored image signal is written in the VM word by word. As described in detail above, the image signal restoration unit 270
0 has the effect that the image signal can be restored at high speed because it restores the image signal completely in parallel.

The details of the hardware configuration of the Codec and the outline of its operation have been described above with reference to FIGS. 3 to 13 and Tables 1 to 5. Next, using FIG. 14 to FIG.
The operation in each of the various processing modes will be described with reference to the state transition diagram.

FIG. 14 is a state transition diagram in the encoding and decoding processing modes. SI represents an idle state.

In the SI state, after receiving appropriate parameter settings from the microcomputer, a macro command (for example, MH
When an encoded command) is input, the state transits to S ₁ . S ₁ is a state in which a predetermined process is executed for one line, and the details of the operation at this time will be described in the description of the microprogram flow. S ₁ until processing for one line is completed
The process is continuously executed in the state of. When the processing for one line is completed and the page mode is not set, the processing completion flag is turned on and the state returns to the SI state. In the page mode, the state is shifted to the S ₂ state, the contents of SAR and the contents of HWR are added here, the start address is updated by storing this in the SAR, and the LNR is decremented to determine the page end. . If the content of LNR is not zero, it is determined that it is not the page end (Page End) and the state shifts to S ₁ . At the page edge, returns to SI. In this way, the microcomputer has 1
Since the macro command need only be issued once per line or page, the load on the microcomputer can be reduced.

FIG. 15 is a state transition diagram in the line mode when a VM read macro command is issued.
This command is used when the microcomputer's system bus and video bus are separated
Issued when accessing M. State SI is idle. At this time, when a proper parameter setting is received from the microcomputer and a VM read command is received, the status S
Go to ₁ .

If the Codec has the exclusive right of VBus in S ₁ , the state immediately shifts to S ₂ . VBu in state S ₁
s If you do not have the exclusive right, output the BRQT signal and
Wait for K signal. When the BACK signal is returned, the state moves to state S ₂ . In the state S ₂ , the contents of SAR and the contents of VAR are added to output the video address, VR / W and VDS are output, VD is input from VM and latched in DBR, and DB
R Ready flag is turned on, BRQT is released, state S ₃
Move on to. In the state S ₃ , the DBR is read from the microcomputer or the DACK signal is input from the DMAC. DBR
Is accessed, the DBR ready flag is turned off and V
Increment AR. At this time, the line end (Line
End), move to SI, and if not the line end, move to S ₁ . In this way, the microcomputer can send VBus via DBR.
You can access the memory above. Moreover, since the video address is output by the Codec, even a microcomputer with a small address space can access a large-scale memory. Moreover, since the Codec automatically increments the video address, the VM can be accessed at high speed.

FIG. 16 shows the reading unit or the recording unit and the VM.
It is a state transition diagram at the time of performing the data transfer between. This data transfer is not executed by a macro command from the microcomputer, but TDRQT from the reading unit or recording unit.
Alternatively, it is executed by RDRQT. Since these signals enter the sequencer 2230 as interrupts, data transfer is possible even while the operation shown in FIG. 20 or 21 is being executed. State SI is a state in which the transfer end flag is ON. At this time, when the SARC receives the setting of the VM start address from the microcomputer, the state moves to state S ₁ . State S
₁ is a state in which TDRQT or RDRQT can be accepted. In state S ₁ , TDRQT signal or RD
When the RQT signal is input, the state moves to state S ₂ . State S
₂ has no meaning if the Codec has VBus exclusive rights and immediately moves to state S ₃ . Codec is V
BRQT in state S ₂ if not waiting for Bus monopoly
It issues a signal and stays in this state until the BACK signal is returned. When the BACK signal is returned in the state S ₂ , the state moves to the state S ₃ . In state S ₃ , TDACK signal or RDACK
A signal is output to notify the reading unit or recording unit or the like of the start of data transfer, and the state moves to state S ₄ . In the state S ₄ , the video address, VR / W , and VDS are output and VD is transferred, then the BRQT is released and the state moves to the state S ₅ . State S
_{At 5} , VARC is incremented. At this time, if it is not the line end, the state moves to state S ₁ . If the line end and the page mode are not set, the transfer end flag is turned on and the status SI
Return to. If it is at the line end and in page mode, state S ₆
Move on to. In state S ₆ , the start address is updated and L
Decrement the NR. At this time, if it is not the page edge, the state moves to state S ₁ . At the page edge, the transfer end flag is turned on and the state returns to SI. As described in detail above, for example, since data transfer can be performed even during the encoding process, there is an effect that high-speed processing can be performed. Further, since the data transfer is completely parallel transfer, there is an effect that data can be transferred at high speed with a low speed memory.

Next, the internal operation of the Codec will be described in more detail using a microprogram flow of MR encoding / decoding processing. First, the MR code system will be briefly described with reference to FIG.

FIG. 17 illustrates the MR code system. (A) explains the definition of the change point, and shows the states of the pixels on the reference line and the coding line. Pixels with diagonal lines represent black pixels. In the figure, a
₀ represents the coding start point, and a ₁ and a ₂ represent the change points of the coding line. b ₀ is the point on the reference line directly above a ₀ , b ₁
A ₀ and the first reference line changing points of opposite color, b ₂ at the right of b ₀ is at the right of b _1, representing the first-th reference line changing points of the same color as a _0. The MR code is roughly divided into a pass mode (abbreviated as P mode), a vertical mode (abbreviated as V mode) and a horizontal mode (abbreviated as H mode). (B) shows the case where the P mode is set. P-mode is when b ₁ and b ₂ appear before a ₁ appears. When P-mode coding is performed, a new a ₀ is created just below b ₂ .

(B) is an example of the vertical mode. This is a case where the mode is not the P mode and the absolute value of the distance between a ₁ and b ₁ (also referred to as a relative address difference or difference) is 3 or less. a ₁
When the difference between b ₁ is "0", V (0) becomes a sign, if a ₁ is from b ₁ to the left, it becomes VL (difference) code, if a ₁ is to the right than b ₁ and, It becomes a VR (difference) code. In the illustrated case, it is encoded as VR (2). After encoding, a
₁ becomes new a ₀ . (D) is an example of horizontal mode,
If not in P mode and the difference between a ₁ and b ₁ exceeds 3,
After outputting the H code, the RL between a ₀ and a ₁ is MH coded, and then the RL between a ₀ and a ₂ is MH coded. After encoding, a
₂ becomes the new a ₀ .

[0056]

[Table 6]

Table 6 shows the function of each register during MR encoding. VARA stores the virtual word address and bit address of the current scan of the encoded line. VARB stores the virtual word address and bit address of the scanning point of the reference line. T
The ARA stores the virtual word address and bit address of a ₀ or a ₁ . TARB is b ₁
The virtual word address and the bit address of the are stored. GRA is for counting the total number of code bits in one line. GRB is for 8-bit counting of the S / P converter 2507. SARA is the actual word address of the scanning start point of the VM that stores the data of the encoded line. SARB is a V that stores the data of the reference line.
This is the actual word address of the scan start point of M.

18 to 23 show a part of the flow of the microprogram at the time of MR encoding. It is assumed that the user has the exclusive right to VBus. Codec is from microcomputer to MR
When the IR 2210 receives the macro command for encoding, the sequencer 2230 outputs the address for executing the process 6101 and starts the MR encoding process. Micro program RO
The M2240 outputs the bit pattern of the microprogram for performing the processing 6101 accessed by the sequencer 2230 to the pipeline register 2250, and the processing is started. Processing 6101 is initialization, for example,
This is to set the output of the ALU2350 to zero and write the output of the ALU to VARA to clear VARA, or to set the color of a ₀ to white. In process 6102, the b ₁ detection mode is set. This means that the signals b ₁ / b ₂ to the EXOR 2611 are set to 0 (white = 0). In process 6103, VA
RB is latched in A-latch 2320, outputs of SARB and A-latch 2320 are added together and latched in address latch 2430, this is output to VABus, VR / W signal is read, VDS is output and VM is accessed. Then, VD is latched in the latch 2617. This series of operations will be called VD input of the reference line. Similarly, process 6
At 104, input VD of the encoding line and latch it.
Latch at 624. The determination 6105 is to determine whether or not there is a change point. The priority encoders 2618 and 2625 notify the sequencer if there is a change point in the input VD. Therefore, the sequencer can determine whether there is a change point and can jump to each processing block. If there is no change point, the process proceeds to step 6106, and if there is a change, the process proceeds to determination 6109. Process 6106
Increments the word address of VARA and VARB. For example, in the case of VARA, this is latched in the A latch 2320, the A mask 2341 is turned on, the output is input to the A port of the ALU2350, the B port is input to 8 and (A + B) is executed to execute the ALU2360. VAR output
Write to A. As a result, the word address of VARA is incremented and the bit address of VARA is cleared. Further, when VARA is latched in the A latch 2320, and TRAB is latched in the B latch 2330 at the same time, when the VARA is incremented, it is determined by the equivalence comparator 2370 whether or not it is the line end at the same time.

VARB is incremented in the same manner. In the judgment 6107, the line end is judged and the Line E
If it is not nd, that is, if the line end flag of the equality comparator 2370 is not ON, the sequencer returns to processing 6103 and repeats the processing described above. If it is the line end, the V (0) code output subroutine is called in process 6108, and then the line end process is performed. The line end processing is control of Fill and the like, and is omitted here. Judgment 6109
Then, the state of the change point is determined in determination 6110. If there is a change point only in the coding line, the process jumps to processing 6201, and if there is a change point only in the reference line, processing 6301
Jump and if there is a change point in both, process 640
Jump to 1. In this way, since the video address of the coding line and the video address of the reference line are alternately output and scanned, even if the coding line and the reference line are present in the same VM, the coding line and the reference line are as if they exist. There is an effect equivalent to scanning at the same time and at the same relative position. If the method of detecting the change point of the reference line after detecting the change point of the encoding line is adopted, the encoding of the pass mode becomes slow. In addition, when detecting the change point of the coding line after detecting the change point of the reference line,
If b ₁ exists farther to the right than a ₁ , the coding will be delayed.

In process 6201, the bit address of the change point of the encoded line is stored. This latches the contents of VARA in the A latch 2320, inputs this to the A port of the ALU2350, executes (A + 0), and executes the file register 2
MP so that the lower 3 bits input to 310 become the encoded line change point bit address from the change point detection unit 2600.
It can be realized by controlling X2381 and writing to VARA. As a result, only the bit address of VARA becomes the change point bit address of the encoding line, the word address remains unchanged, and the position of a ₁ is stored in VARA. The process 6202 increments the word address of VARB. In the decision 6203,
It is determined whether the reference line is the end of the line. If it is a line end, the process 6207 shifts to the incremented value b
_It is stored in TARB as ₁ . If it is not the end of the line, step 6204 follows and the VD of the reference line is input. Decision 62
At 05, it is determined whether or not b ₁ exists on the reference line.
If there is no change point, the difference between a ₁ and b ₁ is 8 or more, and therefore the H coding process is started. In this way, since the coding line and the reference line can be scanned in parallel, there is an effect that the H mode can be determined before the change point of the reference line is detected. If there is a change point, the process moves to step 6206 and b ₁
The position of is stored in the TARB. This is a ₁ for VARA
It can be realized by the same method as that stored in. Process 620
In step 8, (b ₁ −a ₁ = difference) is executed. This is VARA
To the A latch 2320, and TARB to the B latch 2
Latch to 330, turn off mask and turn these outputs AL
It is realized by inputting into the A and B ports of U2350 and executing (BA).

The output of the ALU2350 is latched by the latch 2501 and the mode determination circuit 2502 determines whether the difference is within 3 or not. If the difference is within 3, the process proceeds to the VL encoding process, and if the difference exceeds 3, the process proceeds to the H encoding process.

If there is a change point only in the reference line in the judgment 6110, the process goes to the process 6301. In process 6301,
Store b ₁ in TARB. In process 6302, the b ₂ detection mode is set. In process 6303, by outputting a latch pulse to the latch 2617 of the reference line change point detector 2610, the VD of the reference line input in process 6103 is output.
It is detected whether or not b ₂ exists in addition to b ₁ . This operation is called intra-word change point detection. This operation has been described in detail with reference to FIGS. 10 and 11 and Table 4. At decision 6304, it is decided whether or not b ₂ exists. If b ₂ exists, b ₁ and b before a _1
Since both ₂ existed, the P encoding process is started.
If b ₂ does not exist, the process proceeds to process 6305. Process 630
In step 5 and step 6306, the word addresses of VARB and VARA are incremented. In the determination 6307, the line end is determined, and if it is the line end, the process proceeds to Step 6319.
If it is not the end of the line, the process moves to 6308. Process 6308
Then, in process 6309, the VD of the reference line and the VD of the encoded line are input to the change point detector 2600, and b ₂ and a are input.
₁ is detected. If there is no change point, the process moves to process 6305. If there is only a change point in the reference line, b ₁ to a ₁ previously
Since there is a change point between b and b ₂ , the process moves to the P coding process. If there is a change point only in the coding line, process 6
Move to 313. In process 6313, the bit address of a ₁ is stored in VARA. VARA and T in process 6314
(A ₁ −b ₂ = difference) is obtained by taking the difference of ARB. In the determination 6315, it is determined whether the difference is 3 or less. If the difference is 3 or less, the VR coding process is started, and if it exceeds 3, the H coding process is started. Decision 6310 to Decision 6312
If there is a change point on both the reference line and the encoding line,
Move to processing 6316. In process 6316, a is added to VARA.
Store ₁ and store b ₂ in VARB. In process 6317
(VARB-VARA) is executed to detect the positional relationship between a ₁ and b ₂ . If (b ₂ −a ₁ ) is negative, that is, if the ALU 2350 underflows, it is determined that b ₂ is on the left of a ₁ , and the P encoding process is started. If underflow has not occurred, the process proceeds to process 6314. If it is determined at the determination 6307 that the line end is reached, the process proceeds to processing 6319. Process 6
At 319, the address at the line end is regarded as the position of a ₁ , and this address is stored in VARA, and (VARA-T
Run the ARB) seek (a ₁ -b ₁ = difference). If the difference is 3 or less, the VR code output subroutine is called in process 6327, and then the line end process is performed. If the difference exceeds 3, the process proceeds to process 6321. In process 6321, an H code output subroutine is called. In Process 6322, (VARA
-TARA) running obtain _{(a 1 -a 0 = RL)} . This RL
Are latched in the latch 2501. In process 6323, M
Call the H code output subroutine. Process 6324: a ₀
Invert the color of. In process 6325, the output of the ALU2350 is set to zero, and this is latched by the latch 2501 to generate (RL = 0). In process 6326, the MH code output subroutine is called to code (RL = 0), and the line end process is started. In the determination 6110, when there is a change point on both the coding line and the reference line, the process moves to the processing 6401. In process 6401, a ₁ is stored in VARA, and process 64
At step 02, b ₁ is stored in TARB. In processing 6403 (V
ARA-TARB) is executed, it calculates the (a ₁ -b ₁ = difference). When the difference is zero, the V (0) coding process is started. If the difference is positive, it means that a ₁ exists to the right of b ₁ , so it is necessary to detect whether or not b ₂ exists before a ₁ . Therefore, the processing shifts to the processing 6407, the b ₂ detection mode is set, and the processing 6408 detects the change point in the word of the reference line. If there is a change point, the process moves to the process 6412 if it does not move to the process 6412. In process 6412, b ₂ is stored in VARB. By executing in process 6413 a (VARB-VARA) obtaining the (b ₂ -a ₁ = difference). If the difference is negative, it means that b ₂ exists to the left of a ₁ , so P
Move on to encoding processing. If the difference is not negative, it means that b ₂ exists after a ₁ and the process 6410 starts. Process 641
At 0, it can be determined that the mode is not the P mode because b ₂ does not exist to the left of a ₁ , and (VARA-TARB) is executed to obtain (a ₁ -b ₁ = difference). If the difference is 3 or less, the process proceeds to the VL encoding process, and if it exceeds 3, the process proceeds to the H encoding process. If the difference is negative in the judgment 6406, it means that b ₁ exists to the right of a ₁ , and the process 6415 is entered. Process 641
In step 5, by executing (TARB-VARA),
(B ₁ −a ₁ = difference) is calculated. When the difference is 3 or less, the VR coding process is started, and when the difference is more than 3, the H coding process is started. With the above, the part of determining the mode by scanning the VM to detect the change point is completed. Next, a description will be given of the encoding processing in each mode.

The H encoding process starts from process 6501. In process 6501, the H code output subroutine is called. In process 6502, (VARA-TARA) is executed to obtain (a ₁ −a ₀ = RL), which is latched in the latch 2501 of the encoding table unit 2500. Process 6503
Then, the MH code output subroutine is called. Process 65
In 04, the color of a ₀ is inverted. In process 6505, the contents of VARA are moved to TARA and a ₁ is stored in TARA. In operation 6506, the change point in the word of the encoded line is detected. If there is a change point, the process 6513 is entered. If there is no change point, the process moves to process 6508. In process 6508, VAR
Increment the word address of A. At this time,
If it is Lin End, the process moves to processing 6511. If it is not Line End, the process shifts to the process 6510, the VD of the coding line is input to detect the presence / absence of a change point, and the process shifts to the process 6507. Process 6
In 511, the point at the end of the line is set to a ₂ and (VARA-
Run the TARA), determine the _{(a 2 -a 1 = RL)} . In process 6512, the MH code output subroutine is called,
Move to line end processing. If there is a change point in the determination 6507, the process moves to the process 6513. In process 6513, the position of a ₂ is stored by storing the bit address of the change point of the encoded line in VARA. In process 6514,
(VARA-TARA) is _{executed, (a 2 -a 1 = RL} )
Ask for. In process 6514, the MH code output subroutine is called. Processes 6522 to 6527 are post-processes for scanning the reference line and the encoding line again in parallel and shifting to the mode determination process. First, processing 652
In 2 inverts the color of a ₂ . By transferring the contents of VARA to TARA in process 6523, a ₁ or a ₂ is newly stored as a ₀ . In process 6524, the contents of TARA are transferred to VARB in order to restore the scan address shift between the reference line and the encoded line, and thus a ₀
And b ₀ are aligned. In process 6525, the b ₁ detection mode is set. In process 6526, the contents of TARA are latched in the B latch 2330 and the contents of VARB are latched in the A latch 2
The reference line address return of the reference line change point detector 2610 is turned on, and the reference line V
Latch D in latch 2617. As a result, the mask circuit 2616 operates and the VD of the reference line input up to the bit address of the B latch 2330, that is, the bit address of a ₀ is masked and latched by the latch 2617. This makes it possible to detect a change point immediately above a ₀ , that is, to the right of b ₀ . The processing 6526 has an effect that the scanning start addresses of the reference line and the coded line can be matched accurately and at high speed in bit units. In process 6527, the change point detection operation in the word of the encoded line is performed, the process proceeds to decision 6105, and the mode decision is started again. Next, the VL encoding process will be described. The VL encoding process starts from process 6521. In process 6521, the VL code output subroutine is called, and the process 6522 follows. The processings after the processing 6522 have already been described.

Next, the VR encoding process will be described. First,
In process 6531, the VR code output subroutine is called,
Move to processing 6522. The process 6522 and subsequent steps have already been described.

Next, the V (0) coding process is started. First, in process 6541, a V (0) code output subroutine is called. Process 6542 and subsequent processes are post-processes for moving to the mode determination process again. In the case of V (0), since the scanning points of the reference line and the encoding line match, no special processing for matching the scanning points is necessary. In processing 6542, a ₀
Invert the color of. In processing 6543, the contents of VARA are TA
By moving to RA, a ₁ is newly set as a ₀ . Process 6
At 544, the change point within the word of the reference line is detected.
In process 6545, the change point in the word of the encoded line is detected, the process returns to the determination 6105, and the mode determination process is continued again.

Next, the P coding process will be described. Process 6
At 551, the P code output subroutine is called. Process 6
At 552, the bit address of b ₂ is written to the bit address of VARB to store the position of b _{2 as} the position of b ₀ in VARB. In processing 6553, VARB
By moving the contents of the above to TARA, a ₀ and b ₀ are made to coincide, and the position of b ₂ is newly stored in TARA as a ₀ . In processing 6555, the b ₁ detection mode is set, and processing 655
At 6, the intra-word change point detection operation of the reference line is performed, and the process returns to the determination 6105.

This is the end of the description of the encoding process in each mode. Next, the code output subroutine of each mode will be described. The output of each code is all the encoding table unit 250.
This is done by operating 0. That is, the latch 25
This is realized by causing the address generating circuit 2503 to generate a specific address according to the output of the ALU 2350 latched at 01, that is, RL or difference, and the mode signal from the control unit 2200 that has performed the mode determination, and accessing the encoding table ROM 2504. . Here, the V (0) code output subroutine is described as an example, and the others are omitted.

The V (0) code output subroutine is executed in process 66.
It starts from 01. In processing 6601, the address generation circuit 2
The address (1000000) where the V (0) code is stored in 503
00) ₂ is generated. In process 6602, the encoding table RO
The contents of M2504 are loaded into the shift register 2505.
Since the V (0) code is defined as “1”, the shift register 2505 is loaded with (11000000000000) ₂ . The most significant bit is a V (0) code, and the second bit "1" is for end detection. At decision 6603, the termination is determined by the termination flag from the termination detection circuit 2506 which detects the termination (Terminate) by detecting whether the output of the shift register 2505 is (10000000000000) ₂ . If it is finished, it returns. If not, the process 6604 is entered. Process 660
4, the shift register 2505 and the S / P converter 250
7 outputs a shift pulse to shift the most significant bit of the shift register 2505, that is, “1” in this case to the S / P converter 2507. In process 6605, GRA of the file register 2310 is latched in the A latch 2320, the A mask 2341 is turned off and input to the ALU2350, (A + 1) is executed by the ALU2350, and this output is GRA.
By writing to, the GRA is incremented and the total number of code bits is counted. In process 6606,
The contents of GRB are decremented by the same method as the processing 6606. GRB has a code of 8 in the S / P converter 2507.
It is to determine whether or not a bit has been generated. Judgment 6
At 607, it is determined whether the content of GRB is zero. If it is zero, it can be determined that the S / P converter 2507 generated the code of 8 bits, and the process proceeds to the determination 6608. Judgment 6608
Then, it is determined whether or not the FIFO memory 2508 is an input ready. If it is not input ready, it waits. If it is an input ready, the process proceeds to step 6609. Process 6609
Then, load the 8-bit code of the S / P converter 2507 into the FIFO2508, input 8 to the B port of the ALU2350 in step 6610, execute (O + B), and write this output to GRB to write to GRB. Set 8. Next decision 66
Move to 03. In the determination 6603, in this case, the content of the shift register 2505 is (10000000000000) ₂ , so it is determined to end and the process returns. This is the end of the detailed description of the microprogram flow of the MR encoding process.

Next, regarding MR decoding processing, Table 7 and FIG.
From FIG. 27 will be described.

[0070]

[Table 7]

Table 7 describes the function of each register during the MR decoding process. VARA is a virtual word and bit address of a position where the restored data is written in the VM of the decoding line. VARB is the virtual word and bit address of the scan position of the reference line. TARA is a
It is a virtual word and bit address of ₁ or a ₂ . GRB is for 8-bit counting of the P / S converter 2511. SARA and SARB are the real word addresses at the beginning of the decoding line and the reference line, respectively. TRAB is the number of pixels in one line (word unit). The VD can be transferred between the recording unit and the VM in parallel with the decoding process, but here, VARC, TRC, SAR
C is assigned. VARC is a virtual word address of the transfer line, and TRC is the number of transfer pixels in word units. SARC is the real word address at the beginning of the transfer line. By arbitrarily selecting the values of SARA and SARC, and TRAB and TRC, it is possible to transfer an arbitrary one portion of the restored VD to the recording unit.

24 to 27 are microprograms for MR decoding processing. The processing within the range indicated by processing 7102 and A is a portion for decoding the MR code and determining the mode. Process 7101 is initialization at the beginning of the line. For example, it is a process of clearing VARA and VARB. In process 7102, the head address of MR code decoding is generated in the address generation circuit 2513 of the decoding table section shown in FIG. Decryption table ROM2514
However, since the structure is as shown in Table 3, A _{9 to} A ₉
"10000000" occurs in _1. At decision 7103, it is decided whether or not the content of GRB is zero. If it is zero, it can be determined that there is no code in the P / S converter 2511.
Go to 4. If it is not zero, the process moves to step 7107. Judgment 7
At 104, it is determined whether a code exists in the FIFO 2510. If there is no code, wait. If the code exists, the process moves to 7105. In process 7105, the P / S converter 25
Load the output of FIFO 2510 into 11. In process 7106,
Set GRB to 8 and P /
It is stored that the S converter 2511 has 8 bits of codes. In process 7107, a shift pulse is output to the P / S converter 2511, and the code at the beginning of the P / S converter 2511 is the EOL detection circuit 2512 and the address generation circuit 2513.
To load. In process 7108, the P / S converter 2511
In order to remember that the sign of
Decrement B. In the determination 7109, EOL is determined. This is done in the EOL detection circuit 2512. EO
The L detection circuit 2512 determines whether or not the code sequence input from the P / S converter 2511 is "000000000001", and can be configured by an S / P converter and a gate. If it is EOL, move to line end processing, and if it is not EOL, process 711
Move to 0. In process 7110, the decryption table ROM 2514 is accessed and the output is latched in the latch 2515.
At decision 7111, it is determined whether the code is completed. This is because the decoding table ROM 2514 is configured as shown in Table 3, so that it can be determined whether the least significant bit of the contents of the decoding table ROM 2514 latched in the latch 2515 is 1 or 0. If the code is not completed, the process proceeds to step 7112. In process 7112, D _{1 to} D ₇ of the contents of the decoding table ROM 2514 latched in the latch 2515 are fed back to the address generation circuit 2513 and used as A _{1 to} A ₇ . Next, returning to the determination 7103, the processing in the range indicated by A is continued until the code is completed. If it is determined in decision 7111 that the code has been completed, the MR code mode is determined from the contents of the decoding table ROM 2514 latched in the latch 2515, and the process proceeds to the decoding processing program for each mode.

First, the P decoding process will be described. Process 72
At 01, the VD of the reference line is input, and the change point b ₁ on the right of a ₀ is detected. This processing is the same as the method described in detail when the processing 6526 is described. If there is a change point, the process moves to process 7206. If there is no change point, the process moves to process 7203. In process 7203, the word address of VARB is incremented. At decision 7204,
The value obtained by incrementing the word address of VARB and T
When the RAB values match, that is, when the line ends, the error process is started. If it is not the line end, the process moves to 7205. In process 7205, the VD of the reference line is input, b ₁ detection is performed, and the process returns to determination 7202. When b ₁ is detected, the process proceeds to process 7206. In operation 7206, the change point b ₂ in the word of the reference line is detected. If there is a change point in the judgment 7207, the process moves to the process 7211, and if it does not exist, the process 72
Go to 08. In process 7208, the word address of VARB is incremented. The line end is determined in the determination 7209, and if it is a line end, the process proceeds to error processing, and if it is not a line end, the process 7210 proceeds. In process 7210, the VD of the reference line is input, the b ₂ detection process is performed, and the process proceeds to determination 7207. In processing 7211, the word address of VARB,
Write the change point bit address of the reference line to TARA.
In process 7212, the image signal restoration subroutine is called,
The procedure returns to processing 7102. The image signal restoration subroutine is V
This program restores an image signal from the position indicated by ARA to the position indicated by TARA, which will be described in detail later. This is the end of the P decoding process.

Next, the V (0) decoding process will be described. Process 7
At 213, the VD of the reference line is input and the change point b ₁ on the right of a ₀ is detected. In decision 7214, the presence / absence of a change point is determined. If a change point exists, the process proceeds to process 7218, and if not, the process proceeds to process 7215. VARB in process 7215
Increment the word address of. The line edge is determined in the determination 7216, and if it is the line edge, the line edge is set to b ₁ and the process 7218 is entered. If it is not the line end, process 72
Move to 17. In process 7217, VD of the reference line is input, b _{1 is} detected, and the process returns to decision 7214. If b ₁ exists, the process proceeds to step 7218, and T is set with the word address of VARB and the change point bit address of the reference line as a _1.
Write to ARA and call image signal restoration subroutine in process 7219. In process 7220, the color of a ₀ is inverted, and the process returns to process 7102. This is the end of the V (0) decoding process.

Next, the VL decoding process will be described. In process 7301, the VD of the reference line is input and b ₁ on the right of a ₀ is detected. If there is a change point in the determination 7302, the process moves to process 7306, and if it does not exist, the process moves to process 7303. In processing 7303, the word address of VARB is incremented. The line edge is determined in the determination 7304, and if it is the line edge, the line edge is set to b ₁ and the process 7325 is entered. If it is not the end of the line, the process proceeds to step 7305, the VD of the reference line is input, b ₁ is detected, and the process proceeds to determination 7302.
If there is a change point, the process proceeds to step 7306, and the change point bit address of the reference line is stored in VARB to obtain b
Store the position of ₁ in VARB. In processing 7325, the difference between b ₁ and a ₁ latched by the latch 2515 is calculated by ALU2350.
Input to the A port of the
To the ALU 23 by turning off the B mask 2342.
Enter the 50 B port, (B-A) by the run - seeking (b ₁ difference = a _1), stores it in the TARA. In this way, the output of the decoding table is directly ALU2350
Since it is inside, there is an effect that the position of a ₁ can be obtained at high speed. At decision 7326, if the operation result of the ALU2350 is negative, it is decided as an error. In the determination 7307, (TARA-VARA) is performed, and if the result is negative, it is determined to be an error. In process 7308, the image signal restoration subroutine is called. In process 7309, the contents of VARA are changed to V
The new a ₀ and b ₀ positions are aligned by writing to the ARB. In process 7310, the color of a ₀ is inverted, and the process
Return to 7102. This is the end of the VL processing.

Next, the VR decoding process will be described. Process 73
At 11, the VD of the reference line is input, and the change point b ₁ on the right of a ₀ is detected. If the change point exists in the judgment 7312, the process moves to the process 7315, and if the change point does not exist, the process 732.
Move to 2. In process 7322, the word address of VARB is incremented. The line edge is determined in the determination 7313, and if it is the line edge, error processing is performed. If it is not the line end, the process moves to processing 7314. In process 7314, VD of the reference line is input, b ₁ is detected, and the process proceeds to determination 7312. If there is a change point, in process 7315, the bit address of the reference line change point is stored in VARB. In process 7316, the difference from the decoding table and VARB are added and stored in TARA as a ₁ . If the result of addition at decision 7317 is an overflow, then error processing is entered. If there is no overflow, the image signal restoration subroutine is called in step 7318, the contents of TARA are transferred to VARB in step 7319, and new a ₀ and b ₀ are made to match. In process 7320, the color of a ₀ is inverted, and the process returns to process 7102. This is the end of the VR decoding process.

Next, the H decoding process will be described. Process 740
At 1, the address generation circuit 2513 is caused to generate a start address for decoding the MH code. In the case of the configuration shown in Table 3, if the color of a ₀ is white, set A _{9 to} A ₁ to “00
0000000 ”, and if the color of a ₀ is black, it is“ 010000000 ”. The MH code is found by performing the processing of the area indicated by A in processing 7402. Decision 7403
Then, the decryption table ROM2 latched in the latch 2515
The D ₇ bit of 514 is determined, and if it is “0”, it is determined to be a terminating code and the process proceeds to step 7406. If it is "1", make up code
e) is determined, and the process 7404 is performed. In process 7404,
The outputs D ₁ to D ₇ of the latch 2515 are changed from 2 ⁶ to 2 of RL.
Input it to the A port of ALU2350 as ¹¹ bits, and TARA
Is added to the contents of, and this is written to TARA. Decision 74
In 05, it is determined whether the added result is an overflow,
If it is an overflow, it moves to error processing, and if it is not an overflow, it moves to processing 7401.

When the end code is detected, the process proceeds to step 7406, and the outputs D _{1 to} D ₇ of the latch 2515 are input to the A port of the ALU2350 as 2 ⁶ to 2 ¹¹ bits of RL, and TA
The contents of RA are added and the result is written to TARA. In the determination 7407, it is determined whether or not the added result is an overflow. If it is an overflow, the process proceeds to error processing, and if it is not an overflow, the process proceeds to process 7408. The process 7408 calls the image signal restoration subroutine, and the process 7409 inverts the color of a ₀ . In process 7410, the region indicated by B is processed. In process 7411, the content of TARA is VARB
Then, the new a ₀ and b ₀ are matched and the process 7102 is started. This is the end of the description of the decoding process in all modes.

Next, the image signal restoration subroutine will be described. Here, a ₀ is stored in the VARA, a ₁ is stored in the TARA. Therefore, it is necessary to change the color to a ₀ from VARA to the position indicated by TARA. Process 7412
Then, the word address difference between VARA and TARA is detected. This latches VARA into the A latch 2320,
TARA is latched in the B latch 2330, and the A mask 23
41 and B mask 2342 are turned on, input to ALU2350, and BA is executed. If the result is zero, there is no word difference. Thus, since there is a circuit for masking the bit address, there is an effect that the word address difference can be obtained at high speed. At this time, the image signal restoration circuit 27
Since the word difference presence / absence signal and the bit address of the write start and end points are supplied to 01, the image signal in the word can be output at high speed simply by outputting the latch pulse to the latch circuit 2704 and the temporary storage register 2702 in process 7413. There is an effect that can be restored to. In decision 7414, it is determined whether there is a word address difference, and if there is no word address difference, the image signal has been restored up to the point a ₁ indicated by TARA, and the process returns. If there is a word address difference, the process proceeds to process 7415. If there is a word address difference, the image signal of one word has been restored in the latch circuit 2704, and therefore the output of the latch circuit is changed to (VARA +
The image signal is restored to the decoding line by writing to the address indicated by the word address of (SARA). Process 741
At 6, the temporary storage register 2702 is cleared. Process 74
At 17, the VARA word address is incremented. This latches the contents of VARA into the A latch 2320, and TR
The contents of AB are latched in the B latch 2330 and the A mask 23
Turn on 41 and input to A port of ALU2350, ALU235
Since 8 is input to the B port of 0 and (A + B) is executed and the result is written to VARA, clearing of the bit address of VARA and detection of the line end by the equality comparator 2370 are performed at the same time when the word address of VARA is incremented. The effect is that you can do it. At decision 7418, it is decided whether the line end is reached or not. If it is not the line end, the process returns to step 7412 and the image signal restoration process is continued. If it is the end of the line, the flow shifts to determination 7419, and it is determined whether VARA and TARA match. If they do not match, error processing is performed.
If they match, the process goes to line end processing.

This is the end of the description of the microprogram flow of the MR decoding process.

28 and 29 show an example in which a facsimile is constituted by a Codec, a microcomputer and the like.

FIG. 28 shows an example in which the VBus of Codec 2000 and the system bus of the microcomputer 8010 are shared. The microcomputer 8010 may be a general-purpose microcomputer such as Intel 8085 or Motorol 6800. The microcomputer 8010 issues an appropriate parameter setting and macro command to the Codec 2000. For example, in the case of encoding processing, first, a scanning command is issued to the reading unit 1000. When the reading unit 1000 receives a scanning command from the microcomputer 8010, the reading unit 1000 scans the document and generates an image signal (VD). And Code
c Output TDRQT to 2000. Codec 20
00 indicates the reading unit 100 by the method described with reference to FIG.
The VD from 0 is transferred to the video memory (VM) 8020 by DMA. When the transfer of one line is completed, Codec 20
00 outputs an interrupt request (IRQ) to the microcomputer 8010. In this way, the microcomputer 8010 has 1 line
It is possible to transfer the VD for one line by setting the parameter in Codec 2000 once every two times. Also, the microcomputer 8
When 010 issues a macro command for encoding processing to Codec 2000, Codec 2000 inputs VD from VM, performs encoding processing, and outputs the code to DBus of microcomputer 8010. The microcomputer 8010 stores the code in the code memory 8030. Further, the microcomputer 8010 outputs the code in the code memory to the modulation / demodulation device 3000.
In this way, the facsimile transmitter can be easily constructed. The receiver can be configured with this system as well. Further, the system bus of the microcomputer 8010 and the video bus of Codec are shared. The VM 8020 and the code memory 8030 may be the same chip, which has the effect of downsizing and cost reduction.

FIG. 29 is an example of a system in which the system bus of the microcomputer 8010 and the video bus of Codec 2000 are separated. Since the image signal is transferred on the VBus and the code is transferred on the system bus, there is an effect that encoding and decoding can be performed at high speed. Also, DM on the system bus side
Since the AC8060 is used and the code can be transferred by the DMAC8060, there is an effect that the load on the microcomputer 8010 can be further reduced. In addition, VM8020 is a microcomputer 8
Since it is irrelevant to the address space of 010, it is not limited to the space of 64 kilobytes (K byte) which is a general address space of an 8-bit microcomputer, and has an effect of having a large-scale VM. For example, the VA generator 24
By configuring the hardware in 00 with a 24-bit configuration,
Codec 2000 VA space is 16 megabytes (M byte)
Can be

The case where the present invention is applied to a facsimile has been described above as an example, but any system that handles MH code, MR code, or both can be used, and can be applied to, for example, an image file system. Further, by providing a circuit for generating refresh timing and a register for storing a refresh address, the refresh RAM can be used for the VM.

[0085]

The effects obtained by the present invention are as follows.

(1) Since the change point detection and the image signal restoration are parallel processing, high speed processing can be performed.

(2) Since it has a microcomputer bus I / F, it can be directly connected to the microcomputer bus, and the system can be made compact and easy.

(3) Since the video bus (VB) and the system bus (SB) can be shared, the code memory and the image memory can be shared.

(4) Since the video bus (VB) and the system bus (SB) can be separated, it is possible to move simultaneously on buses with different codes and images, so that high speed processing can be performed. Further, it is possible to have a large VM without being limited to the address space of the microcomputer.

(5) Since the codec has a micro program and a sequencer, it can be operated by a macro command for each line or page from the microcomputer, and the load on the microcomputer is small.

(6) Since a parameter can be set in each register in the Codec from the microcomputer, flexible processing is possible.

(7) Since it has a horizontal pixel number register (HWR), a line number register (LNR), a start address register (SAR), and a terminal register (TR),
Arbitrary rectangular area of one screen can be processed.

(8) Since the ALU of the arithmetic unit, the table unit, the change point detection unit and the image signal restoration unit are directly connected, high speed processing is possible.

(9) Since the virtual address system is adopted in the arithmetic unit, the hardware amount of the arithmetic unit can be reduced and the arithmetic operation can be performed at high speed.

(10) Since both the word address and the bit address can be handled at the same time, the change point processing can be performed at high speed.

(11) Since the timing control is collectively managed by the control unit composed of the microprogram and the sequencer, the design is easy and the LSI is easy.

(12) Channels for encoding and decoding processing,
Since the transfer channel is independently provided, it is possible to encode an arbitrary part of the image signal from the reading section or transfer an arbitrary part of the decoded image signal to the recording section.

[Brief description of drawings]

FIG. 1 is an overall block diagram of a facsimile.

FIG. 2 is an explanatory diagram of a hierarchical structure of encoding / decoding processing.

FIG. 3 is an overall block diagram of Codec.

FIG. 4 is a block diagram of a control unit.

FIG. 5 is a block diagram of a calculation unit.

FIG. 6 is a block diagram of a video address generator.

FIG. 7 is an explanatory diagram of page mode processing.

FIG. 8 is a block diagram of an encoding table unit.

FIG. 9 is a block diagram of a decoding table unit.

FIG. 10 is a block diagram of a change point detection unit.

FIG. 11 is a detailed circuit diagram of a mask circuit in the change point detection unit.

FIG. 12 is a block diagram of an image signal restoration unit.

FIG. 13 is a detailed circuit diagram of an image signal restoration circuit.

FIG. 14 is a state transition diagram of Codec during encoding / decoding processing.

FIG. 15 is a state transition diagram of the Codec when the microcomputer accesses the VM via the Codec.

FIG. 16 is a state transition diagram of Codec during image signal transfer.

FIG. 17 is an explanatory diagram of an MR encoding system.

FIG. 18 is a microprogram flow of MR encoding processing.

FIG. 19 is a microprogram flow of MR encoding processing.

FIG. 20 is a microprogram flow of MR encoding processing.

FIG. 21 is a microprogram flow of MR encoding processing.

FIG. 22 is a microprogram flow of MR encoding processing.

FIG. 23 is a microprogram flow of MR encoding processing.

FIG. 24 is a microprogram flow of MR decoding processing.

FIG. 25 is a microprogram flow of MR decoding processing.

FIG. 26 is a microprogram flow of MR decoding processing.

FIG. 27 is a microprogram flow of MR decoding processing.

FIG. 28 is a block diagram of a facsimile system using a Codec.

FIG. 29 is a block diagram of a facsimile system using a Codec.

[Explanation of symbols]

2100 ... MPUI / F, 2200 ... control section, 2300
... Calculation unit, 2400 ... Video address (Video Addres
s) Generation unit 2500 ... Table unit 2600
... Change point detection unit, 2700 ... Image signal restoration unit, 2800
… VBus I / F.

Claims (1)

[Claims] 1. A code having reading means for reading an original to generate an image signal, coding means for converting the read image signal into a code signal, and decoding means for decoding the code signal into an image signal. An encoding / decoding device, an image memory for recording the image signal generated by the reading means and an image signal decoded by the encoding / decoding device, and the decoded image signal is called from the image memory and recorded. A recording means, an image bus for connecting the encoding / decoding device, the image memory, the reading means, and the recording means to flow the image signal, a microcomputer for controlling the system, and transmission / reception for transmitting / receiving the code signal to / from the outside. Means, a code memory for recording the received code signal and the code signal of the encoding / decoding device, and a code bus for flowing the code signal and the program. Facsimile apparatus characterized by.