JPH02146650A - Bus analyzer - Google Patents

Abstract

PURPOSE:To attain a simple and compact constitution of a bus analyzer by monitoring the address value of a transfer cycle, setting a corresponding bit when an address equal to the preceding one or an address following the preceding one is decided and storing the data on the transfer cycle. CONSTITUTION:The present data is stored in a memory 6 together with the present address when the present transfer address is different from the preceding transfer address and the value produced by an internal adder 4. When the present address is coincident with the preceding address, the same address bit is set and the present data is stored in the memory 6. While the next address bit is set and the present data is stored in the memory 6 when the present address is coincident with the value produced by the adder 4 contained in a bus analyzer. Thus it is not required to store the address data on all transfer cycles into the memory 6. As a result, the memory area can be reduced and a simple and compact bus analyzer is obtained.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a bus analyzer installed in a computer system and used for analyzing the behavior of the system. This is what we aim to do.

<Prior Art> A bus analyzer is sometimes used in a computer system to analyze whether the operation is normal or abnormal.

This bus analyzer stores addresses and data sent to the system bus in memory one by one for each transfer cycle, and the operator can refer to this memory to
System operation can be checked.

<Problem to be solved by the invention> Recently, there has been a tendency to increase the address and data width of the system bus, and the bus analyzer also needs to increase its memory area in response to this. However, in order to increase the memory area, it is necessary to prepare and install twice or even three times as many memory elements as before, and the bus analyzer itself has to deal with memory mounting space, memory control section, etc. There were problems in that it became large and its configuration became complicated.

The present invention solves the above-mentioned problems, and aims to realize a bus analyzer with a simple configuration and a small size.
target

<Means for Solving the Problem> The present invention monitors the transfer address, checks whether it matches the previous address, and whether it matches the address value generated internally, sets corresponding bits, and transfers the address. →
It is designed to store Fuikuru data,
Its composition is as follows.

That is, the present invention includes: a register that holds the address value in the previous transfer; a first comparator that compares the value held in this register with the address value in the current transfer;
An adder that adds a value corresponding to the size of the data lotus to the value held in the register, a second comparator that compares the output value of this adder with the current address value, and a memory ( Iiii, if the first comparator and the second comparator fail to rescue the current transfer address value and the current transfer data, the current transfer address value and the current transfer data are stored in the memory, and a match is detected from the first comparator. When an output is made, the same address bit is set and the current data is stored in the memory, and when a match is output from the second comparator, the next address bit is set.
The bus analyzer is characterized in that it is provided with a control means for setting a bit and storing current data in the memory.

Functions The bus analyzer of the present invention operates as shown in the following (a) and (c) regarding addresses and data in a transfer cycle.

(If the current transfer address is different from the previous transfer address and the value generated by the internal adder, the current data is stored in the memory along with the current address.

(b) If the current address matches the previous address,
Set the same address pin 1~ and store the data this time in the memory.

(c) If the current address matches the value generated by the adder of the Hass analyzer itself, set the next address to Hira 1 and store the current data in the memory.

<Embodiment> FIG. 1 is a block diagram of a bus analyzer embodying the present invention.

In this 1-in-1, 1 is the system bus involved in the transfer of address 1 data, 2 is the register that holds the address value of system bus 1, and 3 is the register that holds the value in register 2 and the current transfer address value. 4 is an adder that adds a value corresponding to the data width to be transferred to the value in register 2; 5 is a second comparator that compares the output value of adder 4 with the current transfer address value. Comparator 6 is memory.

Here, the adder 4 is configured to generate the next transfer address for the address value held in the register 2. That is, if the data width to be transferred is 16 bits, add +2 to the value in register 2, and if the data width is 32 bits, add +4.
to add. In addition, the data to be transferred is 1 by 1 to 8 bits I.
~) unit, and the transfer address always corresponds to the first byte of the transfer data.

Next, the internal configuration of the memory 6 is shown in FIG.

The memory 6 is allocated with the same address, bit area, 121st address bit area F2, and storage area X.

Now, the operation of the bus analyzer of the present invention configured as described above will be explained next.

In the first transfer cycle (a), both the transfer address a1 and the transfer data d1 are stored in the storage area X of the memory 6 as they are. At this time, the same address bit area 1
-''I9th address pin 1 '0'' is set in area F2.

In the next transfer cycle (b), the current address a2 sent on the system path I is compared with the previous address m a, ] held in the register 2 in the first comparator 3.

Simultaneously with this operation, the value a1 in the register 2 is added with a value that is 1,6 times the data width in the adder 4, and the adder 4
The second comparator 5 compares the output value a1* with the current address a2 sent to the system bus 1.

If the current address a, 2 matches the previous address a1 held in the register 2, the matching output of the first comparator 3 causes the same address bit 1 to be stored in the memory 6.
"]'" is set, and the data d2 at this time is stored at the same time. The next address bit I/2 remains at "'0°".

In the next transfer cycle (c), a new transfer address a3 is added.
．． Assume that data d3 is sent.

In the same manner as in the previous transfer cycle (<17), the first axis ratio device 3 compares the current address a3 with the previous address values a and 2 of the register 2. The second comparator 5 compares the current address a,3 with the output value a2* of the adder 4.

Then, when the first comparator 3 outputs a mismatch and the second comparator 5 outputs a match, the memory 6 stores
The same address pins 1-F1 are set to "0", and the next address pins I-F2 are set to "1'".Then, the data d3 sent out at this time is stored in area X.

Regarding the address a4 transferred in the next transfer cycle (d), the first . If both outputs of the second comparator 3.5 do not match, the same address bit 1-Fl'''0'' and the next address bit YS2 are both 0'.

or address a4. The data d4 is stored in the memory 6.

Thereafter, the same operation is repeated.

In this way, the bus analyzer of the present invention sets the same address bit when the address value sent to the system bus matches the previous address value, and sets the next address bit when it matches the internally generated addition value. Set the address bit, and if it does not match the previous address and the added value, the corresponding address,
Write both data to memory.

Finally, when analyzing the behavior of the system, refer to memory 6 and select the same address bits secondary address bits 1 to 2.
If both are set, both the data and address are read from the memory, and if the same address bit is set, it is assumed that data corresponding to the same address as the previous cycle is stored, and the next address is read. If P1~ is set, it is assumed that data corresponding to the address next to the address of the previous cycle is stored, and a system analysis operation is performed.

<Effects of the Invention> According to the bus analyzer of the present invention, the address value in the transfer cycle is monitored, and when it is determined that the address is the same as the previous address or the next address of the previous address, the same address bit or the next address bit is Since it is set and only the data at that time is stored, there is no need to store addresses and data for all transfer cycles in the memory, and the memory area can be reduced accordingly. Therefore, the configuration is simple and a compact bus analyzer can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a bus analyzer embodying the present invention, and FIG. 2 is a diagram showing the internal configuration of a memory installed in the bus analyzer of the present invention. 1...System bus, 2...Register, 3...
First comparator, 4... Adder, 5... Second comparator, 6... Memory.

Claims (1)

[Claims] (1) A register that holds the address value in the previous transfer; a first comparator that compares the value held in this register with the address value in the current transfer; The first comparator includes an adder that adds a value according to the size of the bus, a second comparator that compares the output value of the adder with the current address value, and a memory. When the second comparator outputs a mismatch, the current transfer address value and the current transfer data are stored in the memory, and when the first comparator outputs a match, the same address bit is set and the current transfer data is stored in the memory. A bus characterized in that it is provided with a control means for storing data in the memory, and setting a next address bit when a match is output from the second comparator to store the current data in the memory. analyzer.