JPH0214409A - Head changeover processing circuit - Google Patents

Abstract

PURPOSE:To correctly execute the changeover of a read/write head even when a noise is mixed in a head select signal by recording the condition of the head select signal into a shift register in three stages or above, fetching the condition of each stage and deciding the condition as a whole with a majority logic. CONSTITUTION:A shift register 1 is in three stages or above, and the condition of an inputted head select signal C1 is recorded according to an inputted clock signal S2. A majority logic circuit 2 fetches the condition of each stage of the head select signal S1 recorded to the shift register 1, the condition as the whole is decided by the majority rule, and a majority output signal S4 is outputted. A latch circuit 3 latches the condition of the majority output signal just before when an inputted write gate signal S5 or a read gate signal is active, and a head selecting signal S6 is outputted. Thus, even when the noise is mixed in the head select signal S1, the changeover of the read/write head can be correctly executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is utilized for head switching processing of a magnetic disk device.

The present invention relates to a head switching processing circuit that performs head switching processing in a magnetic disk storage device having a plurality of read/write heads.

〔overview〕

The present invention provides a head switching processing circuit in a magnetic disk storage device having a plurality of read/write heads, which records the state of an input head select signal in three or more stages of shift registers according to an input clock signal, and
The state of each stage of this shift register is taken out, the overall state is determined by majority logic, a majority decision output signal is output, and when a write gate signal or a read gate signal is input, the state of the majority decision output signal immediately before that is latched. By outputting a head selection signal, even if noise is mixed into the head selection signal, the read/write heads can be switched correctly.

[Conventional technology]

Conventionally, this type of head switching processing operation in a magnetic disk storage device involves directly selecting a read/write head using a single or multiple head select signals sent from a disk control device that controls the magnetic disk storage device. A write operation table and a read operation are performed on the head selected by the write gate signal or read gate signal sent from the head.

[Problem that the invention seeks to solve]

In the head switching processing operation in the conventional magnetic disk storage device described above, the selection operation of a read/write head that performs a write operation or a read operation is directly switched by a single or multiple head select signal sent from a disk control device. If noise or the like is mixed into the head select signal during a write or read operation for a selected read/write head using a write gate signal or a read gate signal sent from the disk controller, the write operation for a different read/write head due to the noise may occur. There was a drawback that the operation or read operation was performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a head switching processing circuit that can correctly switch read/write heads even when noise is mixed into the head select signal by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a head switching processing circuit in a magnetic disk storage device having a plurality of read/write heads, in which at least one stage of three or more stages records the state of an input head select signal according to an input clock signal. a shift register; at least one majority logic circuit that inputs the state of each stage of the shift register, determines the state by majority logic, and outputs a majority output signal; and when the input write gate signal or read gate signal is active. The present invention is characterized in that it includes at least one latch circuit that latches the immediately previous state of the majority output signal and outputs a head selection signal.

[Effect]

The shift register has three or more stages and records the state of the input head select signal according to the input clock signal. The majority logic circuit extracts the state of each stage of the head select signal recorded in the shift register, determines the overall state by majority logic, and outputs a majority output signal. When the input write gate signal or read gate signal is active, the latch circuit latches the state of the majority output signal immediately before it and outputs a head selection signal.

Therefore, even if noise mixes into the head select signal, it will not appear in the majority output signal unless it spans the period of the clock signal, and any noise that mixes into the head select signal during write or read operations will be ignored. It becomes possible to do this.

〔Example〕

In this embodiment, in a head switching processing circuit in a magnetic disk storage device having a plurality of read/write heads, a clock signal that receives the state of one head select signal S1 input from a magnetic disk control device (not shown) is used. S
one three-stage shift register 1 for recording according to 2;
First, second and third shift register output signals s3. representing the states of each stage of the shift register 1; , s3□ and 33
one majority logic circuit 2 which inputs 3 and determines the state by majority logic and outputs a majority output signal S4; and a write gate signal S5 input from the magnetic disk control device.
The head selector circuit 3 includes one latch circuit 3 that latches the state of the immediately preceding majority output signal S4 when active, and outputs a head selection signal S6.

Note that this embodiment shows a case where there is one head select signal S1, and when there are a plurality of N head select signals S1, there are also a plurality of N shift registers 1, majority logic circuits 2, and latch circuits 3. Each is connected in the same manner as in FIG.

The feature of the present invention is that in FIG. 1, a shift register 1,
This is because a majority logic circuit 2 and a latch circuit 3 are provided.

Next, the operation of this embodiment will be explained with reference to the timing diagram shown in FIG.

The head select signal S1 is input to the shift register 1, and is sequentially captured at the rising edge of the clock signal S2 as shown in the first shift register output signal S33, the second shift register output signal 532J, and the third shift register output signal S3z. . The majority logic circuit 2 receives the first shift register output signal S3. , the second shift register output signal S3□, and the third shift register output signal S33 are inputted, a logical majority decision is made, and a majority decision output signal S4 is output.

With respect to the noise contamination shown in A of the head select signal Sl in FIG. S3z responds sequentially to B, C, and D shown in FIG. 2, but this does not affect the majority output signal S4, which is their majority output signal.

The majority output signal S4 is latched by the latch circuit 3 in a state immediately before the write gate signal S5 becomes active when the write gate signal S5 is active, and is output by the latch circuit 3 as a head selection signal S6 which is an actual read/write head selection signal. Output.

As explained above, in this embodiment, the head select signal S
Noise mixed into the head select signal S1 can be made invalid unless it spans the cycle of the clock signal S2, and furthermore, any noise mixed into the head select signal S1 during the write operation can be made invalid.

Note that although this embodiment has been described in the case of a write operation, a read operation can be similarly performed by replacing the write gate signal with a read gate signal.

Further, in this embodiment, although the shift register 1 has three stages, the number of stages can be made larger than three stages in response to the requirement for operational accuracy of the device.

〔Effect of the invention〕

As explained above, the present invention sequentially captures a head select signal into three or more stages of shift registers using a clock signal, performs a logical majority decision on the output state of each stage of the shift register using a majority logic circuit, and outputs a majority output signal. When the write gate signal or read gate signal is active, the latch circuit latches the state immediately before the write gate signal goes active, and the output of the latch circuit is used as the actual read/write head selection signal, which is mixed into the head selector signal. There is an effect that noise can be made ineffective as long as it does not extend over the period of the clock signal, and furthermore, any noise that mixes into the head select signal during a write operation or a read operation can be made ineffective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. FIG. 2 is a timing diagram showing the operation. ■...Shift register, 2...Majority logic circuit, 3
...Latch circuit, Sl...Head select signal, S
2... Clock signal, 33. ...First shift register output signal, S3□...Second shift register output signal, S3z...Third shift register output signal, S4...
・Majority output signal, S5...Write gate signal, S6
...Head selection signal.

Claims (1)

[Scope of Claims] 1. In a head switching processing circuit in a magnetic disk storage device having a plurality of read/write heads, at least one head switching circuit records the state of at least one input head select signal according to an input clock signal. a shift register (1) having more than one stage; at least one majority logic circuit (2) that inputs the state of each stage of the shift register, determines the state by majority logic, and outputs a majority output signal; and a write gate to which the input is applied. 1. A head switching processing circuit comprising at least one latch circuit (3) that latches the state of the majority output signal immediately before a signal or a read gate signal is active and outputs a head selection signal.