JPH02141043A - Signal repeater - Google Patents

Abstract

PURPOSE:To remove distortion and to construct a multistage type transmission circuit by shaping a transmitted waveform by an internal reference clock using an FIFO. CONSTITUTION:For the title repeater, a reference clock generating circuit 1, an edge detecting circuit 2 to detect the edge of a transmitted signal, a clock/ data extracting circuit 3 to extract transmitted clock and data by an edge detected signal, an FIFO 4 to store the data according to the extracted clock, a clear circuit 5 to detect the start of a frame by the edge detected signal and clear the FIFO 4, a sending timing generating circuit 6 to delay sending timing for the depth of this FIFO, and a clock component synthesizing circuit 7 to take out the data from the FIFO 4 by the reference clock of the reference clock generating circuit 1 in the sending timing and synthesize a communication signal including clock components are provided. Thus, when the fixed quantity of data are stored in the FIFO 4, the data are read out, the data components are synthesized according to a transmission clock, synchronization is obtained again, and waveform shaping is executed.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a relay device for a signal including a clock component and a data component transmitted via a communication bus, and more specifically relates to a relay device for a signal including a clock component and a data component transmitted via a communication bus. The present invention relates to a signal relay device that has a function of shaping.

<Conventional technology> When transmitting data via a transmission line made of optical fiber, the electrical signal is first converted into an optical signal, sent out to the optical transmission line, and then the optical signal is converted into an electrical signal at the other station. It is being done.

In such a communication system, the transmitted signal is distorted and jittered at various locations. In particular, a large amount of jitter occurs when converting an optical signal into an electrical signal.

<Problems to be Solved by the Invention> When the jitter becomes large, a problem occurs in that the waveform at the transmitting end is not properly transmitted to the receiving end, and communication is not performed accurately.

The present invention has been made in view of these points, and its purpose is to prevent the occurrence of jitter by shaping the jitter generated in the communication system at each receiving end, and to ensure accurate communication without causing reception errors. The object of the present invention is to realize a relay device that can perform the following operations.

Means for Solving the Problems> The present invention stores data components in a FIFO format according to clock components.
(First InF'1rst 0ut), and a communication signal including a clock component is synthesized from this FIFO at the sending timing, and its detailed configuration is as follows.

That is, the present invention, as shown in FIG. a clock/data extraction circuit 3 that extracts data; a FIFO 4 that stores data extracted according to the extracted clock; a clear circuit 5 that detects the beginning of a frame using an edge detection signal and clears the FIFO 4; A transmission timing generation circuit 6 delays the transmission timing by a depth of
This signal relay device is characterized by being provided with a clock component synthesis circuit 7 that extracts data from the FO 4 and synthesizes a communication signal including a clock component.

For Kusaku The signal relay device of the present invention operates as follows.

When a transmission signal is input, a clock component and a data component are extracted from the edges and stored in the FIFO. F
When a certain amount of data is stored in the IFO, the data is read out according to the transmission timing, data components are synthesized according to the transmission clock, synchronization is reestablished, and the waveform is shaped.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a configuration block diagram showing an example of the present invention.

In this figure, parts corresponding to those in FIG. 1 are given the same reference numerals.

The reference clock generation circuit 1 includes a crystal oscillator that generates a 1.6 MHz clock, and a synchronous 4-bit counter 12 that generates an 11.2 MHz clock.

The edge detection circuit 2 operates according to a 16MHz clock.
It is composed of a serial shift register 21 that detects the edge of the input signal In, and an exclusive OR circuit 22.

The clock/data extraction circuit 3 includes a D flip-flop circuit 31 receiving the edge detection signal BS at the CK line terminal, and a CK line terminal receiving the edge detection signal BS.
Receives a 2MHz clock from the line terminal, and outputs D to the clear terminal ξπ ball.
A synchronous 4-bit counter 32 receiving the terminal output of the flip-flop circuit 31,
OR gate 3 provided on the output side of bit counter 32
Consists of 3. Furthermore, the output of the OR gate 33 and D
Input the Q terminal output of the flip-flop circuit 31 and
An OR gate 34 for clearing a flip-flop circuit 31 and a NAND gate 35 for holding a synchronous 4-bit counter 32 are provided. 36 is an OR gate, and 37 is a D flip-flop circuit for extracting the clock component of the input signal In.

FIFO4 is a 64×1 bit storage circuit section.

The clear circuit 5 includes a retriggerable monostable multivibrator 51 that maintains the "H" state during data reception, and receives the output α of this multivibrator 51 to output F T FO4.
It has a D flip-flop circuit 52, OR gates 53, 54, 55, and a NOT gate 56, in which logic for applying a reset, confirming and canceling the reset is incorporated.

The sending timing generation circuit 6 inputs the D flip-flop circuit 61 that divides the 2 MHz clock, the output α of the multivibrator 51, and the 2 MHz clock, and generates the FI.
Three stages of 8 and y parallel output serial shift registers 62, 6 that generate data sending timing in the FOJ
3.64. Furthermore, there is a D-flip that generates a clock to take out data from FIFO4.
Flop circuit 65. It is equipped with an AND gate 66 and monitors whether data is stored in the FIFOJ (even if data is stored in the FIFOJ, the output ready signal O is not activated while preparing the data).
A monostable multivibrator 67, an OR gate 68, and a NOT gate circuit 69 are provided.

The data output DO of the FIFO 4 is once latched by the flip-flop 1 circuit 8 and then provided to the clock component synthesis circuit 7.

The clock component synthesis circuit 7 includes a NAND gate 71 and JK flip-flop circuits 72 and 73 for synthesizing the clock component to be sent out with data. 74.75
is the output gate.

The operation of the signal relay device of the present invention configured as described above will be explained using the time chart of FIG. 3.

First, the edge detection circuit F#I2 takes in the transmitted and photoelectrically converted input signal In(A), that is, a signal including a clock component and a data component, and detects its rising edge and falling edge from the reference clock generation circuit 1. 16M
Detected by Hz (b). The edge detection signal is (c)E
It becomes like S.

The D flip-flop circuit 31 inputs this edge detection signal ES (c) and clears the counter 32, and the counter 32 starts counting the 16 MHz clock. The count values are Qa (d), Qb (e), Qc(
'), Qd (g).

Here, the counter 32 is cleared by the edge detection signal BS and starts counting, so if no edge is detected, an "H" output is made from the terminal Qd, and this Q(f terminal output (g) is within the input signal In). corresponds to the data component RXD.

Further, the D flip-flop circuit 37 has the Qc ratio output CK terminal of the counter 32 and the data component RXD (=Qd output) applied to the D terminal, and its Q output corresponds to the clock component RXC (Q) of the input signal In. do.

On the other hand, the clear circuit 5 uses the edge detection signal ES to detect the frame start using the multivibrator 51, and uses the signal α(
)), the Q output of the D flip-flop circuit 52, and the OR gate 55 clear the FIF04 (signal β(
)) Then, upon detecting the clearing of FIFO4, the D flip-flop circuit 52 is reset by the OR gate 54.53 and the NOT gate 56.

In this state, the FIFO4 receives the clock component RXC at the SI terminal, and at this timing takes in the data component RXD from the DI@ child.

The transmission timing creation circuit 6 absorbs clock errors in each part, and in order to create the depth for storing data in the FI FO 4, it detects the frame start (signal α) and performs three stages. Shift register 62, 63.64
D flip-flop circuit 65 after 20czs by
is inverted by the signal γ.

This causes the D flip-flop circuit 61 to
Open gate 66 and output IMHz clock TXC (wo)
is the data sending terminal s of FIFO4.

supply to.

In addition, multivibrator 67, knot gate circuit 69
, OR gate 68 outputs "H" when there is data in FIFO 4, and outputs "I-" when there is no data, resets D flip-flop circuit 65, and
Stop the IMHz clock supply to IFO4.

The FIFO4 sends out data from the IMHZ output terminal Do, and this data is once latched into the D flip-flop circuit 8.

The NAND gate 71 receives the data component 'T' x D from the D flip-flop circuit 8 and the IMHz clock (72Q (Y)) obtained by dividing the 2 MHz clock (W) by the JK flip-flop circuit 72. is input, and the output will be like C (evening).

Finally, the output C of the OR gate 71 is applied to the JK flip-flop circuit 73, and the MLA and MLB are output from the Q terminal and the distortion signal corresponding to the input signal In, respectively, via the gate circuits 74 and 75. An output signal is obtained from which the jitter generated by is removed.

<Effects of the Invention> According to the signal relay device of the present invention, the following effects can be obtained.

Since a waveform distorted by jitter or the like is shaped using an internal reference clock using a FIFO, distortion can be removed. This prevents jitter and distortion from occurring in photoelectric conversion, electro-optical conversion, etc., and allows a multi-stage transmission circuit to be configured.

Since the waveform can be shaped with a delay equal to the amount of data stored in the FIFO, it is faster than interpreting and reconstructing the data structure using a processor or the like.

The FIFO clear circuit clears the FIFO if an edge change occurs in the input signal without being detected for a certain period of time.
Since O is cleared, even if a single noise signal or a frequency noise slower than a communication wave is mixed in, a clear output is not performed from the output end, so it also has a filter function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal relay device of the present invention, FIG. 2 is a circuit diagram of an example of a device implementing the present invention, and FIG. 3 is a time chart showing the operation of the device of the present invention. 1...Reference clock generation circuit, 11...Crystal resonator, 12...Synchronous 4-bit counter, 2...
- Edge detection circuit, 21... Serial shift register, 22... Exclusive OR circuit, 3...
Clock/data extraction circuit, 31...D flip-flop circuit, 32...Synchronous 4-bit counter, 33.34.36...OR gate, 35...
NAND gate, 37...D flip frog circuit, 4...FIFO25...clear circuit, 51...
Monostable multivibrator, 52...D flip-flop circuit, 53, 54.55...OR gate, 5
6... Not gate, 6... Sending timing creation circuit, 61.65... D free lag flop circuit, 6
2, 63.64...8-bit parallel output serial shift register, 66...AND gate, 67...
... Monostable multivibrator, 68... OR gate, 69... Not gate circuit, 7... Clock component synthesis circuit, 71... NAND gate, 72.73
...JK flip-flop circuit, 74.75...
Output gate, 8...D flip-flop circuit.

Claims (1)

[Claims] (1) A relay device for a signal including a clock component and a data component, comprising a reference clock generation circuit, an edge detection circuit for detecting an edge of the signal, and a clock and data transmitted by the edge detection signal. a clock/data extraction circuit for extracting; a FIFO for storing the extracted data according to the extracted clock; a clearing circuit for detecting the beginning of a frame using the edge detection signal and clearing the FIFO;
and a clock component synthesis circuit for extracting data from the FIFO using the reference clock of the reference clock generating means and synthesizing a communication signal including a clock component according to the sending timing. A signal relay device characterized by: