JP2003298563A - Node in data transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately reproduce data by eliminating jumped values of time information due to deviation in a clock oscillation frequency of each node in the pseudo synchronization system. <P>SOLUTION: A node among a plurality of nodes on a network acts as a node for transmitting a cycle start packet including a cycle start time and the other nodes receive this packet. Each reception node has a counter for generating cycle time count data comprising higher-order bits equivalent to the amount of information of the cycle start time and lower-order bits equivalent to time information with an accuracy greater than the minimum resolution of the cycle start time, matches the time which the cycle time count data generated from the counter indicates with the time which the cycle start time indicates and uses the higher-order bits in the cycle time count data for the cycle time of the node. By using the cycle time, a reproduction time relation of the received data is accurately reproduced. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system for transmitting data, such as digital audio data, which changes in a time series at a predetermined cycle through a communication network, and in particular, is provided with a dedicated synchronization signal line. Even if it does not exist, the present invention relates to a data transmission system configured such that the receiving side can accurately reproduce the original data in consideration of the time-series change state based on the transmitted data.

[0002]

2. Description of the Related Art A data transmission system via a network is roughly classified into a synchronous system and an asynchronous system. Generally, in the synchronization method, a dedicated synchronization signal line or the like is provided between the transmission side and the reception side, and data is transmitted in synchronization with the synchronization signal line, so that the reception side uses the original data based on the transmitted data. The data can be reproduced accurately. Therefore,
The synchronous data transmission method is a method suitable for transmission of digital audio data or the like which requires accurate reproduction of the temporal position of information on the receiving side. However, it is necessary to provide a separate sync signal line or to have a structure for synchronizing transmission and reception. Further, during communication by the synchronous system, the line is dedicated only for that purpose, and there is a drawback that the versatility of the communication system is lacking. On the other hand, the asynchronous method is suitable for transmitting character data or still image data such as personal computer communication because it is not necessary to secure a dedicated synchronization signal line or the like. However, the packet transmission adopted in the asynchronous method is not suitable for transmission of digital audio data, etc., because the information on the original time position of data is lost.

[0003]

Therefore, recently, each node has a clock oscillation circuit and a clock counter for counting the clock, and the node on the transmission side indicates the time position of the data at the beginning of the packet data. Time data (time stamp) is added and the data is transmitted on the network. The receiving node compares the time data with the count value of the internal clock counter, and if both do not match, the count value is used as the time data. Then, a pseudo synchronization method has been adopted in which the data is sequentially reproduced based on the corrected count value of the clock counter. An example of such a pseudo synchronous communication system (isochronous communication system) is defined as IEEE.
There is E1394. In other words, in this pseudo-synchronization method, the clock oscillation circuit of each node does not always oscillate at exactly the same frequency. A method of correcting the count value of the clock counter according to the time data each time data is received is adopted. To modify this count value,
It follows the rule that the same value as the count value can be repeated, and that it can be skipped in the positive direction, but it cannot be returned in the negative direction.
According to these rules, when the digital audio data is accurately reproduced as the original data on the receiving side in consideration of the time-series change state based on the transmitted data, the count value is in the positive direction. When jumping, there is a problem that the skipped data will not be read, or in the worst case, if the skipped data is specified by the time stamp, the subsequent packet data will not be played correctly. occured. In addition, there is a problem that the circuit for generating the clock becomes complicated because the jump in the plus direction is permitted.
The present invention has been made in view of the above points, and in the pseudo synchronization method, data capable of eliminating the skip of the value of the time information due to the deviation of the oscillation frequency of the clock oscillation circuit provided for each node. It seeks to configure a node so that it can provide a transmission system. Furthermore, it is intended to configure a node so as to provide a data transmission system capable of accurately reproducing the reproduction time relationship of data by using such accurate time information.

[0004]

A node according to the present invention according to claim 1 is composed of a plurality of nodes that operate asynchronously and a communication network that connects the plurality of nodes, and each of the nodes is built in. Each cycle time is counted according to the clock generated by the oscillation circuit, and one of the plurality of nodes transmits a cycle start packet including a cycle start time indicating the cycle time of the start timing of one isochronous cycle to another node. The other node receiving the cycle start packet synchronizes the cycle start time with the cycle time, and uses a synchronization data packet including a time stamp based on the synchronized cycle time among the plurality of nodes. It was configured to allow synchronous communication. The other node in the data transmission system, the receiving unit receiving the cycle start packet or the synchronous data packet via the communication network, and a high-order unit corresponding to the information amount of the cycle start time according to the clock. A counter that sequentially generates cycle time count data consisting of bits and lower bits corresponding to time information with a precision exceeding the minimum resolution of the cycle start time; and when the receiving unit receives the cycle start packet from the certain node. , A counter synchronization unit for matching the time indicated by the cycle time count data generated by the counter with the time indicated by the cycle start time, and the upper bit of the cycle time count data before the node. And cycle-time supply unit to cycle time, when the receiving unit receives the synchronization data packets, based on the timestamp included in the synchronous data packets received cycle time and the supplied from the cycle time supply unit,
And a data synchronization unit that controls the read timing of the received synchronization data packet.
A node according to the present invention according to claim 2 is a claim for a node for receiving a synchronous data packet according to the present invention, comprising a plurality of nodes each operating asynchronously and a communication network connecting the plurality of nodes. , Each of the nodes counts a cycle time in accordance with a clock generated by a built-in oscillation circuit, and a node among the plurality of nodes includes a cycle start time indicating a cycle time of a start timing of one isochronous cycle. A time based on the synchronized cycle time between the plurality of nodes, the start packet being transmitted to another node, the other node receiving the cycle start packet synchronizing the cycle start time with the cycle time. Same as stamp A said other nodes in the configuration data transmission system to allow synchronous communication using a data packet, a reception unit for receiving the cycle start packet via the communication network,
A counter for sequentially generating cycle time count data consisting of an upper bit corresponding to the information amount of the cycle start time and a lower bit corresponding to time information with accuracy exceeding the minimum resolution of the cycle start time according to the clock, and the receiving unit. When the cycle start packet is received from the certain node, a counter synchronization unit that matches the time indicated by the cycle time count data generated by the counter with the time indicated by the cycle start time, and the cycle. A cycle time supply unit that uses the upper bit of the time count data as the cycle time at the node.

One of the plurality of nodes connected to the communication network becomes a node that transmits a cycle start packet including a cycle start time, and the other nodes receive the packet. Each node has an oscillation circuit incorporated therein. In the node defined in claims 1 and 2, according to the clock generated by the built-in oscillation circuit, a high-order bit corresponding to the information amount of the cycle start time and a low-order bit corresponding to time information with an accuracy higher than the minimum resolution of the cycle start time. A counter that sequentially generates cycle time count data consisting of bits, and when a cycle start packet from the certain node is received, the time indicated by the cycle time count data generated by the counter is indicated by the cycle start time. And the upper bit of the cycle time count data is set as the cycle time of the node. In this way, the cycle time of each node is pseudo synchronized with the cycle start time given by the cycle start packet as a reference. At that time, the cycle time count data is composed of upper bits corresponding to the information amount of the cycle start time and lower bits corresponding to time information with an accuracy higher than the minimum resolution of the cycle start time. Since its upper bits are used, even if the oscillation frequencies of the oscillation circuits of the certain node that transmits the cycle start packet and the other node that receives the cycle start packet are slightly different, It is possible to eliminate the jump of the cycle time value that occurs. Furthermore, by controlling the read timing of the received synchronous data packet using such an accurate cycle time, the reproduction time relationship of the received data can be accurately reproduced. Therefore, there is an excellent effect that data such as digital audio data in consideration of a time-series change state can be accurately reproduced on the receiving node side.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 2 is a schematic block diagram showing the overall configuration of an embodiment of a data transmission system according to the present invention. FIG. 3 is a diagram showing a configuration example of data transmitted by this data transmission method. In this specification, a case where data transmission is performed according to the above-mentioned IEEE 1394 communication method will be described as an example. The figure shows a case where the transmission side node 10, the reception side node 20, and the other nodes 30 and 40 are connected via a communication network 90. Hereinafter, for convenience of explanation, only data transmission between the transmission-side node 10 and the reception-side node 20 will be described. However, other than this, many nodes may be connected, and the transmission-side node and the reception-side node may be connected. It goes without saying that only the nodes may be connected, or the data transmission may be performed between the coupled nodes (node 30 and node 40) of the transmission-side node 10 and the reception-side node 20.
In this embodiment, the node 30 sends a synchronization signal (cyc) having a normal cycle period of 125 μsec as shown in FIG.
(le sync) in the case where the cycle start packet signal corresponding to
A case where 0 transmits a data string as shown in FIG. 3 to the communication network 90 and the receiving node 20 receives and reproduces the data string 9 will be described.

In the transmission side node 10, the data generation circuit 11 has a predetermined frequency (for example, a frequency of 24.576 MH) generated by a built-in crystal oscillator (not shown).
z (cycle of about 40 nsec)), and sequentially generates and outputs a plurality of data having a time-series array of a predetermined sampling cycle T.
The sequential sample data of the digital audio signal is output. For example, the data generation circuit 11 may include an audio reproducing device such as a CD (Compact Disc) player, or may include a musical tone synthesizing device that synthesizes musical tone sample data in real time. . The sampling period T of the data output from the data generation circuit 11 may be appropriately changed according to the data source.

The data output from the data generation circuit 11 is temporarily stored in the transmission data buffer 12 in the order of its time series. The transmission data buffer 12 is a buffer register that operates asynchronously for input / output. Counter circuit 13
Is for creating time stamp data, that is, time data, and is like a running counter of a 32-bit configuration that counts a clock of a predetermined frequency generated by a crystal oscillator (not shown). The network interface 14 has a predetermined transmission interrupt cycle (a synchronization signal (cycle) output from the node 30 described above.
sync)) based on the data temporarily stored in the transmission data buffer 12 in synchronization with one isochronous cycle (isochronous cycle) as shown in FIG.
The data sequence 9 (hereinafter referred to as a “cycle packet sequence”) corresponding to (le) is configured and is transmitted to the communication network 90.

As shown in FIG. 3, the cycle packet sequence 9 is composed of a cycle start packet 91, a synchronous data packet group 92 and an asynchronous data packet group 93. The cycle start packet 91 is composed of 32 bits, the upper 20 bits of which are data indicating the cycle timing of the cycle packet string 9, and the lower 12 bits.
The bit is data indicating the cycle start data X indicating how much time delay the cycle packet string 9 has been transmitted from the synchronization signal (cycle sync) on the communication network 90. Synchronous data packet group 9
Reference numeral 2 is composed of a plurality of P pieces of packet data which are targets of the pseudo synchronization signal processing. In the figure, as an example, channel J
Five synchronous data packets from to N are shown. The number P of the synchronization data packets can be set arbitrarily. Further, each synchronous data packet has a plurality of groups each including a predetermined number Q of data and any one (in this embodiment, the first data) time stamp data indicating the time position of the data. In this embodiment, one group is composed of four data and one time stamp. That is, in the figure, one piece of time stamp data T1 and T2 is provided for four pieces of data D1 to D4 and D5 to D8, respectively.
The time stamp data T1 indicates the time position of the first data D1, and the time stamp data T2 indicates the time position of the data D5. Therefore, each synchronous data packet is composed of an integral multiple of (Q + 1) data groups.
In addition, because of the communication of digital audio data,
The data may be transmitted even if the number of data is less than Q, but detailed description thereof will be omitted. The asynchronous data packet group 93 is composed of a plurality of R pieces of packet data to be subjected to asynchronous signal processing. In the figure, two packet data of packet B and packet C are shown as an example.
The asynchronous data packet does not have to exist.

In the receiving side node 20, the network interface 24 receives the cycle packet sequence 9 transmitted via the communication network 90, and temporarily stores it in the reception data buffer 22 in a time series in the order of reception. To do. The reception data buffer 22 is a buffer register that performs an input / output operation asynchronously. The clock generation circuit 23, based on the cycle start data X in the cycle start packet of the received cycle packet sequence 9, has the same original sampling period T as the data supplied from the data generation circuit 11 of the transmission side node 10.
Is to be reproduced. The data generation circuit 21 sequentially reads out and reproduces the data temporarily stored in the reception data buffer 22 in accordance with the reproduced sampling period T given from the clock generation circuit 23. The read data is used as appropriate. In what form the reproduced data is used is arbitrary. For example, it may be D / A converted as it is and then sounded from a speaker or the like, or it may be processed by an effect or the like and then sounded from the speaker or the like or the processed data may be sent to the outside. Good.

The detailed configuration of the receiving side node 20 will be described with reference to FIG. In FIG. 1, the cycle time extraction circuit 5
1 extracts a cycle start packet 91 from the transmitted cycle packet sequence 9 and receives the cycle start packet data from the reception cycle time register 5
2 and outputs the remaining synchronous data packet group 92 and asynchronous data packet group 93 to the data separation circuit 55. The reception cycle time register 52 is a 34-bit configuration register in which the lower 2 bits store a constant of "00" in advance, and the upper 32 bits thereof have the 32-bit configuration extracted by the cycle time extraction circuit 51. The cycle start packet data is temporarily stored and the 34-bit data is directly transferred to the built-in cycle time counter 53. The built-in cycle time counter 53 is a 34-bit counter that counts a clock having an oscillation frequency of 98.304 MHz (a period of about 10 nsec) output from a crystal oscillator built in the reception node 20, and the reception cycle time register 5
The contents are sequentially rewritten by the data transferred from 2. The value of the built-in cycle time counter 53 may be rewritten only when the reception cycle time register 52 and the built-in cycle time counter 53 have different 34-bit count values. The cycle time register 54 always stores the count value of the upper 32 bits of the built-in cycle time counter 53. Therefore, the top 3 built-in cycle time counters 53
When the 2-bit count value changes or is rewritten, the value of the cycle time register 54 is also changed accordingly. These reception cycle time register 5
2. The relationship between the built-in cycle time counter 53 and the cycle time register 54 is illustrated in FIG. As is apparent from the figure, the 34-bit data of the reception cycle time register 52 is directly output to the built-in cycle time counter 53, and the upper 32-bit data of the built-in cycle time counter 53 is directly output to the cycle time register 54. Become.

The data separation circuit 55 extracts time stamp data from the packet data forming the synchronous data packet, outputs the time stamp data to the time stamp register 56, and outputs the remaining data to the reception data buffer 22. To do. For example, as shown in FIG. 3, when one time stamp data T1 is provided for four data D1 to D4, the first time stamp data T1 is output to the time stamp register 56 and the remaining time stamp data T1 is output. Data D1 to D4 of the received data buffer 22
Is output to. The data separation circuit 55 does nothing for the packet data of the asynchronous data packet group,
The data is directly transferred to the reception data buffer 22.
The time stamp register 56 temporarily stores the time stamp data T1 separated by the data separation circuit 55. The comparison circuit 57 includes a cycle time register 54.
And a value stored in the time stamp register 56 are compared with each other, and when they match each other, a coincidence signal (clock signal) is output to the phase difference detection circuit 61 of the clock generation circuit 23 through the gate circuit 58.

When the output of the flip-flop circuit 5A is at the high level "1", the gate circuit 58 is in the through state in which the coincidence signal output from the comparison circuit 57 is directly output to the phase difference detection circuit 61, and the gate circuit 58 of the flip-flop circuit 5A is in the through state. When the output is at the low level "0", the output of the comparison circuit 57 is shut off to enter the gate state. The detection circuit 59 detects whether or not the value of the lower 2 bits of the built-in cycle time counter 53 becomes "00", and when it becomes "00", outputs a set signal to the set terminal S of the flip-flop circuit 5A. , The output Q of the flip-flop circuit 5A is set to the high level "1". The flip-flop circuit 5A inputs the detection signal from the detection circuit 59 to the set terminal S and the coincidence signal of the comparison circuit 57 to the reset terminal R via the gate circuit 58, and outputs its output Q to the gate control terminal of the gate circuit 58. Output to.

The clock generation circuit 23 is a PLL circuit composed of a phase difference detection circuit 61, a VCO 62 and a 1 / Q frequency dividing circuit 63, and a coincidence signal from a comparison circuit 57 input via a gate circuit 58. Work based on.
Here, Q is the number of pieces of data forming one group of synchronous data packets as described above. Therefore, the number of data Q
When the number is four, a quarter frequency divider is used for the frequency dividing circuit, and when there are eight, the eighth frequency divider is used for the frequency dividing circuit. The data generation circuit 21 includes a read control circuit 71 and a D / A conversion circuit 72. The read control circuit 71 is
The data stored in the reception data buffer 22 is sequentially read in synchronization with the clock from the VCO 62 of the clock generation circuit 23, and is output to the D / A conversion circuit 72. The D / A conversion circuit 65 converts the data read by the read control circuit 71 into an analog signal.

The operation of the receiving side node 20 of FIG. 1 will be described below with reference to FIG. In FIG. 5, the vertical axis indicates the passage of time,
Receiving cycle time register 5 after the passage of time
2 shows how the respective values of the built-in cycle time counter 53 and the cycle time register 54 change. FIG. 5A shows a case where the crystal oscillator built in the transmission side node 10 oscillates at a frequency slightly higher than that of the crystal oscillator built in the reception side node 20, and FIG.
On the contrary, the case where the crystal oscillator built in the transmission side node 10 oscillates at a slightly smaller frequency than the crystal oscillator built in the reception side node 20 is shown.

First, the case of FIG. 5A will be described. When the crystal oscillator built in the transmission side node 10 oscillates at a frequency slightly higher than that of the crystal oscillator built in the reception side node 20, the count operation of the built-in cycle time counter 53 is gradually delayed, and the cycle start when the count value is received. It becomes smaller than the value of the lower 12 bits of cycle start data X included in the packet. Such a case is called a delayed state. That is, "326"
The cycle start packet including the cycle start data X must be extracted by the cycle time extraction circuit 51 at time t4 when the value of the built-in cycle time counter 53 is originally “326.00”, but in the state where a delay occurs, The value of the cycle time counter 53 is "3.
25.75 ”at time t3. Therefore, the value of the built-in cycle time counter 53 is rewritten to "326.00" at the time t3 when the cycle start data X is extracted, and thereafter, the count-up is sequentially performed according to the clock of the built-in crystal oscillator. According to the data rewriting process of the built-in cycle time counter 53, the value of the cycle time register 54 is changed by advancing by one clock of the built-in crystal oscillator. Then, the output timing of the coincidence signal output from the comparison circuit 57 also becomes slightly longer, but this is absorbed by the operation of the clock generation circuit 23, that is, the PLL circuit. Note that the numbers after the decimal point are represented by 2 bits, so ".
00 ”,“. 25 ”,“. 50 ”and“. 75 ”is displayed.

Next, the case of FIG. 5B will be described. When the crystal oscillator built in the transmission side node 10 oscillates at a frequency slightly smaller than that of the crystal oscillator built in the reception side node 20, the counting operation of the built-in cycle time counter 53 gradually progresses, and the count value is received in the received cycle. It is larger than the value of the cycle start data X of the lower 12 bits included in the start packet. Such a case is called a state in which the advance has occurred. That is, "32
The cycle start packet including the cycle start data X of "5" must be extracted by the cycle time extraction circuit 51 at the time t1 when the value of the built-in cycle time counter 53 is originally "325.00", but the advance has occurred. Then, the value of the cycle time counter 53 is extracted at the time point t2 of “325.25”. Therefore, at the time t2 when the cycle start data X is extracted, the value of the built-in cycle time counter 53 is "325.00".
Is rewritten to, and thereafter, the count-up is sequentially performed according to the clock of the built-in crystal oscillator. When this advance has occurred, the built-in cycle time counter 53
Although the value of the cycle time register 54 does not change according to the data rewriting process, the value of the lower 2 bits of the built-in cycle time counter 53 is set to "0" by the detection circuit 59.
It is detected that it has become "0". That is, the detection circuit 5
9 detects "00" during a short time between time t2 and time t1, outputs a set signal to the set terminal S of the flip-flop circuit 5A, and sets the output Q of the flip-flop circuit 5A to the high level "1". As a result, the comparison circuit 57 also continuously outputs the coincidence signal to the clock generation circuit 23 for a short period of time, but in this case also, the operation of this clock generation circuit 23, that is, the PLL circuit is absorbed. It has no effect. According to the data rewriting process of the built-in cycle time counter 53, the value of the cycle time register 54 changes with a delay of one clock of the built-in crystal oscillator. Then, although the output timing of the coincidence signal output from the comparison circuit 57 is slightly deviated, it is absorbed by the operation of the clock generation circuit 23, that is, the PLL circuit. According to the above-described embodiment, since the skip of the built-in cycle time counter 53 can be eliminated, the comparison circuit of the time stamp register and the cycle time register 54 can be easily configured and the jitter amount of the digital audio data can be reduced. You can Also,
Since the built-in cycle time counter 53 is corrected by the decimal part, the jitter of the digital audio data is dispersed on the time axis, so that the clock generation circuit 23, that is, the PLL circuit can easily perform filtering.

In the above embodiment, the case where the number of data forming one group of the synchronous data packet is 4 has been described, but the present invention is not limited to this, and the value may be 3 or more. Furthermore, it is preferable to set Q to a power of 2 because the division operation can be simplified. Further, it is also possible to perform a process of adding unique time data to the data to which the time stamp data is not added, and perform reproduction and reading by referring to the unique time data of each data. In the above embodiment, the case where the lower 2 bits are added to the built-in cycle time counter and the count clock is quadrupled has been described, but another register or the like may be provided. Further, in the above-described embodiment, the reception side node has a frequency four times as high as that of the transmission side node (98.304).
Although the case where the transmitting side node operates at the same frequency as the receiving side node and transmits the data on the communication network, the normal frequency (2
It may be transmitted at 4.576 kHz). In the above embodiment, the case where the value of the built-in cycle time counter 53 is rewritten with the value of the reception cycle time register 52 when the lower 12 bits of cycle start data X included in the cycle start packet is received has been described. Time stamp data may be extracted from the packet data forming the synchronous data packet, and rewriting processing may be performed for each of the extracted time stamp data.

[0019]

According to the present invention, in the pseudo synchronous system (isochronous communication system), the cycle time count data generated at each receiving node is the upper bits corresponding to the information amount of the cycle start time included in the cycle start packet. And a lower bit corresponding to time information with an accuracy higher than the minimum resolution of the cycle start time, and the upper bit is used as the actual cycle time. Even if the oscillation frequencies of the respective oscillation circuits of the other nodes (reception nodes) that receive this change somewhat, it is possible to eliminate the skip of the cycle time values caused by the deviation of the oscillation frequency. Furthermore, by controlling the read timing of the received synchronous data packet using such an accurate cycle time, the reproduction time relationship of the received data can be accurately reproduced. Therefore, there is an excellent effect that the data considering the time-series change state such as digital audio data can be accurately reproduced on the receiving node side.

[Brief description of drawings]

FIG. 1 is a detailed configuration block diagram showing an embodiment of a receiving node in a data transmission system according to the present invention.

FIG. 2 is a schematic block diagram showing the overall configuration of an embodiment of a data transmission system including the receiving node shown in FIG.

FIG. 3 is a diagram showing a configuration example of data transmitted by the data transmission system according to the present invention.

FIG. 4 is a diagram showing a relationship among a reception cycle time register, a built-in cycle time counter, and a cycle time register shown in FIG.

FIG. 5 is a diagram showing how the values of a reception cycle time register, a built-in cycle time counter, and a cycle time register change over time.

[Explanation of symbols]

10 transmission side node, 11 ... data generation circuit, 12 ... transmission data buffer, 13 ... counter circuit, 14 ... network interface, 20 ... reception side node, 21 ...
Data generation circuit, 22 ... Reception data buffer, 23 ... Black generation circuit, 24 ... Network interface, 30, 40 ... Other node, 90 ... Communication network, 51 ... Cycle time extraction circuit, 52 ... Reception cycle time register, 53 ... Built-in cycle time counter, 54 ... Cycle time register, 55 ... Data separation circuit, 56 ... Time stamp register, 57 ... Comparison circuit, 58 ... Gate circuit, 59 ... Detection circuit, 5A ... Flip-flop circuit, 61 ... Phase difference detection circuit , 62 ... VC
O, 63 ... Frequency divider circuit, 71 ... Read control circuit, 72 ...
D / A conversion circuit.

Claims (2)

[Claims] 1. A plurality of nodes each operating asynchronously and a communication network connecting the plurality of nodes, each of which counts a cycle time according to a clock generated by an internal oscillation circuit,
One of the plurality of nodes transmits a cycle start packet including a cycle start time indicating the cycle time of the start timing of one isochronous cycle to another node, and the other node receiving the cycle start packet A data transmission system configured to synchronize the cycle start time with the cycle time, and to perform synchronous communication between the plurality of nodes using a synchronous data packet including a time stamp based on the synchronized cycle time. A receiving unit which is the other node and receives the cycle start packet or the synchronous data packet via the communication network; and an upper bit corresponding to the information amount of the cycle start time and the cycle scan packet according to the clock. A counter that sequentially generates cycle time count data consisting of lower bits corresponding to time information with a precision exceeding the minimum resolution of the start time, and a counter that is generated when the receiving unit receives the cycle start packet from the certain node. A counter synchronization unit that matches the time indicated by the cycle time count data with the time indicated by the cycle start time, and a cycle time in which the upper bit of the cycle time count data is the cycle time at the node. When the synchronization data packet is received by the supply unit and the reception unit, the received synchronization data packet is received based on the cycle time supplied from the cycle time supply unit and the time stamp included in the received synchronization data packet. Read out And a data synchronization unit for controlling timing. 2. A plurality of nodes each operating asynchronously and a communication network connecting the plurality of nodes, each node counting cycle time in accordance with a clock generated by an oscillation circuit incorporated therein,
One of the plurality of nodes transmits a cycle start packet including a cycle start time indicating the cycle time of the start timing of one isochronous cycle to another node, and the other node receiving the cycle start packet A data transmission system configured to synchronize the cycle start time with the cycle time, and to perform synchronous communication between the plurality of nodes using a synchronous data packet including a time stamp based on the synchronized cycle time. A receiving unit that is the other node and receives the cycle start packet via the communication network, and a high-order bit corresponding to the information amount of the cycle start time and a minimum resolution of the cycle start time according to the clock. Surpass A counter that sequentially generates cycle time count data consisting of lower bits corresponding to precision time information, and the cycle time count data that the counter generates when the receiving unit receives the cycle start packet from the certain node. A counter synchronization unit that matches the time indicated by 1 to the time indicated by the cycle start time, and a cycle time supply unit that sets the upper bit of the cycle time count data as the cycle time at the node. A node characterized by that.