JPH05268199A - Data replacement device - Google Patents

Abstract

PURPOSE:To provide a control circuit for an FIFO memory not requiring a special monitor circuit for a write clock in the data replacement circuit employing the FIFO memory. CONSTITUTION:A write clock 12 and a replacement clock 14 are clocks whose frequency is coincident but whose phases are different. When data written in an FIFO memory 1 reaches an output stage, a read enable signal 16 is outputted from the FIFO memory, an N-stage shift register 2 shifts the replacement clock by N-bits, and the supply and its stop of the replacement clock are controlled by a gate 3 based on the output of the shift register 2. Thus, a FIFO read clock 15 is fed to the FIFO memory in N-bits after the read of the FIFO memory is enable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for transferring digital signals on different clock phases having the same frequency.

[0002]

2. Description of the Related Art A conventional circuit will be described with reference to FIG. The write clock 12 and the transfer clock 14 are clocks having the same frequency but different phases. The digital input signal 11 is written in the FIFO (first in first out) memory 1 by the write clock 12.
When reading the stored data from the FIFO memory 1, the data is stored in the FIFO memory 1 to some extent in order to surely hold it in the flip-flop 4 at the next stage and to prevent a read error due to the jitter included in the digital input signal. I need to leave.

In the figure, the N-bit counter 22 is used to count the number of the write clock 12 by N bits, and the transfer clock 14 is stopped by the gate 3 during that period, thereby controlling the FIFO read clock 15 to perform FIFO.
N-bit data is stored in the memory 1. The N-bit counter 22 controls the gate 3 so that the transfer-side clock 14 is always supplied to the FIFO memory 1 after the N-bit counting.

[0004]

In the conventional control circuit described above, the FIFO write clock is constantly monitored and the F
If the IFO write clock is cut off, the N-bit counter 22 must be reset.

Therefore, the technical problem of the present invention is to solve the general FI problem.
In the case of FO, the read permission signal that is always provided is used to provide a data transfer device that does not require a special monitoring circuit.

[0006]

According to the present invention, there is provided a first-in-first-out memory for writing predetermined data and outputting a read enable signal, and data transfer for transferring digital signals to different clock phases of the same frequency. In the replacement device, an N-stage shift register that shifts the read permission signal by N bits and outputs the shifted read permission signal, and for reading the data from the memory based on the shifted read permission signal There is provided a data transfer device having a gate circuit for controlling supply and stop of the read clock of.

Further, according to the present invention, in the above-mentioned data transfer device, there is provided holding means for holding the data read from the memory based on a predetermined transfer side clock and outputting it as a digital output signal. A data transfer device characterized by the above is obtained.

Further, according to the present invention, in the above-described data transfer device, the data transfer device is obtained in which the holding means is a flip-flop.

That is, the data transfer circuit of the present invention is F
A shift register that shifts a read enable signal (data output ready) by N stages using an IFO memory, a gate circuit that supplies and stops a read clock according to the shifted read enable signal, and data loaded from the FIFO memory It is composed of a flip-flop for holding with a substitute clock.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Also referring to FIG. 2 showing the signal waveforms of the respective parts, the digital input 11 is made into the FIFO by the write clock 12.
Written to memory 1. When the data written in the FIFO memory 1 reaches the output stage, the read enable signal 1
6 is output from the FIFO memory 1. The N-stage shift register 2 transfers the read enable signal 16 to the replacement clock 1
4 shifts by N bits, and the output thereof controls the supply and stop of the replacement clock 14 by the gate 3. FIFO
The read clock 15 is supplied to the FIFO memory 1 N bits after it becomes readable from the FIFO memory. The data read from the FIFO memory 1 is held in the flip-flop 4 by the transfer side clock 14 and becomes the digital output signal 13.

[0012]

As described above, the present invention is a FIFO.
In a circuit that uses a memory to transfer digital signals to different clock phases of the same frequency, a shift register that shifts the read enable signal (data output ready) by N stages, and supply and stop of the read clock by the shifted read enable signal By having the gate circuit for performing the above and the flip-flop for holding the data read from the FIFO memory, there is an effect that a special circuit for monitoring the write clock to the FIFO memory is unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of signals at various parts of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 FIFO memory 2 N-bit counter 3 Gate 4 Flip-flop 11 Digital input 12 Write clock 13 Digital output signal 14 Transfer side clock 15 FIFO read clock 16 Read enable signal 22 N-bit shift register

Claims (3)

[Claims] 1. A data transfer device having a first-in first-out memory for writing predetermined data and outputting a read enable signal, wherein the digital enable signal is transferred to different clock phases of the same frequency, wherein the read enable signal is An N-stage shift register that shifts N bits and outputs a shifted read enable signal, and supply and stop of a read clock for reading the data from the memory based on the shifted read enable signal. A data transfer device having a control gate circuit. 2. The data transfer apparatus according to claim 1, further comprising holding means for holding the data read from the memory based on a predetermined clock on the transfer side and outputting the data as a digital output signal. A data transfer device. 3. The data transfer apparatus according to claim 2, wherein the holding means is a flip-flop.