JPH05143493A - Serial data transfer device - Google Patents

Abstract

PURPOSE:To reduce the overhead of a central processing unit even at the time of complicated communication by easily realizing the chip select required for serial data transfer. CONSTITUTION:A chip select signal CS (inverted) is driven, and a counter 22 starts to count the delay signal obtained based on a clock signal 9 at the time of the start of serial data transfer, and a stop signal 10 is outputted to terminate the transfer when the counted value reaches the set value of a register 23. Since the chip select signal CS (inverted) is driven from the start of transfer to the generation of the stop signal 10 in this manner, a device to which data should be transferred can keep the write operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer device used for a microcomputer or the like and for transferring serial data to another device.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing the configuration of a conventional serial data transfer device. In FIG. 3, reference numeral 1 denotes a clock generating circuit for inputting a basic clock signal 5 and generating a clock signal (clock signal for serial transfer) 9. Reference numeral 2 denotes a clock generating circuit 1 when the clock signal 9 is counted a predetermined number of times. The counter 3 outputs a stop signal 10 for storing the serial data input from the data bus 7 or the input line 11 in synchronization with the clock signal 9 or stores the stored serial data in the clock signal 9
, A serial register for outputting to the output line 12 in synchronization with a serial clock line 13 for outputting a serial clock signal for external output, and a data register 4 for storing the data of the chip select signal to be output from the chip select line 14. Is. Serial register 3 has write signal 6
Thus, the data of the data bus 7 and the input data from the input line 11 are written and stored. The data register 4 writes and stores the data of the data bus 7 by the write signal 8.

FIG. 4 is a timing chart for explaining the operation of the circuit of FIG. In FIG. 4, 8 is a write signal to the data register 4, 6 is a serial register 3
Write signal to SCLK is serial clock line 13
External output clock signal (same as clock signal 9), SIN is serial data input to input line 11 (not shown in this case), SOUT is serial data output from output line 12, CS ( Inversion) is a chip select signal output from the chip select line 14.

Next, the operation of this conventional example will be described with reference to FIGS. In the case of serial transfer, in addition to the serial transfer block centered on the serial register 3, it is necessary to select the device to be transferred by the chip select function. In FIG. 3, this is indicated by the data register 4 and the chip select line 14. The general-purpose port is used to realize the chip select function. First, "0" is written in the data register 4, the chip select signal CS (inversion) is set to "0" as shown in FIG. 4, and then the transfer data is written in the serial register 3. Next, write signal 6
, The serial transfer block starts operation,
The clock signal 9 and SCLK are output from the clock generation circuit 1, and the serial data in the serial register 3 is output from the output line 12 in synchronization with them. The counter 2 is, for example, a 3-bit counter, counts the clock signal 9 (clock signal SCLK) eight times, and then outputs the stop signal 10 to the clock generation circuit 1 to stop the clock signal 9 and the clock signal SCLK. Then, "1" is written in the data register 4 to set the chip select signal CS (inversion) to "1". Here, the chip select signal CS
Only when (inversion) is "0", the device to be transferred is selected, and the chip select signal CS (inversion) is "0".
The device receives the serial data at the time.

[0005]

In the conventional serial data transfer device, it is necessary to control a general-purpose port such as the data register 4 in order to realize a chip select function when selecting a device to be transferred. Some devices must continue to assert chip select (drive chip select signal) for a certain period even after the end of data transfer, and a central processing unit for realizing the chip select function associated with them other than serial data transfer. However, there is a problem that the control of the above becomes complicated.

The present invention has been made in order to solve the above problems, and performs a chip select in conjunction with the control of serial data transfer to transfer a plurality of bytes or hold a chip select after the transfer is completed. It is an object of the present invention to obtain a serial data transfer device capable of realizing the above.

[0007]

According to another aspect of the present invention, there is provided a serial data transfer device which stores a value set in association with a driving period of a chip select signal for making a device operable. 23, the chip select signal is driven, and when the transfer of the serial data from the serial register 3 is started, the delay signal obtained based on the clock signal is started to be counted, and the count value reaches the set value of the register 23. At this time, a counter 22 that stops the clock signal to end the transfer of the serial data from the serial register 3 and outputs a stop signal to stop the chip select signal is provided.

According to a second aspect of the present invention, there is provided a serial data transfer device, a register 23 for storing a value set in association with a drive period of a chip select signal for making a device operable, and the chip select. When the signal is driven and the transfer of the serial data from the serial register 3 is started, the delay signal obtained based on the clock signal is started to be counted, and when the count value reaches the set value of the register 23, the serial register 3 A counter 22 that outputs the stop signal for stopping the clock signal and the chip select signal in order to terminate the transfer of the serial data from the device, and the stop signal from the counter 22 for the write operation of the device. Delay the set time in relation to the time of maintenance, etc., and It is obtained by a delay circuit 24 for delaying the time of stopping of the bets signals.

[0009]

In the invention of claim 1, when the chip select signal is driven and the transfer of the serial data from the serial register 3 is started, the counter 22 starts counting the delay signal obtained based on the clock signal, and the count value is When the set value of the register 23 is reached, the stop signal for stopping the clock signal to stop the transfer and the stop signal for stopping the chip select signal are output. As described above, since the chip select signal is driven from the start of transfer to the generation of the stop signal, the device to be transferred can maintain the write operation and write the serial data from the serial register 3.

In the second aspect of the invention, when the chip select signal is driven and the serial data transfer from the serial register 3 is started, the counter 22 starts counting the delay signal obtained based on the clock signal, and the count value is When the set value of the register 23 is reached, the stop signal for stopping the clock signal to stop the transfer and the stop signal for stopping the chip select signal are output. This stop signal is delayed by the delay circuit 24 for a set time to delay the time for stopping the chip select signal. As a result, it is possible to further maintain the appropriate write operation of the transfer target device after the transfer is completed. That is, the delay holding of the chip select after the transfer is surely realized.

[0011]

1 is a block diagram showing the configuration of a serial data transfer apparatus according to an embodiment of the present invention. In FIG. 1, components corresponding to those shown in FIG. 3 are designated by the same reference numerals, and their description will be omitted. In FIG. 1, reference numeral 2 denotes a counter which inputs the clock signal 9 from the clock generation circuit 1 to count, and outputs a count result signal 30 when the count value reaches a predetermined value, which is the same as the counter 2 in FIG. Is the count result signal 3 which is this output signal
0 is input to the delay circuit 21 in the next stage and delayed for a predetermined time. Reference numeral 22 denotes a delay signal (delay count result signal 31 from the delay circuit 21) obtained based on the clock signal 9 at the start of transfer of the serial data from the serial register 3.
When the count value reaches the set value of the register 23, the clock signal 9 and the clock signal SCL from the clock generation circuit 1 are used to terminate the transfer.
The counter outputs a stop signal 10 for stopping K and stopping the chip select signal CS (inversion). The register 23 stores a value set in association with a driving period of the chip select signal CS (inversion) for setting a device (not shown) to be transferred to a writable state (operable state). ing. The set value of the register 23 becomes an initial value of the count performed by the counter 22, and the set value is written by a write signal 40 by an instruction from the data bus 7. Reference numeral 24 is a delay circuit that delays the stop signal 10 from the counter 22 by a time set in relation to the time for maintaining the write operation of the device, and delays the time for stopping the chip select signal CS (inversion). 34 is a delay circuit 2 for the stop signal 10
It is a delay stop signal delayed by 4. Reference numeral 50 is a switch means for selecting and outputting the delay stop signal 34 or the stop signal 10. Reference numeral 35 is a chip select stop signal which is a selection result of the switch means 50. Reference numerals 51 and 52 are NOR circuits that form a flip-flop 53. When a write signal 6 is input, a chip select signal CS (inverted) of "0" is output from the chip select line 14 and a chip select stop signal 35 is input. From chip select line 14 to "1"
The chip select signal CS (inversion) is output. That is,
The flip-flop 53 drives the chip select signal CS (inversion) when the write signal 6 is input, and stops the chip select signal CS (inversion) when the stop signal 10 or the delay stop signal 34 is input.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. In FIG. 2, 6 is a write signal to the serial register 3, SCLK is a clock signal for external output (same as the clock signal 9), 30 is a count result signal of the counter 2, 31 is a delay count result signal from the delay circuit 21. , 22a is the value in the counter 22,
Reference numeral 40 is a write signal to the register 23, 10 is a stop signal from the counter 22, 34 is a delay stop signal from the delay circuit 24, and CS (inversion) is a chip select signal from the flip-flop 53.

The operation of this embodiment will be described below with reference to FIGS. An initial value is written to the register 23 by the write signal 40 via the data bus 7. Here, the value '3' is written. Next, by writing data to the serial register 3 by the write signal 6 from the data bus 7 or the input line 11, the serial transfer block centered on the serial register 3 starts operation. At this time, the NOR of the flip-flop 53 is started. Since the write signal 6 is also input to the circuit 51, the chip select signal CS (inversion) becomes “0”. Counter 2 is, for example, 3
Assuming that the counter is a bit counter, as shown in FIG. 2, the counter 2 outputs the count result signal 30 every time the clock signal 9 (SCLK) is counted eight times, and counts the delay count result signal 31 obtained through the delay circuit 21. Two
2 clocks.

Here, the counter 22 is, for example, a down counter, and when the value of the counter 22 becomes "0", the clock stop signal 10 is generated and input to the clock generation circuit 1.
The clock signal 9 and the clock signal SCLK are stopped, and the delay stop signal 34 of the stop signal 10 is generated via the delay circuit 24. The stop signal 10 or the delayed stop signal 34 is set by the switch means 50 that can be set by software.
By inputting any one of them to the chip select stop signal 35 and inputting it to the NOR circuit 52 of the flip-flop 53, the chip select signal CS (inversion) becomes "1" again. As a result, the device to be transferred becomes the unwritable state, and the operation for data transfer from this apparatus is finished.

According to the above embodiment, the chip select signal C is started from the start of data transfer (when the write signal 6 is generated) to the time when the stop signal 10 or the delay stop signal 34 is generated.
Since S (inversion) becomes “0”, it is possible to transfer a plurality of bytes of data, and the function of holding the chip select of the device after the transfer is completed is suitable for the performance of the device.

[0016]

As described above, according to the present invention, the register for storing the value set in relation to the driving period of the chip select signal and the chip select signal are driven, and the serial data transfer is started. Since it is configured with a counter that outputs a stop signal for counting and stopping the clock signal and the chip select signal when the value of the register is reached, the chip select control is linked with the serial data transfer control at the same time. A byte select and a chip select holding function after the end of the transfer are realized, which makes it possible to automatically and easily control the chip select according to the performance of the device to be transferred, and thus the complicated serial data transfer. Also in this case, the effect that the load (overhead) of the central processing unit can be reduced is obtained. Further, according to the present invention, a delay circuit for delaying the stop signal from the counter by a time set in relation to the time for maintaining the write operation of the device and delaying the time for stopping the chip select signal is further provided. Therefore, the delay holding of the chip select after the end of the transfer works more effectively for the device, and the above effect can be efficiently achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a serial data transfer device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of this embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional serial data transfer device.

FIG. 4 is a timing chart for explaining the operation of this conventional example.

[Explanation of symbols]

 1 Clock Generation Circuit 3 Serial Register 22 Counter 23 Register 24 Delay Circuit

Claims (2)

[Claims] 1. A clock generation circuit for generating a clock signal, and a serial register for outputting stored serial data in synchronization with the clock signal. Serial data from the serial register is transferred to a device to be transferred. In a serial data transfer device for transferring, a register for storing a value set in relation to a driving period of a chip select signal for making the device operable, and a serial register driven by the chip select signal. When the serial data transfer is started, the delay signal obtained based on the clock signal is started to be counted, and when the count value reaches the set value of the register, the transfer of the serial data from the serial register is ended. In order to stop the clock signal and A serial data transfer device comprising: a counter that outputs a stop signal for stopping the recto signal. 2. A clock generation circuit for generating a clock signal, and a serial register for outputting stored serial data in synchronization with the clock signal, wherein serial data from the serial register is transferred to a device to be transferred. In a serial data transfer device for transferring, a register for storing a value set in relation to a driving period of a chip select signal for making the device operable, and a serial register driven by the chip select signal. When the serial data transfer is started, the delay signal obtained based on the clock signal is started to be counted, and when the count value reaches the set value of the register, the transfer of the serial data from the serial register is ended. In order to stop the clock signal and A counter that outputs a stop signal to stop the Rect signal and a stop signal from this counter that is delayed by the time set in relation to the time for maintaining the write operation of the device to stop the chip select signal. A serial data transfer device, comprising: a delay circuit for delaying the time for which the serial data transfer is performed.