KR20200092146A - Host and slave apparatus having cascade connection structure - Google Patents

Abstract

According to the present technology, provided is a device, which comprises: a plurality of slaves cascaded to each other while each including ports for chip select signal input and output, serial clock input and output, and serial data input and output, and a register; and a host forming and outputting a chip select signal, a serial clock, and serial data. The serial data includes an assign byte controlling the slave, an address byte of the register included in the slave, and a data byte to be stored in the register.

Description

Host and slave devices with cascaded connection structure{HOST AND SLAVE APPARATUS HAVING CASCADE CONNECTION STRUCTURE}

The present technology relates to a cascaded connection structure host and slave devices.

There can be multiple methods to control by connecting multiple slave modules with one host. For example, in order to control a plurality of slave devices to be controlled by the host, a dedicated input/output port for each slave device may be provided to perform control signal, data, and clock communication between the host and slave devices.

When a plurality of slave devices are to be controlled by a single host, I/O ports are required as many as the number of slave devices to be controlled, and a host having a large-scale computing capability is required to independently control communication with each slave device.

According to the prior art, input/output ports are required as many as the number of slave devices to be controlled by the host, and it is uneconomical to consume a lot of cost to form them. In addition, an expensive high-performance computing device is required to control communication made independently at each port.

One of the technical problems to be solved by the present technology is to provide a host device and a slave device having a cascade connection structure in order to solve the above-mentioned difficulties of the prior art.

The device according to this embodiment includes a port for chip select signal input and output, serial clock input and output, and serial data signal input and output, registers, and multiple slaves connected to each other and cascaded to each other. It is connected to the first stage of the slaves, and includes a host that forms and outputs a chip select signal, a serial clock and a serial data signal, and the serial data signal includes a set byte to control the slave and a register included in the slave. And the address byte of and the data byte to be read from or written to the register.

According to an aspect of the present technology, each of a plurality of slaves cascaded to each other is activated by a chip select signal output from a previous stage, receives a serial clock output from a previous stage, and samples serial data. .

According to an aspect of the present technology, a plurality of slaves cascaded from each other are provided with a chip select signal, and after 8 clocks, the next stage is activated, and a serial clock and a serial data signal are output.

According to an aspect of the present technology, the setting byte includes a read/write setting bit for controlling data writing and reading of the slave, and a packet for setting a desired slave among the slave's operation mode or a plurality of slaves. It includes an increase/decrease setting bit to set the packet processing bit to decrease or increase as data propagates through the processing bits and a plurality of slaves connected by cascade.

According to an aspect of the present technology, the host sets the increment/decrease setting bit so that the packet processing bit decreases as data propagates through each slave connected in a cascade, and as the packet processing bit decreases, the preset value is set in the target slave. If possible, set the read/write setting bit to perform data writing or reading on the target slave.

According to one aspect of the present technology, the host outputs an address of a register to write or read data through an address byte and outputs data to be written in a data byte.

According to an aspect of the present technology, the host sets and outputs a set byte so that a plurality of slaves connected by cascade write the same data.

According to one aspect of the present technology, the host outputs an address of a register to perform data writing through an address byte, and outputs data to be written as data bytes.

According to an aspect of the present technology, a slave is a controller that controls a digital signage.

According to the present invention, since a host and a plurality of slaves are cascaded to each other, an input/output port as many as the number of slaves is unnecessary, thereby providing economical effect. In addition, according to the present invention, since the slaves can be controlled with a set byte, an expensive computing device is unnecessary and thus economical advantages are provided.

1 is a block diagram showing the outline of the present invention.
FIG. 2 is a schematic timing diagram showing a reformation of signals input from one slave to input ports and output signals to output ports.
3 is a schematic diagram showing a schematic structure of serial data (SDA).
4 to 6 are diagrams for explaining the operation of the present invention.

Hereinafter, the present invention will be described with reference to the accompanying drawings. In describing the present invention, a single line and a bus are not distinguished for concise description and easy understanding.

Reference numerals such as a, b, and c are added to each of the same or similar plurality of components. When a description of any one of these is required, a sign may be added to explain it, and when a description of any one is unnecessary, a sign may be removed and described.

1 is a block diagram showing the outline of the present invention. Referring to FIG. 1, the present invention provides a port for each chip select signal input (CS_IN) and output (CS_OUT), serial clock input (SCL_IN) and output (SCL_OUT), and serial data input (SDA_IN) and output (SDA_OUT). , Connected to the initial stage of a plurality of slaves (200a, 200b, ... 200f) connected to each other cascaded and includes a register (not shown) and a plurality of slaves (200a, 200b, ... 200f) connected to a cascade It includes a host 100 that forms and outputs a chip select signal CS, a serial clock SCL, and serial data SDA, and the serial data SDA includes an assign byte to control the slave. , The address byte of the register included in the slave and a data byte to be stored in the register.

The host 100 forms a chip select signal CS, a serial clock signal SCL, and a serial data signal SDA, respectively, and a chip select signal output port CS_OUT, a serial clock output port SCL_OUT, and a serial data output port, respectively. Output as (SDA_OUT). The host 100 may include a processor (not shown) for signal formation and a memory (memory) storing necessary data.

A plurality of slaves (200a, 200b, ... 200f) is connected to a cascade (cascade), and provides chip select signal (SC), serial clock signal (SCL) and serial data (SDA) signal from the slave of the previous stage It receives and performs the necessary signal processing and provides it to the slave of the next stage.

For example, among the slaves connected by cascade, the first stage slave 200a may receive a signal from the host 100, and the last stage slave 200f may output a signal to the host 100.

Each slave may include a processor for signal processing and a register for storing data. In one embodiment, data stored by each slave may be 8 bits and may be input or output through a data byte included in the serial data signal (SDA). The address of the register included in each slave may be 8 bits, and the register may be accessed through an address byte included in the serial data signal (SDA).

In the embodiment illustrated in FIG. 1, each slave may be a controller that controls a digital signage (300), and the host (100) displays content such as images and videos to be displayed by the digital signage (300). Can be provided by the user. The host 100 may perform operations such as providing and dividing each controller by processing the provided contents.

FIG. 2 is a schematic timing diagram showing an improvement of signals input to input ports CS_IN, SCL_IN, and SDA_IN from one slave 200 and signals output to output ports CS_OUT, SCL_OUT, and SDA_OUT. . Referring to FIG. 2, a chip select signal CS is provided so that the corresponding slave 200 is enabled. According to the illustrated embodiment, when the chip select signal CS transitions to a logic low state, the slave 200 is activated. According to an exemplary embodiment, when the chip select signal CS transitions to a logic high state, the slave 200 may be activated.

The slave 200 provided with the signal may sample the serial data SDA provided from the previous stage as the serial clock signal SCL, and perform an operation corresponding to the sampled serial data SDA.

When the chip select signal CS, the serial clock signal SCL and the serial data signal SDA are provided to the slave 200, the corresponding slave performs processing according to the provided information, delays by a delay time of 8 clocks, and then Output to the stage.

3 is a schematic diagram showing a schematic structure of serial data (SDA). Referring to FIG. 3, the serial data (SDA) may be composed of a plurality of bytes including a set byte, an address byte, and a data byte. The address byte may be 8-bit data of [A7:A0], and is data corresponding to the address of the register included in the slave. The data byte may be 8-bit data of [D7:D0], and may be data to be read from or written to the register of the corresponding address.

The set byte (assign byte) may include an increase/decrease setting bit (DU), a read/write setting bit (RW), and packet processing bits of S[5:0]. The slave 200 controls to increase or decrease the output of the packet processing bits S[5:0] according to the increase/decrease setting bit DU. For example, when the increase/decrease setting bit DU is input to the slave in a logic low state, the corresponding slave 200 may reduce and output the packet processing bit by one. As another example, when the increase/decrease setting bit DU is input to the slave 200 in a logic high state, the corresponding slave 200 may increase and output the packet processing bit by one.

The slave 200 reads/writes a command input according to the read/write setting bit RW. For example, if the read/write setting bit RW input to the slave 200 is logic high, the slave 200 may write data provided as a data byte into a register of an address provided as an address byte. As another example, if the read/write setting bit RW input to the slave 200 is a logic low, the slave 200 may read data from a register of an address provided as an address byte and output it as a data byte.

The slave 200 processes the input packet according to the input packet processing bits S[5:0]. In one embodiment, if S[5:0] = 111111 (0x3F) provided to the slave 200, and the read/write setting bit is logic high, the same data is written to all slaves 200. Also, the slave 200 maintains and outputs the packet setting bits S[5:0] at 111111 (0x3F).

In another embodiment, if the packet processing bits S[5:0] provided to the slave 200 are any one of 101111 (0x2F) to 000001 (0x01), the packet processing bits S[] input according to the increase/decrease setting bit 5:0] is increased or decreased by 1 according to the increment/decrement setting bit (DU), and output.

In another embodiment, if S[5:0] provided to the slave 200 is 000000 (0x00) and the read/write setting bit is logic high, data provided as a data byte is written to and written to a register designated as an address byte. Output data. The slave 200 outputs 000001 (0x01) as a packet setting bit [5:0], a logic high for the increase/decrease setting bit (DU), and a logic low for the read/write setting bit.

Further, if the read/write setting bit is a logic low, data is read from a register designated as an address byte, and the read data is output provided as a data byte. The slave 200 outputs 000001 (0x01) as a packet setting bit [5:0], a logic high for the increase/decrease setting bit (DU), and a logic high for the read/write setting bit.

4 is a diagram for explaining a case in which the same data is written to all slaves 200. In FIG. 4, the content displayed adjacent to the signal line schematically describes the content of the signal transmitted through the serial data (SDA). Referring to FIG. 4, the host 100 has a state of increasing/decreasing control bits DU, which is a don't care, a read/write setting bit RW, a logic high, and packet processing bits S[5:0] Output 111111 (0x3F).

Since the logic high is provided as the read/write setting bits RW, and the packet processing bits S[5:0] are 111111 (0x3F), the packet processing bits S[5:0] are also outputted as 111111 (0x3F). . Accordingly, data provided as data bytes is written to registers corresponding to the address bytes of all the slaves 200a, 200b, ..., 200f connected by cascade.

5 is a diagram for explaining a case in which data is written to a specific slave 200c. As an example, it is assumed that the host 100 writes data to the third slave 200c among the plurality of slaves 200a, 200b, ..., 200f connected by cascade. The host outputs a logic low as the increment/decrease setting bit (DU), a logic high as the read/write setting bit (RW), and 000010 (0x02) as the packet processing bit S[5:0].

The slave 200a receives the packet setting bits S[5:0] 000010 (0x02), the logic low increment/decrease setting bits, and the logic high read/write configuration bits (RW) to receive the packet configuration bits S[5:0]. 1 Decrease 000001 (0x01), increase/decrease setting bit of logic low and read/write setting bit (RW) of logic high are output to slave 200b.

The slave 200b receives the packet setting bits S[5:0] 000001 (0x01), the logic low increment/decrease setting bits, and the logic high read/write configuration bits (RW) to receive the packet configuration bits S[5:0]. 1 Reduced 000000 (0x00), the logic low increment/decrease setting bit and logic high read/write setting bit RW are output to the slave 200c.

Since the slave 200c is provided with the packet setting bits S[5:0] 000000 (0x00) and the logic high read/write setting bits (RW), write the data provided as data bytes to the register of the address provided as the address byte Then, the written data is output as data bytes. The slave 200c converts and outputs the increment/decrement setting bit to logic high, and sets and outputs the packet setting bit S[5:0] 000001 (0x01).

Since the packet setting bits S[5:0] 000001 (0x01) and the increment/decrement setting bits of logic high are input to the slave 200d, the packet setting bits S[5:0] increased by 1 to 000010 (0x02) and logic high The increase/decrease setting bit is output to the slave 200e. Through this process, the slave 200f outputs 000100 (0x04), a logical high state increase/decrease setting bit (DU) and a read/write setting bit to the host 100 with the packet setting bits S[5:0].

As illustrated above, the host 100 may write data to a desired slave by adjusting the value of the packet setting bits S[5:0] and the increment/decrement setting bits (DU), and the received packet setting bits S[ 5:0] and the increment/decrement setting bit (DU) value, it can be determined whether the desired data has been successfully written to the target slave.

6 is a view for explaining a case in which data is read from a specific slave 200d. As an example, it is assumed that the host 100 reads data from the fourth slave 200d among the plurality of slaves 200a, 200b, ..., 200f connected by cascade. The host outputs 000011 (0x03) as a logic low as the increment/decrease setting bit (DU), a logic low as the read/write setting bit (RW), and a packet processing bit S[5:0].

The slave 200a, the slave 200b, and the slave 200c are provided with increment/decrement setting bits of a logic row, so the packet setting bits S[5:0] 000011 (0x03) output by the previous stage are decreased by 1, respectively, to the next stage. Output to the slave. Accordingly, the slave 200d is provided with the increment/decrement setting bits of the logic row, the read/write setting bits (RW) of the logic row, and the packet setting bits S[5:0] of 000000 (0x00).

The slave 200d reads data from a register of an address provided as an address byte and outputs data provided as a data byte. In addition, the slave 200d converts and outputs the increment/decrement setting bit to logic high, and sets and outputs the packet setting bit S[5:0] 000001 (0x01).

The packet setting bits S[5:0] 000010 (0x02) and the increment/decrement setting bits of logic high are input to the slave 200e, respectively, so that the packet setting bits S[5:0] are increased by 1, thereby setting the packet setting bits S[5]. :0] and the increment/decrement setting bits of the logic high state are output.

Through this process, the slave 200f sends 000011 (0x03), a logic high state increase/decrease setting bit (DU), and a logic low read/write setting bit to the host 100 as the packet setting bits S[5:0]. Output.

As described above, the host 100 may read data from the desired slave by adjusting the value of the packet setting bits S[5:0] and the increment/decrement setting bits (DU).

100: host
200a, 200b, 200c, 200d, 200e, 200f: slave
300a, 300b, 300c, 300d, 300e, 300f: digital signage
CS: Chip select signal
SCL: Serial clock
SDA: Serial data signal

Claims (9)

Ports for chip select signal input and output, serial clock input and output, and serial data signal input and output, respectively, and a plurality of slaves cascaded together including registers and
And a host connected to an initial stage of a plurality of slaves connected by the cascade to form and output the chip select signal, the serial clock and the serial data signal,
The serial data signal
A configuration byte (assign byte) for controlling the slave,
The address byte of the register included in the slave and
An apparatus comprising data bytes to be read from or written to the registers. According to claim 1,
Each of the plurality of slaves cascaded to each other,
Enabled by the chip select signal output from the previous stage,
A device that receives the serial clock output from the previous stage and samples the serial data. According to claim 2,
Each of the plurality of slaves cascaded to each other
8 clocks after receiving the chip select signal,
A device that activates the next stage and outputs a serial clock and serial data signal. According to claim 1,
The setting byte,
A read/write setting bit for controlling data writing and reading of the slave;
Packet processing bits for setting an operation mode of the slave or a desired slave among the plurality of slaves, and
And an increase/decrease setting bit that sets the packet processing bit to decrease or increase as data propagates through a plurality of slaves connected to the cascade. According to claim 4,
The host
The increase/decrease setting bit is set so that the packet processing bit decreases as data propagates through each slave connected to the cascade,
As the packet processing bit decreases, the target slave is set to a preset value,
An apparatus for setting the read/write setting bit to perform data writing or reading at the target slave. The method of claim 5,
The host
And outputting the address of the register to perform data writing or reading through the address byte.
An apparatus for outputting data to be written in the data bytes. According to claim 4,
The host
A device for setting and outputting the setting byte so that a plurality of slaves connected to the cascade write the same data. The method of claim 7,
The host outputs the address of the register to perform data writing through the address byte,
An apparatus for outputting data to be written in the data bytes. According to claim 1,
The slave device is a controller that controls a digital signage.

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