JP6445890B2 - Communication method and communication system - Google Patents

Description

  The present invention relates to a communication method and a communication system for performing communication by connecting two or more slave devices in series to a master device, and in particular, a specific slave device selectively selects a data string transmitted from a master device. The present invention relates to a communication method and a communication system that receive and control the load of the slave device.

  In a communication system in which a plurality of slave devices are connected in series to a single master device and configured in a single master / multi-slave method, a plurality of slave devices are used in a synchronous system such as SPI (Serial Peripheral Interface). In general, a control system that controls a continuous shift register is used.

  On the other hand, in an asynchronous communication system, by setting a unique ID code in each slave device in advance, each slave device can be controlled independently by the master device.

<First Conventional Example>
FIG. 9 shows a configuration of a plurality of conventional slave devices 300_1, 300_2, and 300_3 that are connected in parallel and used in an asynchronous communication system. The slave device 300_1 will be described as a representative. The slave device 300_1 receives an asynchronous data string SD and processes serial / parallel conversion and the like, a UART (Universal Asynchronous Receiver Transmitter) 301, a decoder 302 that decodes the received data string, and compares input and decoded ID codes An ID register 303 in which an ID code for identification is set and a general-purpose register 304 in which data for controlling the load of the slave device 300_1 are stored are provided.

  In the communication system of FIG. 9, different ID codes are set in the ID registers 303 of the slave devices 300_1, 300_2, and 300_3. If the ID code included in the data string SD input from the master device (not shown) matches the ID code stored in the ID register 303 of any slave device, it is included in the data string SD. The control data is stored in the general-purpose register 304 of the slave device whose ID code matches. Thereby, on / off of the LED or the like as a load of the slave device is controlled according to the data stored in the general-purpose register 304.

  In this way, different ID registers are set in advance for each slave device, and then a data string SD including an ID code and control data is transmitted to each slave device to select and control a specific slave device. As a thing, there exists description in patent document 1,2.

<Second Conventional Example>
FIG. 10 shows conventional slave devices 400_1, 400_2, and 400_3 having, for example, a 4-bit ID setting terminal 404 in which the GND potential is set as “0” and the VDD is set as “1”. 401 is a UART, 402 is a decoder, and 403 is a general-purpose register. In this conventional example, the ID code of the slave device can be set by operating the ID setting terminal 404.

<Third conventional example>
FIG. 11 is a diagram illustrating a plurality of serially connected slave devices 500_1, 500_2, 500_3, and 500_4 used in another conventional asynchronous communication system. In the communication system of FIG. 11, the ID code assigned to all the slave devices 500_1 to 500_4 is set as a common, for example, 0x00 (0x represents that the subsequent numerical value is a hexadecimal number).

  In this communication system, when a data string SD1 including an ID code of 0x03 and control data for controlling a load is output from a master device (not shown), the ID code in the data string SD1 is 1 in the first-stage slave device 500_1. The data string SD2 reduced by (= 0x01) to become 0x02 is input to the second-stage slave device 500_2.

  In the second-stage slave device 500_2, the ID code in the data string SD2 is further reduced by 1, and is input to the third-stage slave apparatus 500_3 as a data string SD3 that becomes 0x01.

  In the third-stage slave device 500_3, the ID code in the data string SD3 is further reduced by 1, and is input to the fourth-stage slave apparatus 500_4 as a data string SD4 that is 0x00.

  In the slave device 500_4 at the fourth stage, the ID code of 0x00 set in advance matches the ID code of the input data string SD4. Therefore, the control data included in the input data string SD4 controls the load of the fourth-stage slave device 500_4.

  In this way, a common ID code is set for the plurality of slave devices 500_1 to 500_4, and the ID code included in the data string SD0 transmitted from the master device 400 is subtracted one by one in each slave device. Patent Document 3 describes that a slave device is selected when the ID code of the subtraction result matches the ID code of a specific slave device.

Japanese Patent No. 4703394 Japanese Patent No. 4881696 JP 2014-134866 A

  However, in the first and second conventional examples, it is necessary to set different unique ID codes in advance to a plurality of slave devices. In the third conventional example, a common ID code can be set for a plurality of slave devices. However, since each slave device performs a subtraction operation of the ID code in the data string transmitted from the master device. Thus, it is impossible to transmit the data string SD1 with the error correction parity bit added.

  An object of the present invention is to make it possible to select a specific slave device by transmitting a data string to which a parity bit for error correction is added without having to set unique ID codes for a plurality of slave devices. And providing a communication system.

In order to achieve the above object, the invention according to claim 1 is configured to select information from a master device by selecting one slave device among a plurality of slave devices connected in series to the master device. A communication method for transmitting a data string including bits, wherein the master device performs error correction coding on the information bits to form information bits with parity, and one slave device to be selected from the plurality of slave devices. A number of "1" bits corresponding to the order from the master device are added to the head of the information bits with parity as address bits to create and transmit the data sequence, and each of the plurality of slave devices is Receiving the data string transmitted from the master device or the data string transmitted from the slave device in the previous stage, and The data starting from the bit next to the first “1” bit of the first bit is received as an information bit with received parity, and the decoded information bit is generated by decoding the information bit with received parity. When the same error correction coding as the error correction coding is performed to create information bits with reproduction parity, and the number of mismatch bits in the comparison between the information bits with reproduction parity and the information bits with reception parity is less than a predetermined value Determining that the received data sequence includes information bits addressed to the slave device, and creating a new data sequence in which only one “1” bit of the address bit is deleted from the received data sequence. It transmits to the slave device of the next stage, It is characterized by the above-mentioned.

  According to a second aspect of the present invention, a first slave device is selected from among a plurality of slave devices connected in series to the master device, and the first to nth (n is 2) for control from the master device. A communication method for transmitting a data string including information bits of the above integers), wherein the master device performs error correction coding on the first to n-th information bits to generate first to n-th information bits with parity. The number of “1” bits corresponding to the order from the master device of one slave device to be selected from among the plurality of slave devices is added to the head of the first information bit with parity as an address bit. The data string is generated and transmitted, and each of the plurality of slave devices is transmitted from the data string transmitted from the master device or the previous slave device. The received data string is received as data bits with first to nth received parity sequentially from the data starting from the bit next to the first “1” bit of the address bits. The first to n-th decoded information bits are generated by decoding the n-th received parity information bits, and the same error correction coding as the error correction coding is performed on the first to n-th decoded information bits. To generate first to n-th information bits with reproduction parity, a first comparison between the first information bits with reception parity and the first information bits with reproduction parity, to the n-th reproduction parity bits. Each of the information bits with reception parity and the nth information bit with reproduction parity is compared, and the number of mismatch bits in each of the first to nth comparisons is a predetermined value. In the following case, it is determined that the received data string includes information bits addressed to the slave device, and a new data string in which only one “1” bit of the address bit is deleted from the received data string It is created and transmitted to the slave device at the next stage.

  According to the third aspect of the present invention, one slave device is selected from a plurality of slave devices connected in series to the master device, and the first to nth (n is 2) an information bit) and a data string sequentially including checksum bits created based on the first to nth information bits, wherein the master device includes the first to the first information bits. The n-th information bit and the checksum bit are error-correction-encoded to form first to n-th information bits with parity and checksum bits with parity, and one slave device to be selected from among the plurality of slave devices. The number of “1” bits corresponding to the order from the master device is added to the head of the first information bit with parity as an address bit. The data sequence is generated and transmitted by each of the plurality of slave devices, and each of the plurality of slave devices receives the data sequence transmitted from the master device or the data sequence transmitted from the previous slave device, and The first to nth received information bits with received parity and the checksum bit with received parity are sequentially received from the data starting from the bit next to the first one “1” bit, and with the first to nth received parity The checksum bits are decoded to create first to nth checksum bits with decoded parity, and the same error correction coding as the error correction coding is performed on the checksum bits with decoded parity, and the reproduced parity is added. Create a checksum bit, and checksum bit with received parity and check parity bit When the number of mismatch bits in comparison with the checksum bit is equal to or less than a predetermined value, it is determined that the received data string includes an information bit addressed to the slave device, and the address bit “1” is determined from the received data string. A new data string from which only one bit is deleted is generated and transmitted to the slave device at the next stage.

According to a fourth aspect of the present invention, a slave device is selected from a plurality of slave devices connected in series to the master device, and the first to nth (n is 2 or an integer) and a data string sequentially including checksum bits generated based on the first to nth information bits, wherein the master device includes the first to the first The n information bits and the checksum bits are error-correction-encoded to form first to n-th information bits with parity and checksum bits with parity, and the slave device to be selected among the plurality of slave devices is selected. A number of “1” bits corresponding to the order from the master device are added to the head of the first information bits with parity as address bits. The data sequence is generated and transmitted, and each of the plurality of slave devices receives the data sequence transmitted from the master device or the data sequence transmitted from the previous slave device, and The first to nth received information bits with received parity and the checksum bit with received parity are sequentially received from the data starting from the bit next to the first one “1” bit, and with the first to nth received parity information bits and creates a decoded parity information bits and checksum bits with decoded parity of the first to n decodes the received parity checksum bits, the first to decode parity information bits and the n-th Same error correction coding as the error correction coding for checksum bits with decoding parity To generate first to n-th information bits with reproduction parity and checksum bits with reproduction parity, a first comparison between the first information bits with reception parity and the first information bits with reproduction parity, Or n-th comparison between the n-th received parity information bit and the n-th reproduced parity information bit, and a checksum bit comparison between the received parity checksum bit and the reproduced parity checksum bit. When the number of mismatch bits in the first to nth comparisons and the checksum bit comparison is less than or equal to a predetermined value, it is determined that the received data sequence includes information bits addressed to the slave device, and the reception A new data string is created by deleting only one “1” bit of the address bit from the data string. And it transmits to the next slave device and characterized in that.

  According to a fifth aspect of the present invention, in the communication method according to any one of the first to fourth aspects, the error correction coding and decoding are performed using a BCH code.

The invention according to claim 6 includes a master device and a plurality of slave devices connected in series to the master device, and selects one of the plurality of slave devices to select the master device. A communication system for transmitting a data sequence including information bits for control from the master device, wherein the master device performs error correction coding on the information bits to generate information bits with parity, and the plurality of the plurality of information bits. An address bit creation circuit for adding a number of “1” bits corresponding to the order from the master device of one slave device to be selected as an address bit to the head of the information bits with parity. The data string is composed of the address bits and the information bits with parity, and each of the plurality of slave devices. Receives the data sequence transmitted from the master device or the data sequence transmitted from the slave device in the previous stage, and receives data starting from the next one “1” bit of the data sequence as information with parity A decoder that accepts as bits and decodes into decoded information bits; a second encoder that performs error correction coding same as the error correction coding on the decoded information bits to create information bits with reproduction parity; and the reception A data comparison circuit that determines that the received data string includes information bits addressed to the slave device when the number of mismatch bits in the comparison between the information bits with parity and the information bits with reproduction parity is equal to or less than a predetermined value; Create a new data sequence by deleting only one “1” address bit from the received data sequence. And a bit operation circuit for transmitting to the slave device of the stage.

The invention according to claim 7 includes a master device and a plurality of slave devices connected in series to the master device, and selects one of the plurality of slave devices to select the master device. A communication system for transmitting a data string including 1st to nth (n is a positive integer) information bits for control, wherein the master device performs error correction on the 1st to nth information bits A first encoder that encodes first to n-th information bits with parity and a number corresponding to the order from the master device of one slave device to be selected among the plurality of slave devices; An address bit creating circuit for adding the bit of 1 ″ as an address bit to the head of the information bit with the first parity and transmitting it as the data string. Each of the slave devices receives the data string transmitted from the master device or the data string transmitted from the previous slave device, and receives data starting from the next one bit of “1” in the data string. A decoder that accepts first to n-th received information bits with received parity and decodes them to first to n-th decoded information bits; and the same error as the error correction coding for the first to n-th decoded information bits A second encoder that performs correction coding to generate first to n-th information bits with reproduction parity, and a first information bit with the first reception parity and the first information bit with reproduction parity. The n th comparison between the n th received information bit with received parity and the n th received information bit with reproduction parity is performed, and in each of the first through n th comparisons. A data comparison circuit that determines that the received data string includes an information bit addressed to the slave device when the number of mismatch bits is less than or equal to a predetermined value, and a bit “1” of the address bit from the received data string And a bit operation circuit that creates a new data string from which only one is deleted and transmits it to the slave device at the next stage.

  The invention according to claim 8 includes a master device and a plurality of slave devices connected in series to the master device, and selects one of the plurality of slave devices to select the master device. To a data sequence sequentially including first to nth (n is a positive integer) information bits for control and checksum bits generated based on the first to nth information bits. The master device performs error correction coding on the first to n-th information bits to create information bits with parity, and error correction codes the parity checksum bits to create checksum bits with parity. One encoder and a number of "1" corresponding to the order from the master device of one slave device to be selected from among the plurality of slave devices An address bit creating circuit for adding the first bit to the head of the information bit with the first parity as an address bit, and each of the plurality of slave devices includes the data string transmitted from the master device or the previous slave A data string transmitted from the apparatus is received, and data starting from the next one “1” bit of the data string is accepted as first to nth information bits with received parity and checksum bits with received parity. A decoder for decoding the first to nth decoded information bits and the decoded checksum bit, and performing the same error correction coding as the error correction coding on the decoded checksum bit to create a checksum bit with reproduction parity The second encoder, the checksum bit with received parity, and the playback parameter. A data comparison circuit that determines that the received data sequence includes information bits addressed to the slave device when the number of mismatched bits in the comparison with the checksum bit with the utility is equal to or less than a predetermined value, and the received data sequence from the received data sequence And a bit operation circuit that creates a new data string in which only one “1” bit of the address bit is deleted and transmits it to the slave device at the next stage.

The invention according to claim 9 includes a master device and a plurality of slave devices connected in series to the master device, and selects one slave device of the plurality of slave devices to select the master device. To a data sequence sequentially including first to nth (n is a positive integer) information bits for control and checksum bits generated based on the first to nth information bits. The master device performs error correction coding on the first to n-th information bits to create information bits with parity, and error correction codes the parity checksum bits to create checksum bits with parity. One encoder and a number of "1" corresponding to the order from the master device of one slave device to be selected from among the plurality of slave devices An address bit creating circuit for adding the first bit to the head of the information bit with the first parity as an address bit, and each of the plurality of slave devices includes the data string transmitted from the master device or the previous slave A data string transmitted from the apparatus is received, and data starting from the next one “1” bit of the data string is accepted as first to nth information bits with received parity and checksum bits with received parity. Decoding the first to nth decoded information bits and the decoded checksum bits, and the same as the error correction coding for the first to nth decoded information bits and the decoded checksum bits Error correction coding is performed to obtain information bits with first to nth reproduced parity and a check with reproduced parity. A second encoder for creating Kkusamubitto, first comparison between the first said and received parity information bits first playback parity information bits, to the a receiving parity information bits of the first n second n-th comparison with n information bits with reproduction parity, and checksum comparison between the checksum bit with reception parity and the checksum bit with reproduction parity, and the first to nth comparisons and the checksum A data comparison circuit that determines that the received data string includes information bits addressed to the slave device when the number of mismatch bits in the comparison is less than or equal to a predetermined value; and “1” of the address bit from the received data string Bit operation that creates a new data string with only one bit deleted and sends it to the slave device at the next stage And a road, characterized in that.

  According to a tenth aspect of the present invention, in the communication system according to any one of the sixth to ninth aspects, the error correction coding and decoding are performed by a BCH code.

  According to the present invention, a specific slave device can be accurately selected without setting a unique ID code to a plurality of slave devices and transmitting a data string to which error correction parity bits are added. Can do.

It is a block diagram which shows the structure of the communication system of the Example of this invention. It is a wave form diagram of four types of data strings output from the master device of FIG. Is a table of BCH encoding. Is a table of BCH encoding. FIG. 3 is a circuit diagram of a serial / parallel conversion circuit and a bit operation circuit of a slave device. FIG. 5 is a block diagram showing an internal configuration of the control circuit of FIG. 4. FIG. 6 is a cycle diagram of the state machine of FIG. 5. It is a waveform diagram in each slave device when “4” is set as an address in the master device. It is explanatory drawing of the data in each slave apparatus when "4" is set as an address of a master apparatus. It is explanatory drawing of a 1st prior art example. It is explanatory drawing of the 2nd prior art example. It is explanatory drawing of a 3rd prior art example.

  FIG. 1 shows the configuration of a communication system according to an embodiment of the present invention. Reference numerals 100_1, 100_2,..., 100_4 are four slave devices controlled independently from each other by one master device 200. One data line and one clock line are connected to the master device 200. Are connected in series in order. 100_1, 100_2,..., 100_4 have the same configuration.

  FIG. 2 is a diagram illustrating a data structure generated by the master device 200. Here, since there are four slave devices, one of the four types shown in (a) to (d) is used as the data string SD1 and the clock SCK1 output from the master device 200. (A) is for selection of the first slave device 100_1, and is an example in which only one piece of data “1” as an address bit is added to the head of the data string SD1. (B) is for selecting the second slave device 100_2, and is an example in which only two pieces of data “1” as address bits are added to the head of the data string SD1. (C) is for selecting the third slave device 100_3, and is an example in which only three pieces of data “1” as address bits are added to the head of the data string SD1. (D) is for selection of the fourth slave device 100_4, and is an example in which only four pieces of “1” data as address bits are added to the head of the data string SD1.

  The data string SD1 shown in (a) to (d) is an information bit with parity consisting of an 8-bit information bit DB1 and an 8-bit parity bit PB1 after 1 to 4 address bits of “1” bits. DATA1 is provided. Further, DATA2 to DATA4 having the same structure are provided behind the DATA1. Finally, there is provided a SUM which is a checksum bit with parity, which is composed of an 8-bit checksum bit DB5 and an 8-bit parity bit BP5 created based on the information bits DB1 to DB4 of DATA1 to DATA4.

  SCK1 is a clock for synchronization transmitted on a different path from the data string SD1. In order to synchronize the address bits, a number of clock components corresponding to 1 to 4 “1” bits added immediately before DATA1 are added to the clock SCK1.

  The configuration of the master device 200 in FIG. 1 will be described. 201 is a data register in which information bits DB1 to DB4 of DATA1 to DATA4 are stored, and 202 is a checksum calculation circuit for calculating and creating checksum bit DB5 based on information bits DB1 to DB4 stored in data register 201 , 203 is a selection circuit for selecting any one of the information bits DB1 to DB4 or the checksum bit from the information bits DB1 to DB4 read from the data register 201 and the checksum bit DB5 generated by the checksum calculation circuit 202. is there.

  Reference numeral 204 denotes a BCH encoder. The information bits DB1 to DB4 and the check subbit DB5 obtained by the selection circuit 203 are individually subjected to BCH encoding for error correction, and the information bits with data DATA1 to DATA4 with parity and the parity bits are added. Create checksum bit SUM.

This BCH encoding is performed by, for example, the following formula GP (x) = x ⁸ + x ⁵ + x ⁴ ++ x ³ +1 as a generator polynomial.
Is used, 8-bit information bits and checksum bits are encoded into any of 2 ⁸ (= 256) data as shown in the tables of FIGS. 3A and 3B. For example, the bit with parity of the BCH code when the information bit is 0x01 is 0x01D7.

  205 is an address bit creation circuit for setting an address bit for specifying any one of the slave devices. As described above, one “1” bit, or two, three, or four consecutive bits The address bit is set by the “1” bit to be added and is added to the preceding stage of DATA1 to DATA4 and SUM.

  A parallel-serial conversion circuit 206 converts parallel data of DATA1 to DATA4 and SUM into a real data string SD1 shown in any one of (a) to (d) of FIG. 2 and a clock SCK1. Output. A control circuit 207 includes a computer that controls the entire master device 200.

  Next, the configuration of the slave device will be described on behalf of the slave device 100_1 in FIG. 101 is a serial / parallel conversion circuit that converts an input serial data string SD1 into a parallel signal by an input clock signal SCK1, and 102 is a BCH decoder that decodes information bits DATA1 to DATA4 with parity from the data string SD1 that has become parallel data. It is.

In this BCH decoder 102, five pieces of data (four information bits with received parity) are generated every 16 bits from data starting from the next bit after the first one “1” bit of the address bit ADB of the data string SD1. And one checksum bit with received parity) are decoded into 8-bit information bits (decoded information bits corresponding to DB1 to DB4 and decoded checksum bits corresponding to DB5). In each decoding, since ¹⁶ (= 65,536) pieces of decoding information bits are obtained, a lookup table is created in advance, for example.

  When 1-bit error correction is possible, 16 + 1 = 17 patterns, 256 × 17 = 4325 patterns in total are valid data, and the rest are invalid data. When 2-bit error correction is possible, 16 × 15 + 1 = 241 patterns, or 256 × 241 = 61969 patterns in total, are valid data. In this decoding, proper information bits cannot be decoded except for data in the “with parity” column in FIGS. 3A and 3B. When creating a decoding table, there are cases where a plurality of data cannot be identified, and in this case, correction is not possible, so the data indicating that is “FFFF.” The output data is 8 bits (including 1 bit error). Since the present invention is not directly related to error correction itself, detailed description thereof is omitted.

  Reference numeral 103 denotes a BCH encoder, which again performs BCH encoding based on each of the four information bits decoded by the BCH decoder 102 to create four 16-bit information bits with reproduction parity. The BCH encoder 103 performs the same encoding as the BCH encoder 204 of the master device 200.

  A checksum calculation circuit 104 calculates a checksum based on the four decoded information bits decoded by the BCH decoder 102 and creates a reproduction checksum bit (corresponding to DB5).

  A BCH encoder 105 BCH-encodes the checksum bit calculated by the checksum calculation circuit 104 to create a checksum bit with reproduction parity (equivalent to SUM). The BCH encoder 105 is realized by using the BCH encoder 103 in a time division manner.

  Reference numeral 106 denotes a data comparison circuit, a received data string comprising four information bits with received parity and one checksum bit with received parity obtained by the serial / parallel conversion circuit 101, a BCH encoder 103, a checksum calculation circuit The four information bits with reproduction parity obtained by the 104 and the BCH encoder 105 are compared with a reproduction data string composed of one checksum bit with reproduction parity, and the number of mismatch bits is calculated to determine the degree of coincidence. .

  Reference numeral 107 denotes a data register. When the number of mismatch bits in the comparison by the data comparison circuit 106 is equal to or less than a predetermined value, the received data string SD1 is considered to be valid, and the four pieces of information decoded by the BCH decoder at this time Of the bits, information bits (corresponding to DB1 to DB4) are extracted and stored. Reference numeral 108 denotes a load such as an LED controlled by data stored in the data register 170, and reference numeral 109 denotes a control circuit for controlling the whole.

  Reference numeral 110 denotes a bit manipulation circuit, which is generated by deleting only one leading “1” bit from the received data string SD1 and deleting the first clock from the clock SCK1. A new clock SCK2 is created and sent to the slave device 100_2 at the next stage.

  FIG. 4 shows a circuit of the serial / parallel converter 101 and the bit operation circuit 110 of the slave device 100_1. Since the real parallel conversion is performed by sampling the received data SD1 in units of 16 bits with the reception clock SCK1, the serial / parallel converter 101 is configured by connecting 16 DFF circuits FF1 to FF16 in series. The serial-parallel converter 101 outputs 16 pieces of data output as D0 to D15 to the BCH decoder 102 every time 16 reception clocks SCK1 are input.

  The bit operation circuit 110 includes a control circuit 110a that takes in the received data string SD1 and the received clock SCK1, a DFF circuit FF20, inverters INV1 and INV2, and multiplexers MPX1 and MPX2.

  As shown in FIG. 5, the control circuit 110a includes a counter 110a1 that counts the input clock SCK1 and a state machine 101a2. When the state machine 101a2 detects “1” of the data string SD1 at the rising edge of the clock SCK1 in the “IDLE” state as shown in the machine cycle shown in FIG. 6, the state shifts to “LOAD”, and the next state The signal SEL is set to “1” at the rising edge of the clock SCK1. When the signal SEL becomes “1”, the multiplexer MPX1 selects the Q output of the DFF circuit FF20, and the multiplexer MPX2 selects the output of the inverter INV2. At this time, the timing selected by the multiplexers MP1 and MP2 is the time when the clock SCK1 has elapsed for one clock since the detection of “1” in the data string SD1, so that the data string SD1 after this one clock is a new one. Is output as a simple data string SD2.

  In this way, the bit operation circuit 110 outputs a new data string SD2 from which only one “1” bit at the head of the data string SD1 has been deleted to the subsequent slave device. The clock SCK2 also starts from a clock that has passed one clock from the beginning of the clock SCK1.

  When LOAD for one clock is completed, the state of the state machine 110a2 becomes “DATA1”, and the slave device 100_1 processes the data string SD1 input from that time as “DATA1” data (such as the above-described decoder, encoder, comparison, etc.). Process). Thereafter, every time the counter 110a1 counts 16 (count value = 0x0F), the state changes from “DATA2” → “DATA3” → “DATA4” → “SUM” → “STOP”, and the received data string SD1 is the same. To process. After that, when the clock signal SCK0 is not received for a certain period of time, the time is over and the flow returns to “LOAD”.

Next, the operation will be described. Here, the information bits DB1 to DB4 stored in the data register 201 of the slave device 200 are
DB1 = 0x9D
DB2 = 0x7C
DB3 = 0xB9
DB4 = 0x90
The case will be described. In this case, the checksum bit DB5 created by the checksum calculation circuit 202 is
DB5 = 0x62
It becomes.

Then, the parity-added information bits DATA1 to DATA4 and the checksum bit with parity SUM created by BCH encoding in the BCH encoder 204 are obtained from the tables shown in FIGS. 3A and 3B.
DATA1 = 0x9DB9
DATA2 = 0x7C66
DATA3 = 0xB9D2
DATA4 = 0x9095
SUM = 0x62DA
It becomes.

  Here, when the information bits DB1 to DB4 of the data string SD1 are selectively received by the slave device 100_4 and the load 108 is driven, four consecutive “1” s are added to the head of the data string SD1. An address bit consisting of "" is added.

  The data string SD1 and the clock signal SCK1 output from the master device 200 under the above conditions are shown as SD1 and SCK1 in FIG. The contents of the data are shown in FIG.

  When this data sequence SD1 is input from the master device 200 to the slave device 100_1, the leading “1” bit of the data sequence SD1 is detected by the rising edge of the clock SCK1, and the machine cycle of the state machine 110a2 of the slave device 100_1 is one clock cycle. Only after 16 bits, the state changes from “DATA1” → “DATA2” → “DATA3” → “DATA4” → “SUM” every 16 bits.

  Each piece of data captured in the state of “DATA1” is data starting from the second bit from the beginning of the original four “1” address bits. In other words, the data captured by “DATA1”, “DATA2”, “DATA3”, “DATA4”, “SUM” is data obtained by shifting the data string SD1 to the left by 1 bit, and “received data” in FIG. The value shown in the column (A). The data decoded by the BCH decoder 102 has a value shown in the “information bit” column of FIG.

  The value shown in the column of “information bits” is re-encoded by the BCH encoder 103, and similarly, a checksum calculation circuit 104 generates a checksum bit and then re-encodes it by the BCH encoder 105. The data of .about.DATA4 and SUM have values shown in the column “Re-encode (B)” in FIG.

  Therefore, when the data DATA1 to DATA4 and SUM in the “Received Data (A)” column and the data DATA1 to DATA4 and SUM in the “Re-encode (B)” column are compared by the data comparison circuit 106, the “number of mismatch bits” is obtained. The value shown in the column “” is obtained. Thus, since the value in the “number of mismatch bits” field is other than 0, it is determined here that the input data string SD1 is not a data string destined for the slave device 100_1.

  Next, the data string SD2 created by deleting only one leading “1” bit of the data string SD1 in the slave device 100_1 is input to the slave device 100_2 at the next stage. However, also in this slave device 100_2, as shown in FIG. 7B and FIG. 8C, the transmitted data DATA1 to DATA4, SUM, and states “DATA1”, “DATA2”, “DATA3”. ”,“ DATA4 ”, and“ SUM ”do not match, the value in the“ mismatch bit number ”column shown in FIG. 8C does not become 0, and the input data string SD2 is the slave device 100_2. It is determined that the data string is not a destination. This is the same as shown in (c) of FIG. 7 and (d) of FIG. 8 even when input to the slave device 100_3 in the next stage.

  Now, the data string SD4 input to the slave device 100_4 is a data string in which three leading “1” bits of the data string SD3 are deleted. At this time, the first “1” bit (only one remains) of the data string SD4 is detected by the rising edge of the clock SCK1, and the machine cycle of the state machine 110a2 of the slave device 100_4 is “LOAD”. ”State. After that, when the state changes from “DATA1” → “DATA2” → “DATA3” → “DATA4” → “SUM” every 16 bits, the state “DATA1” as shown in FIG. To “DATA4” and “SUM” respectively match DATA1 to DATA4 and SUM of the data string SD4.

  Therefore, as shown in FIG. 8E, the data in the “Received Data (A)” column is the same as the data in the “Received Data (A)” column in FIG. Therefore, the data in the “information bit” column obtained by decoding the same is also the same as the data in the “information bit” column in FIG. 8A, and the data of “re-encoder (B)” which is encoded again. Is the same. Therefore, all of the “mismatch bit number” fields are zero. Thereby, it is determined that the data string SD1 transmitted from the master device 200 is destined for the slave device 100_4.

  In this embodiment, the information bits with reception parity and the information bits with reproduction parity are compared for each of the four information bits, and the checksum bit with reception parity and the checksum with reproduction parity are compared for one checksum bit. A comparison with the bit is made to determine whether or not it is destined for the slave device, but this is not restrictive. For example, one information bit with reception parity and one information bit with reproduction parity may be compared to determine whether it is destined for the slave device, or four information bits with reception parity and reproduction parity A comparison of information bits may be made to determine whether or not it is destined for the slave device, and one checksum bit with received parity and a checksum bit with reproduction parity are compared and addressed to the slave device It may be determined whether or not. In addition, although the BCH code is used as the error correction code, the present invention is not limited to this, and it is needless to say that other encodings can be used.

100_1 to 100_4: slave device, 101: serial-parallel conversion circuit, 102: BCH decoder, 103: BCH decoder, 104: checksum calculation circuit, 105: BCH encoder, 106: data comparison circuit, 107: data register, 108: load 109: control circuit, 110: bit manipulation circuit 200: master circuit, 201: data register, 202: checksum calculation circuit, 203: selection circuit, 204: BCH encoder, 205: address bit generation circuit, 206: parallel serial conversion Circuit 207: Clock generation circuit

Claims (10)

A communication method for selecting a slave device from a plurality of slave devices connected in series to a master device and transmitting a data string including information bits for control from the master device,
The master device performs error correction coding on the information bits to form information bits with parity, and a number of “1” corresponding to the order from the master device of one slave device to be selected from among the plurality of slave devices. The data string is created and transmitted by prepending the information bits with parity to the beginning of the information bits with parity as address bits,
Each of the plurality of slave devices receives the data string transmitted from the master device or the data string transmitted from the slave device in the previous stage, and follows the first “1” bit of the address bits. The data starting from this bit is received as an information bit with received parity, the information bit with received parity is decoded to create a decoded information bit, and the same error correction coding as the error correction coding is performed on the decoded information bit To create information bits with playback parity,
When the number of mismatch bits in the comparison between the information bits with reproduction parity and the information bits with reception parity is a predetermined value or less, it is determined that the received data string includes information bits addressed to the slave device;
Creating a new data sequence in which only one “1” bit of the address bit is deleted from the received data sequence and transmitting it to the slave device at the next stage;
A communication method characterized by the above.
A slave device selected from a plurality of slave devices connected in series to the master device is selected, and first to nth (n is an integer of 2 or more) information bits for control are selected from the master device. A communication method for transmitting a data string including:
The master device performs error correction coding on the first to n-th information bits to form first to n-th information bits with parity, and the master of one slave device to be selected from among the plurality of slave devices. A number of "1" bits corresponding to the order from the device is added to the head of the first information bit with parity as an address bit, and the data string is created and transmitted.
Each of the plurality of slave devices receives the data string transmitted from the master device or the data string transmitted from the slave device in the previous stage, and follows the first “1” bit of the address bits. The first to nth received information bits with received parity are sequentially received from the data starting from the first bit, and the first to nth received information bits with received parity are decoded to generate the first to nth decoded information bits. And performing the same error correction coding as the error correction coding on the first to n-th decoded information bits, respectively, to generate first to n-th information bits with reproduction parity,
A first comparison between the first information bit with reception parity and the first information bit with reproduction parity, or the nth information bit with reception parity and the nth information bit with reproduction parity. Make each comparison,
When the number of mismatch bits in each of the first to nth comparisons is less than or equal to a predetermined value, it is determined that the received data string includes information bits addressed to the slave device;
Creating a new data sequence in which only one “1” bit of the address bit is deleted from the received data sequence and transmitting it to the slave device at the next stage;
A communication method characterized by the above. First to nth (n is an integer of 2 or more) information bits for control from one master device selected from a plurality of slave devices connected in series to the master device. And a communication method for transmitting a data sequence sequentially including checksum bits generated based on the first to n-th information bits,
The master device performs error correction coding on the first to n-th information bits and the checksum bits to form first to n-th information bits with parity and checksum bits with parity, and includes the plurality of slave devices. The number of “1” bits corresponding to the order from the master device of one slave device to be selected is added to the head of the first information bit with parity as an address bit to create the data string. Send
Each of the plurality of slave devices receives the data string transmitted from the master device or the data string transmitted from the slave device in the previous stage, and follows the first “1” bit of the address bits. The first to nth received information bits with received parity and the received checksum bits with received parity are sequentially received from the data starting from the first bit, and the first to nth received parity checksum bits are decoded to obtain the first to nth received parity bits. n checksum bits with decoded parity are generated, and the same error correction coding as the error correction coding is performed on the checksum bits with decoded parity to generate checksum bits with reproduction parity,
When the number of mismatch bits in the comparison between the checksum bit with received parity and the checksum bit with reproduction parity is a predetermined value or less, it is determined that the received data string includes an information bit addressed to the slave device;
Creating a new data sequence in which only one “1” bit of the address bit is deleted from the received data sequence and transmitting it to the slave device at the next stage;
A communication method characterized by the above. First to nth (n is an integer of 2 or more) information bits for control from one master device selected from a plurality of slave devices connected in series to the master device. And a communication method for transmitting a data sequence sequentially including checksum bits generated based on the first to n-th information bits,
The master device performs error correction coding on the first to n-th information bits and the checksum bits to form first to n-th information bits with parity and checksum bits with parity, and includes the plurality of slave devices. The number of “1” bits corresponding to the order from the master device of one slave device to be selected is added to the head of the first information bit with parity as an address bit to create the data string. Send
Each of the plurality of slave devices receives the data string transmitted from the master device or the data string transmitted from the slave device in the previous stage, and follows the first “1” bit of the address bits. The first to nth received information bits with received parity and the checksum bit with received parity are sequentially received from the data starting from the first bit, and the first to nth received information bits with received parity and the checksum bit with received parity are The first to n-th decoded parity-added information bits and the decoded parity-added checksum bits are decoded to generate the error for the first to n-th decoded parity-added information bits and the decoded parity-added checksum bits. first to play parity of the n by performing the same error correction encoding and correction coding Create an information bit and checksum bit with playback parity can,
A first comparison between the first information bit with reception parity and the first information bit with reproduction parity, or the nth information bit with reception parity and the nth information bit with reproduction parity. A comparison, and checksum bit comparison of the checksum bit with received parity and the checksum bit with reproduction parity,
When the number of mismatch bits in the first to nth comparisons and the checksum bit comparison is equal to or less than a predetermined value, it is determined that the received data string includes information bits addressed to the slave device;
Creating a new data sequence in which only one “1” bit of the address bit is deleted from the received data sequence and transmitting it to the slave device at the next stage;
A communication method characterized by the above.
The communication method according to any one of claims 1 to 4,
The error correction encoding and decoding are performed by a BCH code. A master device and a plurality of slave devices connected in series to the master device, wherein one slave device is selected from the plurality of slave devices and information bits for control are transmitted from the master device. A communication system for transmitting a data string including:
The master device includes, in order from the master device, a first encoder that performs error correction coding on the information bits to create information bits with parity, and one slave device to be selected from the plurality of slave devices. An address bit creating circuit for adding a corresponding number of “1” bits as address bits to the head of the information bits with parity, and the data string is composed of the address bits and the information bits with parity,
Each of the plurality of slave devices receives the data sequence transmitted from the master device or the data sequence transmitted from the slave device in the previous stage, and follows the first “1” bit of the data sequence. A decoder that accepts starting data as information bits with received parity and decodes them into decoded information bits, and performs the same error correction coding as the error correction coding on the decoded information bits to create information bits with reproduction parity 2 and when the number of mismatch bits in the comparison between the information bits with received parity and the information bits with reproduction parity is equal to or smaller than a predetermined value, the received data string is determined to include information bits addressed to the slave device. And a data comparison circuit that deletes only one “1” bit of the address bit from the received data string. And a bit operation circuit to be transmitted to the next stage of the slave device by creating a new data sequence,
A communication system characterized by the above.
A master device, and a plurality of slave devices connected in series to the master device, wherein one slave device is selected from the plurality of slave devices, and first to first control devices for controlling from the master device A communication system for transmitting a data sequence including n-th (n is a positive integer) information bits,
The master device should select a first encoder that performs error correction coding on the first to n-th information bits to generate first to n-th information bits with parity, and the plurality of slave devices. An address bit generation circuit for adding a number of “1” bits corresponding to the order of one slave device from the master device to the head of the first information bit with parity as an address bit, and transmitting as the data string; With
Each of the plurality of slave devices receives the data sequence transmitted from the master device or the data sequence transmitted from the slave device in the previous stage, and follows the first “1” bit of the data sequence. A decoder that accepts starting data as first to nth received parity-added information bits and decodes the first to nth decoded information bits; and the error correction coding for the first to nth decoded information bits A first encoder that performs the same error correction coding as above to generate first to n-th information bits with reproduction parity, and the first information bit with reception parity and the first information bit with reproduction parity. first comparison, to perform a comparison of the first n of the reproduction parity information bits of the first n and the received parity information bits of the n-th, the comparison of the first to n A data comparison circuit that determines that the received data string includes information bits addressed to the slave device when the number of mismatch bits in each is less than or equal to a predetermined value; and the address bit “1” from the received data string A bit operation circuit that creates a new data string from which only one bit has been deleted and transmits it to the slave device at the next stage,
A communication system characterized by the above.
A master device, and a plurality of slave devices connected in series to the master device, wherein one slave device is selected from the plurality of slave devices, and first to first control devices for controlling from the master device A communication system for transmitting a data sequence sequentially including n-th (n is a positive integer) information bits and checksum bits generated based on the first to n-th information bits,
The master device performs error correction coding on the first to n-th information bits to create an information bit with parity, and also performs error correction coding on the checksum bit to create a checksum bit with parity. In addition, a number of “1” bits corresponding to the order from the master device of one slave device to be selected from among the plurality of slave devices is added to the head of the first information bit with parity as an address bit. And an address bit creation circuit that
Each of the plurality of slave devices receives the data sequence transmitted from the master device or the data sequence transmitted from the slave device in the previous stage, and follows the first “1” bit of the data sequence. A decoder that accepts data starting as first to nth received information bits with received parity and a checksum bit with received parity and decodes the first to nth decoded information bits and decoded checksum bits; A second encoder that performs the same error correction coding as the error correction coding to create a checksum bit with reproduction parity, and a mismatch in comparison between the checksum bit with reception parity and the checksum bit with reproduction parity When the number of bits is less than a predetermined value, the received data string is A data comparison circuit for determining that the information bit addressed to the device is included, and a slave device in the next stage by creating a new data sequence in which only one “1” bit of the address bit is deleted from the received data sequence A bit manipulation circuit for transmitting to
A communication system characterized by the above. A master device, and a plurality of slave devices connected in series to the master device, wherein one slave device is selected from the plurality of slave devices, and first to first control devices for controlling from the master device A communication system for transmitting a data sequence sequentially including n-th (n is a positive integer) information bits and checksum bits generated based on the first to n-th information bits,
The master device performs error correction coding on the first to n-th information bits to create an information bit with parity, and also performs error correction coding on the checksum bit to create a checksum bit with parity. In addition, a number of “1” bits corresponding to the order from the master device of one slave device to be selected from among the plurality of slave devices is added to the head of the first information bit with parity as an address bit. And an address bit creation circuit that
Each of the plurality of slave devices receives the data sequence transmitted from the master device or the data sequence transmitted from the slave device in the previous stage, and follows the first “1” bit of the data sequence. A decoder that accepts and decodes starting data as first to nth received information bits with received parity and checksum bits with received parity to generate first to nth decoded information bits and decoded checksum bits; The first to nth information bits with reproduction parity and the checksum bit with reproduction parity are generated by performing the same error correction coding as the error correction coding on the thirty-nth decoding information bits and the decoding checksum bits. second encoder and, wherein the first receiving parity information bits first reproduction with parity information to First comparison of the bit, to the said n-th received parity information bits of the n comparison between the reproduced parity information bits of the n, and the reproduction parity check and the received parity checksum bits When the number of mismatch bits in the first to nth comparisons and the checksum comparison is less than or equal to a predetermined value, the received data string contains information bits addressed to the slave device. A data comparison circuit that is determined to include a bit operation circuit that creates a new data sequence in which only one “1” bit of the address bit is deleted from the received data sequence, and transmits the new data sequence to a slave device at the next stage; Comprising
A communication system characterized by the above.
The communication system according to any one of claims 6 to 9,
A communication system, wherein the error correction encoding and decoding are performed by a BCH code.

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