JP2000078028A - Rate decision circuit, decoding circuit and rate decision method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a rate decision circuit whose circuit scale is reduced and whose power consumption is reduced and to provide a decoding circuit. SOLUTION: Viterbi decoders 3-5 Viterbi-decode information rates that are set on reception data to a cut length (n), which is previously set, and encode it again by re-encoders 6-8. The encoding result is compared with reception data before decoding by a rate decision unit 9 and therefore the information rates are decided. A path metric at the time of decoding by the Viterbi decoders 3-5 is recorded in a path metric storage circuit 10. A Viterbi decoder 11 reads the path metric of the Viterbi decoder (one of 3-5) corresponding to the information rate which is decided by the rate decision unit 9 from the storage circuit 10 and Viterbi-decodes the information rate informed from the rate decision unit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rate determining circuit, a decoding circuit, and a rate determining method used in a variable rate communication system for performing communication by selectively using a plurality of transmission rates.

[0002]

2. Description of the Related Art A conventional decoding circuit in a variable rate communication system is shown in FIG. After a radio frequency signal from a communication partner station is received by a radio unit (not shown), it is converted into a digital signal and temporarily stored in the input buffer 1 as received data. The received data read from the input buffer 1 is output to the Viterbi decoders 30 to 50 and the rate determiner 9.

[0003] Viterbi decoders 30 to 50 perform Viterbi decoding on the received data according to preset information rates. Here, among the variable rates, the maximum number of bits per frame of the maximum rate is 200 bits, the Viterbi decoder 30 has a 200-bit rate, the Viterbi decoder 40 has a 100-bit rate, and the Viterbi decoder Reference numeral 50 denotes Viterbi decoding at a rate of 50 bits.

[0004] The decoding result of the received data decoded by the Viterbi decoder 30 is output to the re-encoder 6 and the output buffer 1.
2, the decoding result of the received data decoded by the Viterbi decoder 40 is sent to the re-encoder 7 and the output buffer 12, and the decoding result of the received data decoded by the Viterbi decoder 50 is sent to the re-encoder 8. And output buffer 12 respectively.

[0005] The re-encoders 6 to 8 perform convolution operations on the decoding results of the input received data, and re-encode them. Here, the received data re-encoded by the re-encoders 6 to 8 is output to the rate determiner 9.

The rate determinator 9 compares the received data re-encoded by the re-encoders 6 to 8 with the received data from the input buffer 1 before decoding, on a symbol-by-symbol basis. Is calculated.

The rate determiner 9 determines the information rate of the received data based on the normalized error rate and the CRC check bit data added in frame units. To the output buffer 12.

The output buffer 12 includes a Viterbi decoder 30 to
The data decoded by the Viterbi decoder (any one of 30 to 50) corresponding to the information rate notified from the rate determiner 9 among the data decoded at 50, respectively, is converted into a data reproduction unit (shown in the drawing). No) and play back to analog audio etc.

As described above, in the conventional decoding circuit, a plurality of Viterbi decoders 30 to 50 perform Viterbi decoding at a preset information rate, respectively, re-encode the decoding results, and receive the decoded data before decoding. By comparing with the data, the information rate of the received data is determined, and the decoding result of the Viterbi decoder corresponding to this information rate is output to the subsequent data reproducing unit.

The received data is coded by a convolution operation on the transmitting side, and has continuity between symbols. Therefore, as in the above-described decoding circuit, the Viterbi decoders 30 to
In order to provide a simplified hardware configuration for selectively outputting the decoding result of No. 50 from the output buffer 12, each of the Viterbi decoders 30 to 50 requires at least a Viterbi decoder in a frame unit serving as a break of continuity. It is necessary to perform decryption.

The Viterbi decoding method has a property that the processing amount (computation amount) and memory usage at the time of decoding increase exponentially as the constraint length of the convolutional encoder on the transmission side increases.

Therefore, a plurality of Viterbi decoders 30 to 50
And the conventional decoding circuit that performs decoding processing on a frame-by-frame basis in each case, has a problem that not only the circuit scale is large, but also the power consumption is large because the amount of calculation and memory used for decoding are large. .

Conventionally, in addition to the configuration in which a plurality of Viterbi decoders 30 to 50 perform decoding processing in parallel as described above, a configuration in which a single Viterbi decoder sequentially decodes a plurality of information rates. There is also a decoding circuit,
Even with such a configuration, the decoder needs to perform a decoding process for each frame in the decoding process for each information rate, and thus requires relatively large power.

[0014]

In a conventional decoding circuit,
There is a problem that the circuit scale is large and the power consumption is large. SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide a rate determination circuit and a decoding circuit capable of reducing a circuit scale and reducing power consumption. Another object of the present invention is to provide a rate determination method capable of reducing the circuit scale and power consumption.

[0015]

In order to achieve the above object, a rate determining circuit according to the present invention decodes received data up to a predetermined number of bits at different information rates. A plurality of decryption means;
A plurality of re-encoding means for encoding the decoding results of the corresponding decoding means, and comparing the received data with the data re-encoded by the plurality of re-encoding means, respectively, to determine an error rate. And a rate detecting means for detecting the information rate of the received data.

In the rate determination circuit having the above-described configuration, a plurality of decoding means decodes data at different information rates on received data up to a predetermined number of bits, and outputs the decoded result to a plurality of re-encoding means. Again. Then, the rate detecting means compares the received data with the data re-encoded by the plurality of re-encoding means, and obtains each error rate of the decoding result of the plurality of decoding means, thereby obtaining the received data. The information rate is detected.

Therefore, according to the rate determination circuit having the above configuration, the information rate of the received data is detected by decoding the received data up to a preset number of bits, re-encoding and comparing the decoded data with the received data. Therefore, the amount of processing required for decoding and encoding is small, the circuit scale can be reduced, and the power consumption can be reduced.

In order to achieve the above object, a decoding circuit according to the present invention comprises a plurality of first decoding units for respectively decoding received data up to a predetermined number of bits at different information rates. Means, a plurality of re-encoding means for encoding the decoding results of the corresponding first decoding means, respectively, the received data, and a comparison of the data re-encoded by the plurality of re-encoding means, A rate detecting means for detecting an information rate of the received data by obtaining an error rate; and a path metric for storing a path metric when the received data up to a predetermined number of bits is decoded by a plurality of first decoding means. Storage means, and a first decoding means which has performed decoding at the information rate detected by the rate detection means among the path metrics stored in the path metric storage means. And path metrics, based on the reception data after the number of bits set beforehand, the decoding of the received data, and to be configured and a second decoding means for performing an information rate detected by the rate detecting unit.

In the decoding circuit having the above-described configuration, the plurality of first decoding means perform decoding at different information rates on received data up to a predetermined number of bits, respectively.
The decoding result is re-encoded by a plurality of re-encoding means. Then, the rate detecting means compares the received data with the data re-encoded by the plurality of re-encoding means, respectively, and obtains each error rate of the decoding results of the plurality of first decoding means. Then, the second decoding unit decodes the received data based on the path metric of the first decoding unit that has performed decoding at the information rate detected by the rate detection unit and the received data of a predetermined number of bits or more. , At the information rate detected by the rate detecting means.

Therefore, according to the decoding circuit having the above structure, the information rate of the received data is detected by decoding the received data up to a predetermined number of bits, re-encoding and comparing the decoded data with the received data. As for decoding, since the received data is decoded based on the path metric when the detected information rate is decoded and the received data of a predetermined number of bits or more, the decoding and encoding are required. The amount of processing is small, the circuit scale can be reduced, and power consumption can be reduced.

In order to achieve the above object, a rate determining circuit according to the present invention includes a priority storage unit for storing a plurality of priorities of information rates and a priority stored in the priority storage unit. Decoding means for decoding the information rate according to the received data up to a predetermined number of bits, re-encoding means for encoding the decoding result of the decoding means, received data, and re-encoding means. A comparison means for comparing the coded data with the encoded data to determine an error rate, and an information rate of decoding performed by the decoding means when the error rate determined by the comparison means is equal to or less than a predetermined threshold value. And a determination means for detecting the information rate of the received data.

In the rate determination circuit having the above configuration, decoding of the information rate according to the priority order is performed on the received data up to a predetermined number of bits, and the decoding result is encoded again. Then, the received data is compared with the re-encoded data to determine an error rate. If the error rate is equal to or less than a preset threshold, the information rate of the decoding is detected as the information rate of the received data. I am trying to do it.

Therefore, according to the rate judgment circuit having the above configuration, decoding of the information rate according to the priority order is performed on the received data up to a predetermined number of bits, and then re-encoded and compared with the received data. By doing so, the information rate of the received data is detected, so that the amount of processing required for decoding and encoding is small, the circuit scale can be reduced, and the power consumption can be reduced.

Further, the present invention is characterized in that there is provided updating means for changing the priority stored in the priority storing means based on the information rate detected by the determining means. Therefore, according to the present invention, the priority of decoding according to the information rate is updated according to the detected information rate, so that the actual operation status is stored in the priority storage means. Will be reflected in the ranking,
The amount of processing up to the detection of the information rate can be reduced.

In order to achieve the above object, a decoding circuit according to the present invention follows priority storage means for storing priorities of a plurality of information rates and priority stored in the priority storage means. Decoding means for decoding the information rate for received data up to a predetermined number of bits, and path metric storage for storing a path metric when decoding the received data up to a predetermined number of bits by the decoding means Means, a re-encoding means for encoding the decoding result of the decoding means, a comparison means for comparing the received data with the data encoded by the re-encoding means to determine an error rate, Determining means for detecting an information rate of decoding performed by the decoding means as an information rate of received data when the error rate obtained in step (b) is equal to or less than a preset threshold value. The decoding means decodes the information rate based on the path metric stored in the path metric storage means and received data of a predetermined number of bits or more when the information rate is detected by the determination means. It is characterized by.

In the decoding circuit having the above configuration, decoding of the information rate according to the priority order is performed on the received data up to a predetermined number of bits, and the decoding result is encoded again. Then, the received data is compared with the re-encoded data to determine an error rate. If the error rate is equal to or less than a preset threshold, the information rate of the decoding is detected as the information rate of the received data. I do. And
The decoding means decodes the detected information rate based on the path metric stored in the path metric storage means and the received data of a predetermined number of bits or more.

Therefore, according to the decoding circuit having the above structure, the information rate of the received data is detected by decoding the received data up to a predetermined number of bits, re-encoding and comparing the decoded data with the received data. As for decoding, since the received data is decoded based on the path metric when the detected information rate is decoded and the received data of a predetermined number of bits or more, the decoding and encoding are required. The amount of processing is small, the circuit scale can be reduced, and power consumption can be reduced.

Further, the present invention is characterized in that there is provided updating means for changing the priority stored in the priority storing means based on the information rate detected by the determining means. Therefore, according to the present invention, the priority of decoding according to the information rate is updated according to the detected information rate, so that the actual operation status is stored in the priority storage means. Will be reflected in the ranking,
The amount of processing up to the detection of the information rate can be reduced, and decoding can be performed quickly.

Further, in order to achieve the above object, a rate determining method according to the present invention includes a first step of decoding received data up to a predetermined number of bits at a plurality of information rates; By comparing the received data with the data re-encoded in the second process, the second process for encoding the decoding result of the first process, respectively, and obtaining the error rate, And a third step for detecting the information rate of the information.

In the rate determination method having the above-described configuration, decoding at different information rates is performed on received data up to a predetermined number of bits, and these decoding results are encoded again. Then, the information rate of the received data is detected by comparing each of the plurality of re-encoded data with the received data and calculating the error rate of each decoding result.

Therefore, according to the rate determination method having the above configuration, the information rate of the received data is detected by decoding the received data up to a predetermined number of bits, re-encoding and comparing the decoded data with the received data. Therefore, the amount of processing required for decoding and encoding is small, the circuit scale can be reduced, and the power consumption can be reduced.

In order to achieve the above object, a rate determination method according to the present invention provides a method for decoding an information rate according to a preset priority among a plurality of information rates up to a predetermined number of bits. A first step performed on the received data, a second step for encoding the decoding result of the first step, and the received data are compared with the data encoded in the second step. A third step of obtaining an error rate, and detecting an information rate of decoding performed in the first step as an information rate of received data when the error rate obtained in the third step is equal to or less than a predetermined threshold value. Fourth
And the steps described above.

In the rate determination method having the above configuration, decoding of the information rate according to the priority order is performed on received data up to a predetermined number of bits, and the decoding result is encoded again. Then, the received data is compared with the re-encoded data to determine an error rate. If the error rate is equal to or less than a preset threshold, the information rate of the decoding is detected as the information rate of the received data. I am trying to do it.

Therefore, according to the rate determination method having the above-described configuration, decoding of the information rate according to the priority order is performed on the received data up to a predetermined number of bits, and then re-encoded and compared with the received data. By doing so, the information rate of the received data is detected, so that the amount of processing required for decoding and encoding is small, the circuit scale can be reduced, and the power consumption can be reduced.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a decoding circuit according to a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration. After a radio frequency signal from a communication partner station is received by a radio unit (not shown), it is converted into a digital signal and temporarily stored in the input buffer 1 as received data. And input buffer 1
The received data read out from the Viterbi decoders 3 to 5, 1
1 and output to the rate determiner 9.

The truncation length setting device 2 stores a preset truncation length n, and stores this value in the Viterbi decoders 3 to
5 is output. The truncation length n is set to, for example, 4 to 5 times the number of bits of the constraint length of the convolutional encoder on the transmission side or more.

The Viterbi decoders 3 to 5 respectively provide predetermined information to the reception data up to the cutoff length n notified from the cutoff length setting unit 2 among the reception data input from the input buffer 1. It performs Viterbi decoding according to the rate.

Here, as shown in FIG. 2, the number of bits per frame at the maximum rate among a plurality of information rates is 200 bits, and the Viterbi decoder 3
At the bit rate, the Viterbi decoder 4 performs Viterbi decoding at the rate of 100 bits, and the Viterbi decoder 5 performs Viterbi decoding at the rate of 50 bits. In this case, the constraint length of the convolutional encoder on the transmitting side is set to 7
It is assumed that 35 bits, which is five times as large, are set as the cutoff length n.

The 3D decoded by the Viterbi decoder 3
The decoding result of the received data of 5 bits (cutoff length) is sent to the re-encoder 6, the decoding result of the received data of 35 bits decoded by the Viterbi decoder 4 is sent to the re-encoder 7, and the Viterbi decoder 5 Are output to the re-encoder 8 respectively.

Each of the Viterbi decoders 3 to 5 has 3
The path metric when decoding the received data up to the fifth bit is output to the path metric storage circuit 10. On the other hand, the path metric storage circuit 10 stores the path metrics from the Viterbi decoders 3 to 5, respectively.

Each of the re-encoders 6 to 8 performs a convolution operation on the decoding result of the input received data and re-encodes them. Here, the received data re-encoded by the re-encoders 6 to 8 is output to the rate determiner 9.

The rate determinator 9 compares the received data re-encoded by the re-encoders 6 to 8 with the 35-bit received data from the input buffer 1 before decoding, on a symbol-by-symbol basis. Calculate the symbol error rate.

The rate determiner 9 determines the information rate of the received data based on the normalized error rate, and determines this information rate by the Viterbi decoder 11.
Notify.

Note that the rate checker 9 can use a CRC check bit added on a frame basis depending on the setting of the cutoff length. In this case, the data of the CRC check bit is also used to determine the information of the received data. Determine the rate.

When the information rate is notified from the rate determiner 9, the Viterbi decoder 11 reads out the path metric of the Viterbi decoder (any one of 3 to 5) corresponding to the information rate from the path metric storage circuit 10. . Then, Viterbi decoding of the information rate notified from the rate determination unit 9 is performed using the path metric and the reception data of the cutoff length n (= 35) or later among the reception data from the input buffer 1.

The data decoded by the Viterbi decoder 11 is temporarily stored in an output buffer 12 and then output to a data reproducing unit (not shown) at a subsequent stage to be reproduced as analog audio.

Next, the operation of the decoding circuit having the above configuration will be described below. Of the received data stored in the input buffer 1, data of a censoring length of 35 bits is transmitted to the Viterbi decoder 3.
, And Viterbi decoders 3 to 5 respectively perform Viterbi decoding according to a preset information rate. Here, the decoded 35-bit received data is re-encoded by the corresponding re-encoders 6 to 8 and output to the rate determination unit 9.

The path metrics obtained when decoding is performed by the Viterbi decoders 3 to 5 are respectively Viterbi decoders 3 to 5.
5 is output to the path metric storage circuit 10 and stored therein.

The rate determinator 9 compares the received data re-encoded by the re-encoders 6 to 8 with the received data from the input buffer 1 before decoding, on a symbol-by-symbol basis. Is calculated, and the information rate of the received data is determined from the result of normalizing these error rates (and, if the CRC check bit can be used, also). The information rate obtained by this determination is notified to the Viterbi decoder 11.

On the other hand, the Viterbi decoder 11 first reads out the path metric of the Viterbi decoder (any of 3 to 5) corresponding to the information rate notified from the rate determiner 9 from the path metric storage circuit 10. Then, using the path metric and the received data of the cutoff length n (= 35) or later among the received data from the input buffer 1, Viterbi decoding of the information rate notified from the rate determiner 9 is performed.

The data thus decoded is temporarily stored in the output buffer 12, and then output to a data reproducing unit (not shown) at the subsequent stage to be reproduced as analog audio.

As described above, in the decoding circuit having the above configuration,
For received data up to a preset cutoff length n,
Viterbi decoding and re-encoding for three information rates are performed, and the information rate is determined by comparing the received data before decoding.

For this reason, conventionally, the determination of the information rate requires a total of 350 bits of 200 bits, 100 bits, and 50 bits, whereas the decoding circuit of the above configuration has three times 35 bits. That is, the information rate can be determined by a 105-bit operation.

In the decoding circuit having the above configuration, the path metric of up to 35 bits decoded for determining the information rate is stored in the path metric storage circuit 10,
After determining the information rate, the Viterbi decoder 11 decodes the remaining received data using the path metric and the received data of the 35th bit and thereafter.

For this reason, conventionally, the decoding required 350 bits of operation irrespective of the information rate. In the decoding circuit having the above structure, the Viterbi decoder 11
At the minimum information rate, the remaining 15 bits of the 50 bits are calculated, and at the maximum information rate, the remaining 165 bits of the 200 bits are calculated. Therefore, the operation required for decoding is a total of 120 to 270 bits including the above 105 bits. Can be done with

Therefore, the decoding circuit having the above configuration can detect the information rate of the received data and decode the received data with a small amount of calculation, so that the power consumption required for these processes can be reduced.

Further, in the decoding circuit having the above configuration, decoding up to the cutoff length n is performed by the Viterbi decoders 3 to 5, and after the information rate is determined, decoding after the cutoff length n is performed by the Viterbi decoder 11. Therefore, decoding in frame units as in the prior art is performed by a plurality of Viterbi decoders 30 to 5.
The amount of memory used can be reduced as compared with the case where the processing is performed in parallel at 0.

Next, a decoding circuit according to a second embodiment of the present invention will be described. FIG. 3 shows the configuration. After a radio frequency signal from a communication partner station is received by a radio unit (not shown), it is converted into a digital signal and temporarily stored in the input buffer 21 as received data. Then, the received data read from the input buffer 21 is output to the Viterbi decoder 24 and the symbol comparator 26.

The truncation length setting unit 23 stores a preset truncation length n, and stores this value in the Viterbi decoder 2.
4 is output. Note that the truncation length n is set to be equal to or more than 4 to 5 times the number of bits of the constraint length of the convolutional encoder on the transmission side, for example, as in the first embodiment. Here, the constrained length of the convolutional encoder on the transmitting side is set to 7, and 5 times that of 3
It is assumed that 5 bits are set as the cutoff length n.

The Viterbi decoder 24 is provided with the input buffer 2
Viterbi decoding according to the information rate instructed by the control circuit 221 is performed on the received data up to the truncation length n (= 35) notified from the truncation length setting unit 23 out of the reception data input from 1. Things.

When decoding the received data of 35 bits, the Viterbi decoder 24 outputs the decoding result up to this point to the re-encoder 25 and holds the path metric so far.

Further, when the determination signal “1” is input from the rate determination unit 28 described later, the Viterbi decoder 24 outputs the held path metric and the cutoff length n of the reception data from the input buffer 21. Using the received data after (= 35), Viterbi decoding is restarted, and the decoding result is output to the output buffer 29.

The re-encoder 25 performs a convolution operation on the result of decoding the 35-bit received data by the Viterbi decoder 24, and encodes the result again. Here, the received data re-encoded by the re-encoder 25 is output to the symbol comparator 26.

The symbol comparator 26 compares the received data re-encoded by the re-encoder 25 with the 35-bit received data from the input buffer 21 before decoding, in symbol units, and calculates a symbol error rate. I do. This symbol error rate is reported to the rate determiner 28.

The rate determiner 28 is a symbol comparator 26
The symbol error rate notified by the threshold setting unit 2
7 is compared with the threshold value set. As a result of this comparison, if the symbol error rate exceeds the threshold,
"0" is output as a determination signal, and when the symbol error rate is equal to or less than the threshold, "1" is output as the determination signal.
Is output. This determination signal is output to the Viterbi decoder 24 and the control circuit 221.

The control section 22 comprises a control circuit 221 and a storage circuit 222. The control circuit 221 includes a rate setting unit 221a, a rate totalizing unit 221b, and a priority rate information updating unit 221c.
Consists of a priority rate information storage area 222a and a tally result storage area 222b.

As shown in FIG. 5, the priority rate information storage area 222a is an area for storing the priority order of information rates when decoding by the Viterbi decoder 24. This order is stored in a priority rate information updating means 221c described later. Will be updated by

As shown in FIG. 6, the count result storage area 222b is an area for storing information on the number of information rates used when decoding is performed by the decoding circuit. It is counted by the means 221b.

The rate setting means 221a, in accordance with the priority rate information stored in the priority rate information storage area 222a, responds to the determination signal notified from the rate determination unit 28 by using 200-bit, 100-bit, and 50-bit information. The rate is sequentially instructed to the Viterbi decoder 24.

The rate summing means 221b monitors the judgment signal sent from the rate judging unit 28, and when "1" is sent through this judgment signal, that is, when the symbol error rate is equal to or less than the threshold, the Viterbi decoding is performed. Result storage area 222 corresponding to the information rate (assigned by rate setting means 221a) used by decoding unit 24 for decoding.
"1" is added to the number of uses of b.

The priority rate information updating means 221c determines the priority order based on the information stored in the counting result storage area 222b of the storage circuit 222 so as to give priority to the information rate with a large number of uses, and determines this priority order. It is recorded in the priority rate information storage area 222a.

Next, the operation of the decoding circuit having the above configuration will be described below. FIG. 4 is a flowchart for explaining this operation. First, in step 4a, the rate setting means 221a refers to the priority rate information stored in the priority rate information storage area 222a,
Among the information rates of 00 bits and 50 bits, the information rate having a higher priority is notified to the Viterbi decoder 24, and the process proceeds to step 4b.

In step 4b, the Viterbi decoder 24
Of the received data stored in the input buffer 21, the received data corresponding to the truncation length of 35 bits is read out and Viterbi decoding is performed in step 4a according to the information rate specified by the rate setting means 221a. Here, the Viterbi decoder 24 holds the path metric when decoding the 35-bit received data. Then, control goes to a step 4c.

At step 4c, the re-encoder 25 re-encodes the 35-bit received data decoded at step 4b, outputs this encoded result to the symbol comparator 26, and proceeds to step 4d.

In step 4d, the symbol comparator 26
Calculates the symbol error rate by comparing the received data re-encoded by the re-encoder 25 with the received data from the input buffer 21 before decoding, on a symbol-by-symbol basis. This symbol error rate is notified to the rate determiner 28, and the process proceeds to step 4e.

In step 4 e, the rate determiner 28 compares the symbol error rate notified from the symbol comparator 26 with a threshold set by the threshold setter 27. As a result of this comparison, if the symbol error rate is equal to or less than the threshold value, that is, at step 4a,
If the information rate notified by 21a to Viterbi decoder 24 is appropriate, rate determiner 28 outputs “1” as a determination signal to Viterbi decoder 24 and control circuit 221, and proceeds to step 4f. I do. On the other hand, if the symbol error rate exceeds the threshold, that is, if the information rate notified by the rate setting means 221a to the Viterbi decoder 24 in step 4a is inappropriate,
8 outputs “0” as a determination signal to the Viterbi decoder 24 and the control circuit 221, and proceeds to step 4i.

In step 4f, the Viterbi decoder 24
Out of the received data from the input buffer 21, the censoring length n
The received data after (= 35) is read out, and Viterbi decoding is resumed using the stored path metric. The decoded received signal is output to the output buffer 29, and the process proceeds to step 4g.

In step 4g, since the judgment signal "1" is notified from the rate judgment unit 28, the rate summation unit 22
1b adds “1” to the number of uses of the tally result storage area 222b corresponding to the information rate used by the Viterbi decoder 24 for decoding, and proceeds to step 4h.

At step 4h, the priority rate information updating means 221c reads the total result storage area 2 of the storage circuit 222.
Based on the information stored in 22b, a priority is determined so that an information rate with a large number of uses is prioritized, and this priority is recorded in a priority rate information storage area 222a.
Update that ranking.

Further, in the decoding circuit having the above configuration, a path metric of up to 35 bits decoded for information rate determination is held, and after the information rate determination, an appropriate information rate decoding is performed. The Viterbi decoder 11 decodes the remaining received data using the path metric and the received data of the 35th bit and thereafter.

For this reason, conventionally, decoding has been performed in a minimum of 5
The decoding circuit of the above configuration can perform decoding by an operation of a minimum of 50 bits and a maximum of 270 bits, whereas the operation of 0 bits and a maximum of 350 operations are required.

Therefore, the decoding circuit having the above-described configuration can detect the information rate of the received data and decode the received data with a small amount of calculation, so that the power consumption required for these processes can be reduced.

Further, in the decoding circuit having the above configuration, the information rate is determined based on the priorities based on the information rates used in the past, so that learning according to the user is performed, and unnecessary learning is performed. The number of operations can be reduced.

The present invention is not limited to the above embodiment. It goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0085]

As described above, in the rate determination circuit and the decoding circuit according to the present invention, the decoding at different information rates is performed by a plurality of decoding means on received data up to a predetermined number of bits. Then, the decoding result is re-encoded by a plurality of re-encoding means. Then, the rate detecting means compares the received data with the data re-encoded by the plurality of re-encoding means,
The information rate of the received data is detected by obtaining each error rate of the decoding results of the plurality of decoding means.

Therefore, according to the present invention, the information rate of the received data is detected by decoding the received data up to a predetermined number of bits, re-encoding and comparing the decoded data with the received data. A rate determination circuit and a decoding circuit that require a small amount of processing for encoding, can reduce the circuit scale, and can reduce power consumption can be provided.

Further, in the rate determination circuit and the decoding circuit according to the present invention, decoding of the information rate according to the priority is performed on the received data up to a predetermined number of bits, and the decoding result is encoded again. . Then, the received data is compared with the re-encoded data to determine an error rate. If the error rate is equal to or less than a preset threshold, the information rate of the decoding is detected as the information rate of the received data. I am trying to do it.

Therefore, according to the present invention, decoding of the information rate according to the priority order is performed on received data up to a predetermined number of bits, and then re-encoded and compared with the received data. Since the information rate of the received data is detected, it is possible to provide a rate determination circuit and a decoding circuit capable of reducing the amount of processing required for decoding and encoding, reducing the circuit scale, and reducing power consumption.

Further, in the rate determination method according to the present invention, decoding at different information rates is performed on received data up to a predetermined number of bits, and these decoding results are encoded again. Then, the information rate of the received data is detected by comparing each of the plurality of re-encoded data with the received data and calculating the error rate of each decoding result.

Thus, according to the present invention, the information rate of the received data is detected by decoding the received data up to a predetermined number of bits, re-encoding and comparing the decoded data with the received data. It is possible to provide a rate determination method capable of reducing the amount of processing required for encoding, reducing the circuit scale, and reducing power consumption.

Further, in the rate determination method according to the present invention, decoding of the information rate according to the priority order is performed on received data up to a predetermined number of bits, and the decoding result is encoded again. And the received data,
An error rate is obtained by comparing the re-encoded data, and when the error rate is equal to or less than a preset threshold, the information rate of the decoding is detected as the information rate of the received data.

Therefore, according to the present invention, decoding of the information rate according to the priority order is performed on received data up to a predetermined number of bits, and then re-encoded and compared with the received data. Since the information rate of the received data is detected, it is possible to provide a rate determination method capable of reducing the amount of processing required for decoding and encoding, reducing the circuit scale, and reducing power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a first embodiment of a decoding circuit according to the present invention.

FIG. 2 shows the number of bits per frame and the cutoff length n.
FIG.

FIG. 3 is a circuit block diagram showing a configuration of a decoding circuit according to a second embodiment of the present invention;

FIG. 4 is a flowchart for explaining the operation of the decoding circuit shown in FIG. 3;

FIG. 5 is a view showing priority order information stored in a priority rate information storage area 222a of the decoding circuit shown in FIG. 3;

6 is a tally result storage area 2 of the decoding circuit shown in FIG.
The figure which shows the use number information stored in 22b.

FIG. 7 is a circuit block diagram showing a configuration of a conventional decoding circuit.

[Explanation of symbols]

 1, 21 ... input buffer 2, 23 ... truncation length setting device 3-5, 11, 24 ... Viterbi decoder 6-8, 25 ... re-encoder 9, 28 ... rate judgment device 10 ... path metric storage circuit 12, 29 output buffer 22 control unit 221 control circuit 221a rate setting unit 221b rate totaling unit 221c priority rate information updating unit 222 storage circuit 222a priority rate information storage area 222b totaling result storage area 26 symbol comparison Unit 27: threshold setting unit

Claims (8)

[Claims] 1. A plurality of decoding means for respectively decoding received data up to a predetermined number of bits at different information rates, and a plurality of re-encoding means for respectively decoding the decoding results of the corresponding decoding means. Rate detection means for detecting the information rate of the received data by comparing the received data with the data re-encoded by the plurality of re-encoding means to determine an error rate. And a rate determination circuit. 2. A plurality of first decoding means for respectively decoding received data up to a predetermined number of bits at different information rates, and a decoding result of the corresponding first decoding means is encoded. A plurality of re-encoding units, and the received data and the data re-encoded by the plurality of re-encoding units are respectively compared to determine an error rate, thereby detecting an information rate of the received data. A rate metric detecting means, a path metric storing means for storing a path metric when the plurality of first decoding means decode received data up to a predetermined number of bits, and a path metric storing means for storing the path metric. Of the path metrics, the path metric of the first decoding unit that has performed decoding at the information rate detected by the rate detection unit, and the preset path metric Tsu based on the betting amount after the received data, the decoding of the received data, decoding circuit, characterized in that it comprises a second decoding means for performing an information rate detected by the rate detecting unit. 3. A priority storage means for storing priorities of a plurality of information rates, and decoding of an information rate in accordance with the priorities stored in the priority storage means, for receiving data up to a predetermined number of bits. A re-encoding unit for encoding the decoding result of the decoding unit; comparing the received data with the data encoded by the re-encoding unit to determine an error rate. Determining means for determining, when the error rate determined by the comparing means is equal to or less than a preset threshold, an information rate of decoding performed by the decoding means as an information rate of the received data. A rate determination circuit. 4. An apparatus according to claim 3, further comprising updating means for changing a priority stored in said priority storage based on an information rate detected by said determining means.
3. The rate determination circuit according to 1. 5. A priority storage means for storing priorities of a plurality of information rates, and decoding of an information rate in accordance with the priorities stored in the priority storage means, the decoding of received data up to a predetermined number of bits. Decoding means for decoding received data up to a predetermined number of bits by the decoding means, path metric storage means for storing a path metric when decoding the received data, and re-encoding for decoding the decoding result of the decoding means Comparing means for comparing the received data with the data coded by the re-encoding means to obtain an error rate, wherein the error rate obtained by the comparing means is equal to or less than a predetermined threshold value. And determining means for detecting an information rate of decoding performed by the decoding means as an information rate of the received data, wherein the decoding means Decoding the information rate based on a path metric stored in the path metric storage means and received data of the predetermined number of bits or more. circuit. 6. An updating means for changing a priority stored in said priority storage based on an information rate detected by said determining means.
3. The decoding circuit according to 1. 7. A first step of decoding received data up to a predetermined number of bits at a plurality of information rates, and a second step of encoding a decoding result of the first step. A third step of detecting the information rate of the received data by comparing the received data with the data re-encoded in the second step to determine an error rate. A rate determination method characterized by the following. 8. A first step of decoding an information rate according to a preset priority among a plurality of information rates for received data up to a preset number of bits; A second step of encoding a decoding result of the step; a third step of comparing the received data with the data encoded in the second step to determine an error rate; A fourth step of detecting, as an information rate of the received data, an information rate of the decoding performed in the first step when an error rate obtained in the step is equal to or less than a preset threshold value. Rate determination method.