KR102235290B1 - Host and slave apparatus having cascade connection structure - Google Patents

Abstract

The device according to the present technology includes ports for input and output of chip select signals, serial clock input and output, and serial data input and output, respectively, and a plurality of slaves and chip select signals that are cascaded to each other including registers and output. It includes a host that forms and outputs a serial clock and forms and outputs serial data.Serial data includes an assign byte that controls the slave, an address byte of the register included in the slave, and a register. Contains data bytes to be stored in.

Description

Host and slave device in cascade connection structure {HOST AND SLAVE APPARATUS HAVING CASCADE CONNECTION STRUCTURE}

The present technology relates to a host and slave device in a cascade connection structure.

There may be several methods of controlling by connecting a plurality of slave modules to one host. For example, in order to control a plurality of slave devices that the host wants to control, a dedicated input/output port may be provided for each slave device to perform control signal, data, and clock communication between the host and the slave devices.

When one host wants to control a plurality of slave devices, input/output ports are required as many as the number of slave devices to be controlled, and a host having a large-scale computing capability is required to independently control communication with each slave device.

According to the prior art, input/output ports are required as many as the number of slave devices to be controlled by a host, and it is uneconomical because a lot of cost is consumed to form them. In addition, an expensive high-performance computing device is required in order to control communication independently performed in each port.

The present technology is one of the technical problems to be solved by the present technology to provide a host and slave device having a cascade connection structure in order to overcome the difficulties of the prior art.

The device according to the present embodiment includes ports for input and output of a chip select signal, serial clock input and output, and serial data signal input and output, respectively, and a plurality of slaves cascaded to each other and a plurality of cascades connected to each other. It includes a host connected to the first stage of the slaves of the device to form and output a chip select signal, a serial clock and a serial data signal.The serial data signal includes an assign byte that controls the slave and a register included in the slave. And a data byte to be read from or written to the register.

According to an aspect of the present technology, a plurality of slaves cascaded to each other are each enabled by a chip select signal output from the previous stage, receive a serial clock output from the previous stage, and sample serial data. .

According to an aspect of the present technology, a plurality of slaves cascaded to each other each receive a chip select signal, activate a next stage after 8 clocks, and output a serial clock and a serial data signal.

According to an aspect of the present technology, the setting byte is a read/write setting bit for controlling data writing and reading of the slave, and a packet for setting the slave operation mode or a target slave among a plurality of slaves. It includes processing bits and an increase/decrease setting bit for setting a packet processing bit to decrease or increase as data is propagated through a plurality of slaves connected in a cascade.

According to one aspect of the present technology, the host sets the increase/decrease setting bit so that the packet processing bit decreases as data propagates through each slave connected in a cascade, and as the packet processing bit decreases, a preset value in the target slave is set. It is set to be possible, and a read/write setting bit is set to perform data writing or reading in the target slave.

According to an aspect of the present technology, a host outputs an address of a register to perform data writing or reading through an address byte, and outputs data to be written as a data byte.

According to an aspect of the present technology, a host sets and outputs a setting byte so that a plurality of slaves connected in a cascade write the same data.

According to an aspect of the present technology, a host outputs an address of a register to be written data through an address byte, and outputs data to be written as a data byte.

According to one aspect of the present technology, the slave is a controller that controls a digital signage.

According to the present invention, since a host and a plurality of slaves are connected in a cascade to each other, there is no need for input/output ports as many as the number of slaves, thereby providing economical effects. In addition, according to the present invention, since the slaves can be controlled with a setting byte, an expensive operation device is not required, thereby providing an advantage of being economical.

1 is a block diagram showing an outline of the present invention.
2 is a schematic timing diagram showing an outline of signals input to input ports from a slave and signals output to output ports.
3 is a schematic diagram showing a schematic structure of serial data (SDA).
4 to 6 are diagrams for explaining the operation of the present invention.

Hereinafter, the present invention will be described with reference to the accompanying drawings. In describing the present invention, a single line and a bus are not distinguished for concise description and easy understanding.

For each of the same or similar plurality of components, symbols such as a, b, and c are added. When a description of any one of these is required, a code may be added to describe it, and when a description of a specific one is unnecessary, the code may be removed and described.

1 is a block diagram showing an outline of the present invention. Referring to FIG. 1, the present invention provides a port for each chip select signal input (CS_IN) and output (CS_OUT), serial clock input (SCL_IN) and output (SCL_OUT), and serial data input (SDA_IN) and output (SDA_OUT). , Connected to the first stage of a plurality of slaves 200a, 200b, ... 200f connected in a cascade to each other and a plurality of slaves 200a, 200b, ... 200f connected in a cascade including a register (not shown) And a host 100 that forms and outputs a chip select signal CS, a serial clock SCL and serial data SDA, and the serial data SDA includes an assign byte for controlling the slave and , An address byte of a register included in the slave and a data byte to be stored in the register.

The host 100 forms a chip select signal (CS), a serial clock signal (SCL), and a serial data signal (SDA) to form a chip select signal output port (CS_OUT), a serial clock output port (SCL_OUT), and a serial data output port, respectively. Output to (SDA_OUT). The host 100 may include a processor (not shown) for signal formation and a memory (memory) for storing necessary data.

A plurality of slaves 200a, 200b, ... 200f are connected in a cascade, and chip select signal (SC), serial clock signal (SCL) and serial data (SDA) signal are provided from the slave of the previous stage. It receives, performs the necessary signal processing, and provides it to the slave of the next stage.

For example, among slaves connected in cascade, the slave 200a of the first stage may receive a signal from the host 100, and the slave 200f of the last stage may output the signal to the host 100.

Each of the slaves may include a processor for signal processing and may include a register for storing data. In one embodiment, data stored by each slave may be 8 bits, and may be input or output through a data byte included in the serial data signal SDA. The address of the register included in each slave may be 8 bits, and the register may be accessed through an address byte included in the serial data signal SDA.

In the embodiment illustrated in FIG. 1, each of the slaves may be a controller that controls a digital signage 300, and the host 100 includes content such as images and videos to be displayed on a digital signage 300. Can be provided by the user. The host 100 may perform an operation such as processing the provided content and providing the divided content for each controller.

2 is a schematic timing diagram showing an overview of signals input to input ports CS_IN, SCL_IN, and SDA_IN from any one slave 200 and signals output to output ports CS_OUT, SCL_OUT, SDA_OUT . Referring to FIG. 2, a chip select signal CS is provided to enable a corresponding slave 200. According to the illustrated embodiment, when the chip select signal CS transitions to a logic low state, the slave 200 is activated. According to an embodiment not shown, when the chip select signal CS transitions to a logic high state, the slave 200 may be activated.

The slave 200 provided with the signal may sample the serial data SDA provided from the previous stage as a serial clock signal SCL and perform an operation corresponding to the sampled serial data SDA.

When a chip select signal CS, a serial clock signal SCL, and a serial data signal SDA are provided to the slave 200, the slave performs processing according to the provided information and delays by a delay time of 8 clocks. Output to the stage.

3 is a schematic diagram showing a schematic structure of serial data (SDA). Referring to FIG. 3, the serial data SDA may include a plurality of bytes including an assign byte, an address byte, and a data byte. The address byte may be 8 bits of data of [A7:A0], and is data corresponding to an address of a register included in the slave. The data byte may be 8-bit data of [D7:D0], and may be data to be read from a register of a corresponding address or to be written to a register of a corresponding address.

The assign byte may include an increase/decrease setting bit (DU), a read/write setting bit (RW), and packet processing bits of S[5:0]. The slave 200 controls the output of the packet processing bits S[5:0] to increase or decrease according to the increase/decrease setting bit DU. For example, when the increase/decrease setting bit DU is input to the slave in a logic low state, the corresponding slave 200 may decrease the packet processing bit by 1 and output it. As another example, when the increase/decrease setting bit DU is input to the slave 200 in a logic high state, the corresponding slave 200 may increase the packet processing bit by 1 and output it.

The slave 200 reads/writes an input command according to a read/write setting bit RW. For example, if the read/write setting bit RW input to the slave 200 is logic high, the slave 200 may write data provided as a data byte to a register of an address provided as an address byte. As another example, if the read/write setting bit RW input to the slave 200 is a logic low, the slave 200 may read data from a register of an address provided as an address byte and output it as a data byte.

The slave 200 processes the input packet according to the input packet processing bits S[5:0]. In one embodiment, if S[5:0] = 111111 (0x3F) provided to the slave 200 and the read/write setting bit is logic high, the same data is written to all the slaves 200. In addition, the slave 200 maintains and outputs the packet setting bits S[5:0] as 111111 (0x3F).

In another embodiment, if the packet processing bits S[5:0] provided to the slave 200 are any one of 101111(0x2F) to 000001(0x01), the packet processing bits S[ input according to the increment/decrement setting bits 5:0] is output by increasing or decreasing by 1 according to the increase/decrease setting bit (DU).

In another embodiment, if S[5:0] provided to the slave 200 is 000000 (0x00) and the read/write setting bit is logical high, the data provided as data bytes is written to the register designated as the address byte, and Output the data. The slave 200 outputs 000001 (0x01) as packet setting bits [5:0], an increase/decrease setting bit (DU) is a logic high, and a read/write setting bit is a logic low.

Further, if the read/write setting bit is a logical low, data is read from a register designated as an address byte, and the read data is provided as a data byte and output. The slave 200 outputs 000001 (0x01) as a packet setting bit [5:0], a logic high for an increase/decrease setting bit DU, and a logic high for a read/write setting bit.

4 is a diagram for describing a case in which the same data is written to all slaves 200. The content displayed adjacent to the signal line in FIG. 4 schematically describes the content of the signal transmitted through the serial data (SDA). Referring to FIG. 4, the host 100 does not care about the state of the increase/decrease control bit DU, the read/write setting bit RW is logic high, and packet processing bits S[5:0] 111111(0x3F) is outputted.

Logic high is provided as read/write setting bits (RW), and packet processing bits S[5:0] are 111111 (0x3F), so packet processing bits S[5:0] are also output as 111111 (0x3F). . Accordingly, data provided as data bytes is written to the registers corresponding to the address bytes of all the slaves 200a, 200b, ..., 200f connected in a cascade (Register write).

5 is a diagram for explaining a case of writing data to a specific slave 200c. As an example, it is assumed that the host 100 writes data to the third slave 200c among a plurality of slaves 200a, 200b, ..., 200f connected in a cascade. The host outputs a logic low as an increase/decrease setting bit (DU), a logic high as a read/write setting bit (RW), and 000010 (0x02) as a packet processing bit S[5:0].

The slave 200a receives the packet setting bit S[5:0] 000010 (0x02), the increase/decrease setting bit of the logic low and the read/write setting bit (RW) of the logic high, and sets the packet setting bit S[5:0]. The reduced by 1 000001 (0x01), an increase/decrease setting bit of a logic low, and a read/write setting bit of a logic high (RW) are output to the slave 200b.

The slave 200b receives the packet setting bit S[5:0] 000001 (0x01), the increase/decrease setting bit of the logic low, and the read/write setting bit (RW) of the logic high, and sets the packet setting bit S[5:0]. The reduced 000000 (0x00), the increase/decrease setting bit of the logic low, and the read/write setting bit RW of the logic high are output to the slave 200c.

Since the slave 200c is provided with packet setting bits S[5:0] 000000 (0x00) and logical high read/write setting bits (RW), the data provided as data bytes is written to the register of the address provided as the address byte. And outputs the written data as data bytes. The slave 200c converts the increase/decrease setting bit to logic high and outputs it by setting the packet setting bit S[5:0] 000001 (0x01).

Since the packet setting bit S[5:0] 000001 (0x01) and the logical high increase/decrease setting bit are input to the slave (200d), the packet setting bit S[5:0] that has been increased by 1 is changed to 000010 (0x02) and the logical high state. The increase/decrease setting bit is output to the slave 200e. Through this process, the slave 200f outputs 000100 (0x04) to the host 100 as packet setting bits S[5:0], an increase/decrease setting bit (DU) in a logic high state, and a read/write setting bit.

As illustrated above, the host 100 can write data to a target slave by adjusting the value of the packet setting bit S[5:0] and the increase/decrease setting bit (DU) value, and the received packet setting bit S[ 5:0] and the increase/decrease setting bit (DU) value, it is possible to determine whether the target data has been successfully written to the target slave.

6 is a diagram for explaining a case where data is read from a specific slave 200d. As an example, it is assumed that the host 100 reads data from the fourth slave 200d among a plurality of slaves 200a, 200b, ..., 200f connected in a cascade. The host outputs a logic row as an increase/decrease setting bit (DU), a logic row as a read/write setting bit (RW), and 000011 (0x03) as packet processing bits S[5:0].

Since the increase/decrease setting bit of the logic row is provided to the slave (200a), slave (200b) and slave (200c), the packet setting bit S[5:0] 000011 (0x03) output from the previous stage is decreased by 1, respectively, to the next stage. Output to the slave of. Accordingly, the slave 200d is provided with an increase/decrease setting bit of a logic row, a read/write setting bit (RW) of a logical row, and a packet setting bit S[5:0] of 000000 (0x00).

The slave 200d reads data from a register of an address provided as an address byte and outputs data provided as a data byte. In addition, the slave 200d converts the increase/decrease setting bit to logical high and outputs it by setting the packet setting bit S[5:0] 000001 (0x01).

Since the packet setting bit S[5:0] 000010 (0x02) and the logical high increase/decrease setting bit are input to the slave 200e, the packet setting bit S[5] by increasing the input packet setting bit S[5:0] by one. :0] and the increase/decrease setting bit of the logic high state are output.

Through this process, the slave 200f transmits 000011 (0x03) to the host 100 as the packet setting bit S[5:0], the increase/decrease setting bit (DU) of the logic high state, and the read/write setting bit of the logic low. Print it out.

As described above, the host 100 may read data from a target slave by adjusting the value of the packet setting bit S[5:0] and the value of the increase/decrease setting bit (DU).

100: host
200a, 200b, 200c, 200d, 200e, 200f: slave
300a, 300b, 300c, 300d, 300e, 300f: digital signage
CS: Chip select signal
SCL: serial clock
SDA: serial data signal

Claims (9)

Ports for input and output of each chip select signal, serial clock input and output, and serial data signal input and output, and a plurality of slaves including registers and cascaded to each other, and
A host connected to the first stage of the plurality of slaves connected by the cascade to form and output the chip select signal, the serial clock and the serial data signal,
The serial data signal is
An assign byte that controls the slave,
An address byte of a register included in the slave, and
A data byte to be read from or written to the register,
The assignment byte is,
A read/write setting bit for controlling data writing and reading of the slave,
Packet processing bits for setting an operation mode of the slave or a target slave among the plurality of slaves, and
And an increase/decrease setting bit configured to decrease or increase the packet processing bit as data propagates through the plurality of slaves connected in the cascade,
The host,
Set the increase/decrease setting bit so that the packet processing bit decreases as data propagates through each slave connected in the cascade,
As the packet processing bit decreases, it is set to be a preset value in the target slave,
And setting the read/write setting bit to perform data writing or reading in the target slave. The method of claim 1,
Each of the plurality of slaves cascaded to each other,
It is activated by the chip select signal output from the previous stage,
A device that receives the serial clock output from the previous stage and samples the serial data. The method of claim 2,
Each of the plurality of slaves cascaded to each other
After 8 clocks after receiving the chip select signal,
A device that activates the next stage and outputs a serial clock and serial data signal. delete delete The method of claim 1,
The host is
Output the address of the register to perform data writing or reading through the address byte,
An apparatus for outputting data to be written in the data bytes. The method of claim 1,
The host is
An apparatus for setting and outputting the setting byte so that a plurality of slaves connected in the cascade write the same data. The method of claim 7,
The host outputs the address of the register to perform data writing through the address byte,
A device that outputs data to be written in the data byte. The method of claim 1,
The slave device is a controller that controls a digital signage.

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