JPS62208493A - Fifo write control circuit - Google Patents

Abstract

PURPOSE:To form an FIFO register with less hardware by providing a control means that activates the continuous writing of data to a data register when the number of stages including data in the data register attains a set value. CONSTITUTION:An FIFO write circuit 5 writes data with an m-bit width in a clock A from the data register 2, while an FIFO read circuit 5 reads data with an m-bit width in a clock B out of the data register 1. It is assumed that a clock C is required for the FIFO write circuit 4 to write data after an FIFO write ready signal 9 becomes active. Here a minimum integer among (x) satisfying the inequality An+C>B(n-x) is l. Data is sequentially read out of the FIFO register 1 at a constant speed, and remaining effective data in the FIFO register 1 is sequentially shifted at the read end, and the FIFO write ready signal 9 is made active at the time when l-staged effective data disappears in the write end. Then the FIFO write circuit 4 can continuously write n-pieces of data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a FIFO type data input/output device, and
This relates to an IFOf-inclusive control circuit.

[Conventional technology]

Conventionally, in this type of FIFO type input/output device, when there is no valid data at the write end of the FIFO register, the external circuit (F
A method has been used in which a write ready signal is sent to IFO write circuit) K, and after the external circuit detects that this write ready signal is active, it writes to the FIFO register.

FIG. 2 is a block diagram of a conventional example of this FIFO type input/output device. FIFO register 1 holds data with double-stage data register 2 and data register 2 with a door bit width.
It is composed of a use bit register 3 that holds a rubit use bit with a width of 1 pit corresponding to each stage.

FIFO read circuit 5 reads data from FIFO register 1 at regular time intervals. When data is written from the FIFO write circuit 4 to the write end of the data register 2, the data is sequentially shifted in the data register 2 to the read end side. Each stage of the use bit register 3 becomes active when each stage of the corresponding data register 2 holds a valid register, and becomes inactive when it holds no data. The FIFO write ready signal 6 becomes active when one bit on the write end side of the use bit register 3 is inactive, and the FIFO write ready signal 6 becomes active.
K Indicates that FIFO register 1 is ready for writing.

The FIFO write circuit 4 receives the FIFO write ready signal 6.
When detecting that the register 2 is active, m-bit width data is written to the data register 2. However, with this method, the data bus is occupied each time the FIFO write circuit 4 writes data to the data register 2 one by one in response to the FIFO write ready signal 6, so when writing a large amount of data, there is an overhead to the host system. or the data bus usage efficiency decreases. In order to deal with this problem, there is a method in which the FIFO write circuit 4 writes data to the data register 2 several times in succession. This activates the FIFO write ready signal 6 when all registers of the use pit register 3 are inactive,
This starts writing data into the FIFO write circuit 4 consecutively. In this case, in order to prevent an under/under due to reading by the PIFOM output circuit 5, the data register 2 must be composed of one or more stages of data registers.

[Problem that the invention seeks to solve]

Using the FIFO write ready signal 6 mentioned above,
A conventional FIFO input/output device that writes one data item at a time to the O register 1 has the disadvantage that when writing a large amount of data, each data item occupies the system bus, which imposes overhead on the host system. Also, FIF
In the conventional FIFO type data input/output device, which writes to the FIFO register 1 continuously by the O write ready signal 6, if the write speed of the FIFO write circuit 4 is much faster than the read speed of the FIFO read circuit 5, If valid, but the FIFO write speed is not significantly different from the FIFO read, then at the output of FIFO register 1,
In order to prevent an underrun due to data reading, the data register 2 must be configured to have several stages more than the number of n pieces of data that are continuously written at one time.

[Means for solving problems]

The FIFO # write control circuit of the present invention includes a setting means for setting the number of stages in which valid data exists in the data register to a value that does not cause an underrun due to data reading when data is continuously written; It has a control means for activating continuous writing of data to the data register when the number of stages in which data exists in the register reaches the set value.

Controls the activation timing so that continuous data writing starts when the data held in the data register is read and the number of stages in which valid data exists reaches a preset value to prevent underruns caused by data reading. By doing so, continuous writing without underrun is possible, and thereby the data register can be used effectively and the FIFO register can be realized with a small amount of hardware.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an FIFO having a FIFO write control circuit according to the present invention.
FIG. 2 is a block diagram of an embodiment of a Foffl data input/output device.

This embodiment is obtained by adding a mask pit register and a write ready signal control circuit 8 to the conventional example shown in FIG.

The mask pit register 7 in the next stage has a width of 1 bit, and holds 1 mask pits, each of which is connected to the use bit register 3.
It corresponds to each use pit. The mask pit register 7 controls the timing of activating the FIFO-fJ' write ready signal 6 sent to the FIFO write circuit 4. The write ready signal control circuit 8 reads the contents of the use bit register 3 and the mask pit register 7, and uses the phase of the AND of the corresponding registers to write the FIF signal.
O write ready signal 6? make.

The FIFO write circuit 4 can write m-bit data to the data register 2 at a rate of once per A [clock], and the FIFO read circuit 5 can write m-bit data once per B [clock]. Suppose that width data is read from data register 1. Also, after the FIFO write ready signal 9 becomes active, the PIFO! It is assumed that it takes C [clocks] for the circuit 4 to write the data.

Here, the smallest integer in X that satisfies ATL + C > B (rL-x)! shall be. Data is read from the successive end of FIFO register 1 at a constant speed, and
When the valid data remaining in the buffer is sequentially shifted to the read end side and the FIFO write ready signal 9 is activated when the two-stage valid data disappears from the write end, the FIFO write circuit 4 is activated by the following operation. can write n pieces of data consecutively. In other words, it is the number of data to be shifted in advance from the write end side of the rubits of the mask pit register 7 until writing starts! Set the bit to 1, and set the remaining n-1 bits to 0. While the FIFO read circuit 5 is reading data from the FIFO register 1, the write ready signal control circuit 8 constantly detects the values of the use pits in each stage and the mask pits corresponding thereto. When the sum of the ANDs of the use pits and mask bits for all stages of the FIFO is OK, the write ready signal control circuit 8 activates the FIFO write ready signal 6 and causes the FIFO write circuit 4 to write the FIFO
Indicates that there is no valid data in register 1. As a result of the above operation, the PIFOf write circuit 4 is activated when there is no valid data in the first stage from the FIFO write end
It is determined that no valid data exists in IFOtc &, and nine pieces of data can be sequentially written. At this time, FI
Since data is read from the FO at a constant speed, overrun due to data writing does not occur, and continuous writing of several pieces of data to the FIFO register 1 can be realized with one stage of data register 2.

〔Effect of the invention〕

As explained above, the present invention effectively uses the data register by controlling the data write request signal according to the data input/output transfer rate of the FIFO type input/output device, thereby realizing the FIFO register with less hardware. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a FIFO type data input/output device having an embodiment of the FIFO write control circuit of the present invention, and FIG.
The figure is a block diagram of a conventional example of a FIFO input/output device. 1... FIFO register, 2... Data register, 3... Use pit register, 4...
FIFO write circuit, 5... FIFO read circuit, 6... FIFO write ready signal, 7...
...Mask pit register, 8...Write ready signal control circuit. Patent applicant: NEC Corporation, Figure 1, Figure 2

Claims (1)

[Claims] In a FIFO type data input/output device equipped with a data register in which data can be continuously written and data can be read out at regular time intervals, when data is continuously written, valid data is stored in the data register. a setting means for setting the number of stages in which the data register exists to a value that does not cause an underrun due to data read; FIFO write control circuit with control means for activation.