JPS61199334A - Cmi code converting circuit - Google Patents

Abstract

PURPOSE:To prevent generation of glitch by applying code conversion from an NRZ code to a CMI code while keeping a frequency of an input clock signal the same as that of the speed of a binary-coding signal. CONSTITUTION:An input clock signal T having a frequency corresponding to an input data NRZ is given to a delay circuit DLY to obtain a clock signal TD retarding the input clock signal T. Then two kinds of clock pulses T0 synchronously with the leading of the input clock signal T and T1 synchronously with the trailing are generated by ANDing the input clock signal T and an inverted clock signal TD retarding the signal T and ANDing the inverting T and the TD. Then the two kinds of the clock signals are used as a flip-flop deciding the polarity of the first half of the CMI code and as a flip-flop deciding the polarity of the latter half to prevent the glitch.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is directed to CMI (Coded Mark I nve) used as a transmission code of PMCff1.
The present invention relates to a CMI code conversion circuit that creates NRZ signals, clock signals, etc., and particularly relates to a CMI code conversion circuit that suppresses the frequency of the lock signal as necessary.

[Background of the invention]

The CMI code is specified by CCITT as a 139264K bij/S interface code in Recommendation G703, and is also being actively introduced in Japan as a code format suitable for transmission systems that require network synchronization, such as high-speed digital transmission. It is planned.

The CMI code corresponds to a logic "01" as a CMI code for a binary signal of logic II O4', and alternates logic 1+11 B or II OO11 as a CMI code for a binary signal of logic "'1". It is a binary code that is synthesized using a simple code rule that corresponds to .

This code is BSI (Bit 5equence
It has the feature that there is no loss of timing due to the succession of the same code, and the information rate f of the binary signal can be easily changed by inputting it to the tank circuit.
It is known that bit/see timing extraction is possible.

However, the information rate of the CMI code is equal to the information rate f of the corresponding binary signal due to the code rule described above.

bi7/see, so the timing is extracted from the received CMI code and the CMI code is synchronized with that timing.
Transmission using the network synchronization method that requires transmitting MI codes has the following technical problems. First, f from the CMI code. In the method of extracting twice the clock of Pha
(Locked Loop) technology is required, and an increase in the circuit scale such as a voltage controlled oscillator and a phase comparator is unavoidable. Second, the information rate f of the binary signal. bij
In the method of converting to CMI code using a clock with the same frequency as /sec, clock extraction is easy, but as pointed out in Japanese Patent Application Laid-Open No. 59-LO4846, it is necessary to prevent glitches. .

To address the latter problem, JP-A-59-104846 uses a method of masking glitches that occur during conversion using an additional circuit, but this method is insufficient to prevent glitches from occurring for the reasons described below. No, no.

FIG. 3 shows a CMI code conversion circuit disclosed in Japanese Patent Application Laid-Open No. 59-10486 Hayashi, in which gates G7°G8. G9 and flip-flop F4. Although f5 is an additional circuit for masking glitches and the details of its operation are omitted here, as shown in time chart 1- in FIG.
The input data, NRZ code S2, is converted to the information rate f of the corresponding binary signal. When loading into flip-flop F2F in synchronization with input clock signal S1 equal to bit/see, glitch 100 occurs because set-up time and hold time are not guaranteed. This glitch propagates as it is to the output of the CMI code, causing code errors as waveform distortion.

In FIG. 4, a shaded area 102 indicates an uncertain state.

The above-mentioned Japanese Patent Laid-Open No. 59-10486 attempts to remove glitches by providing an additional circuit to mask glitches that occur during conversion.

There was a problem in which glitches would occur in locations other than those intended to be prevented.

[Purpose of the invention]

The object of the present invention is to convert the input clock signal from NRR code to CM while keeping the same frequency as the speed of the binary signal binary code.
It is an object of the present invention to provide a CMI code conversion circuit which can perform code conversion to I code and can sufficiently prevent the occurrence of glitches.

[Summary of the invention]

The present invention provides an input clock signal T having a frequency corresponding to a data rate and a clock signal T delayed from the input clock signal T. By taking the logical product of T and TI and the logical product of T and TI+, a pulse T synchronized with the rising edge of the input clock signal D is obtained. and pulse T synchronized with the falling edge.
, and use these two types of clock pulses as the flip-flop clock signal for determining the polarity of the first half of the CMI code and the clock signal of the flip-flop for determining the polarity of the second half, respectively. By using this, glitches can be prevented.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the CMI code conversion circuit of the present invention, and FIG. 2 shows a time chart explaining its operation.

In FIG. 1, an input clock signal T having a frequency corresponding to input data NRZ is applied to a delay circuit DLY,
A clock signal T, , which is obtained by delaying the input clock signal T, is obtained. Clock signal TQ synchronized with the rising edge of input clock signal T is synchronized with input clock signal T and clock signal T.
. A signal T which is inverted by an inversion gate GC. It is created by taking the logical AND with the AND gate. In addition, a clock signal T synchronized with the falling edge of the input clock signal T,
is the AND gate GB of the logical product of the input clock signal T inverted by the inverting gate GD and the clock signal To.
The six clock signals T, created by taking the CM
The clock signal T0 is used as a clock signal for a flip-flop to determine the polarity of the first half of the I code.
It is used as a flip-flop clock signal to determine the polarity of the second half of the CMI code.

AND gate A1, flip-flop FFI.

FF2 is a circuit that holds the polarity of 111'' sent out immediately before, inverts it, and outputs it.
Clock signal T only when l'1. , and the trigger obtains the signal J1 as the output of the game area A1. Flip-flop FFI should always send out next, N R
It is a flip-flop that maintains the polarity of Z = "1", and under the condition of NRZ = "1", the inverted output of the signal J3 indicating that the polarity of the NRZ to be currently transmitted is 11], TI. It operates to capture signal J4. Blip-prop FF2 is a flip-flop for preventing in-phase transfer, and by delaying the signal J2, which determines the first half of the CMI code, by 1/2 period from the clock signal T1 and using the clock signal Tn,
Output signal J3. in synchronization with clock signal Tn. Get J4. This FF2 output signal J3. J4 is the clock signal T
It is used as a set/reset creation signal for FF4, which synchronizes with 1 and outputs a CMI code.

Flip prop FF3, and gate A2゜A3,
The OR gate A6 is a circuit that creates a set signal for the CMI code flip-flop FF/I. here,
OR gate 6 is the set signal J6 which is the output of gate A.
By ORing the set signal J7 which is the output of the AND gate A3, a set signal JIO is outputted to the CMI code flip-flop FF4. AND gate A2 passes clock signal T when input data NRZ="1" and signal J3="1" indicating that the polarity of NRZ to be currently sent is NII II, and OR gate A6 , a set signal J6 for setting the logic 1llII+ is output. Flip
The flop FF3 takes in the NRZ code as input data using the clock signal T, and outputs a signal J5 which is the inverse of the signal delayed by 1/2 period.

When this signal J5 is II L H, AND gate A3
teeth.

The clock signal T, .

The inverting gate A8, the AND gates A, , A5, and the OR gate A7 are circuits that create a reset signal for the CMI-coded flip-flop FF4.

Here, the OR gate A7 provides a reset signal to the CMI code flip-flop FF4 by ORing the reset signal J8 which is the output of the AND gate A4 and the reset signal J9 which is the output of the AND gate 1-A5. Output Jll. AND gate A4 passes clock signal T when input data NRZ="1" and signal J4="V" indicating that the polarity of NRZ to be currently sent is II O2g, and passes clock signal T to OR gate A7. In contrast, it outputs a reset signal J8 for setting the logic reOOsr.When the NRZ code that is input data is rr Orr, the inverting gate A8 outputs a signal for gating the clock T.This signal Accordingly, AND gate A5 passes clock signal T, and outputs a reset signal J9 for setting logic rr OII to OR gate A7.

By controlling flip-flop FF4 using the set signal JIO and reset signal Jll obtained as described above, the CMI code, which is the final output data, is obtained as the output of FF4.

〔Effect of the invention〕

According to the present invention, in a code conversion circuit from an NRZ code to a CMI code, a circuit can be realized in which the input clock is the same as that of a binary code, does not require twice the clock, and does not generate glitches. A circuit that creates twice as many clocks becomes complex.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the CMI code conversion circuit of the present invention, FIG. 2 is a timing diagram of the operation of FIG. 1, FIG. 3 is a circuit diagram with a conventional glitch prevention circuit added, and FIG. The figure is an operation timing diagram of FIG. 3. NRZ...input code, T...input clock signal,
CM digit...output code, FFI-FF4...flip-flop, DLY...delay circuit, A1-A5
．． OA, GB...andgate, A, 6. A7...Orgate, A8. GC, GD...inversion gate. N)-0ko 2nd Figure-4゜-Figure 3G ``5 Figure 4

Claims (1)

[Claims] (1) A binary binary code with a speed of fn bits/second is transmitted through CMI based on a corresponding fnHz clock signal.
In the CMI code conversion circuit that converts the input clock signal into a code, means is provided to create two types of pulses, one synchronized with the rising edge of the input clock signal and the other pulse synchronized with the falling edge, and these two types of pulses are converted into the first half of the CMI code, respectively. A CMI code conversion circuit characterized in that it is used as a clock signal of a flip-flop for determining the polarity of the second half of the clock and a clock signal of a flip-flop for determining the polarity of the second half.