JPH02139919A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02139919A
JPH02139919A JP29396088A JP29396088A JPH02139919A JP H02139919 A JPH02139919 A JP H02139919A JP 29396088 A JP29396088 A JP 29396088A JP 29396088 A JP29396088 A JP 29396088A JP H02139919 A JPH02139919 A JP H02139919A
Authority
JP
Japan
Prior art keywords
wafer
quartz tube
tube
gas
quartz
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29396088A
Other languages
Japanese (ja)
Inventor
Noboru Terao
寺尾 襄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP29396088A priority Critical patent/JPH02139919A/en
Publication of JPH02139919A publication Critical patent/JPH02139919A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent nonuniformity of heating and development of crystal defects due to heat distortion by providing a wafer with wafer surfaces approximately parallel each other inside an inner side tube having inner surfaces which are approximately parallel each other and by inserting the inner side tube into an outer side tube which is heated in advance. CONSTITUTION:Inner surfaces 7a of an inner side quartz tube 7 are approximately parallel each other, and an inner surface 7a and a wafer surface 30 of an Si wafer 3 are also parallel. Although the Si wafer 3 is heated through the inner side quartz 7, the wafer surface 3a of the Si wafer 3 is approximately parallel to the inner surface 7a of the inner side quartz tube 7; therefore, heat flows at right angles to the wafer surface 3a and the wafer surface 3a is uniformly heated. Although an outer side quartz tube 1 is heated in advance by a furnace body 4, the Si wafer 3 prevents development of heat distortion due to rapid heating of a heat capacity of the inner side quartz tube 7.

Description

【発明の詳細な説明】 〔産業上の利用分舒〕 乙の発明は、半導体装置の製造工程における半導体ウニ
への熱処理を行う半導体装置の製造装置に関するもので
ある。
[Detailed Description of the Invention] [Industrial Application] The invention of Part B relates to a semiconductor device manufacturing apparatus that performs heat treatment on a semiconductor sea urchin in a semiconductor device manufacturing process.

〔従来の技術〕[Conventional technology]

第4図(a)   (b)は従来の半導体装置の製造装
置を示す正面断面図および側面図である。第4図におい
て、1は石英管(t&述の実施例では外側の石英管とい
う) 2はこの石英管1の内部に挿入された石英ボート
、3はこの石英ボート2上に並置されたSiウェハ、4
は前記石英管1を介してSiウェハ3を加熱するための
炉体、5は前記石英管1へのガス供給口であり、6は前
記石英管1に設けられた石英ボート2の押入口である。
FIGS. 4(a) and 4(b) are a front sectional view and a side view showing a conventional semiconductor device manufacturing apparatus. In FIG. 4, 1 is a quartz tube (referred to as the outer quartz tube in the embodiment described above), 2 is a quartz boat inserted into the quartz tube 1, and 3 is a Si wafer juxtaposed on this quartz boat 2. , 4
is a furnace body for heating the Si wafer 3 through the quartz tube 1, 5 is a gas supply port to the quartz tube 1, and 6 is an inlet for the quartz boat 2 provided in the quartz tube 1. be.

次に動作について説明する。Next, the operation will be explained.

石英ボー1−2はSiウェハ3を保持する治具であり、
Siウェハ3は不純物の拡散、酸化、cvD、アニール
等のために1000℃前後の高温ニする必要があるが、
そのために炉体4によって石英管1をあらかじめ加熱し
ておき、その石英管1の内部に、石英ボート2に保持さ
れたSiウェハ3を挿入口6より挿入する。ガス供給口
5からは、必要に応じてN、、O,その他のガスを導入
し、S1ウニ八3を一定の雰囲気に保持する。
The quartz bowl 1-2 is a jig for holding the Si wafer 3,
The Si wafer 3 needs to be heated to a high temperature of around 1000°C for impurity diffusion, oxidation, CVD, annealing, etc.
For this purpose, the quartz tube 1 is heated in advance by the furnace body 4, and the Si wafer 3 held in the quartz boat 2 is inserted into the quartz tube 1 through the insertion port 6. From the gas supply port 5, N, O, and other gases are introduced as necessary to maintain the S1 sea urchin 8 3 in a constant atmosphere.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置の製造装置は、以上のように構成され
ているので、Siウェハ3の加熱ガスが不拘τになる問
題点があった。すなわち、加熱がSiウェハ3の周辺部
から中心部に向って進むので、Siウェハ3内部に温度
勾配が発生し、それが原因となってSiウェハ3に内部
歪みが発生して結晶欠陥が生じる。また、Slウェハ3
は石英管1の挿入口6から挿入される時に、低温から急
に高温にさらされるので、この時もS1ウ工ハ3内部に
温度の不均一が発生し、結晶欠陥が生しる。
Since the conventional semiconductor device manufacturing apparatus is configured as described above, there is a problem in that the heating gas for the Si wafer 3 is unrestricted τ. That is, since the heating progresses from the periphery of the Si wafer 3 toward the center, a temperature gradient occurs inside the Si wafer 3, which causes internal distortion in the Si wafer 3 and crystal defects. . In addition, Sl wafer 3
When inserted through the insertion port 6 of the quartz tube 1, it is suddenly exposed from a low temperature to a high temperature, so that temperature non-uniformity occurs inside the S1 wafer 3 at this time as well, resulting in crystal defects.

これらの不具合のために、従来の半導体装置の製造装置
は一定以上の大面積のウェハでは実用に供し得ない問題
点があった。
Because of these defects, conventional semiconductor device manufacturing apparatuses have problems that cannot be put to practical use with wafers of a certain or larger area.

また、従来の半導体装置の製造装置は、ガス供給口5が
石英管1の端部にあるので、ガス供給口5に対し、Si
ウェハ3が直列に多数設置されることになり、ウェハ面
に新鮮なガスを均一に当てることができない。したがっ
て、供給されるガスが特に反応性ガスの場合には、ウェ
ハ面に均一に不純物を供給したり、酸化膜を形成したり
するのに不具合が生じる場合がある。
Furthermore, in the conventional semiconductor device manufacturing apparatus, since the gas supply port 5 is located at the end of the quartz tube 1, the Si
Since a large number of wafers 3 are installed in series, fresh gas cannot be uniformly applied to the wafer surface. Therefore, especially when the supplied gas is a reactive gas, problems may arise in uniformly supplying impurities to the wafer surface or in forming an oxide film.

この発明は、上記のようなlj1題点を解消するために
なされたもので、半導体ウェハを均一に加熱することに
より、大面積の半導体ウェハでも、結晶欠陥等の不具合
を発生させることのない半導体装置の製造装置を提供す
ることを目的とする。
This invention was made to solve the above-mentioned problems, and by uniformly heating the semiconductor wafer, it is possible to produce semiconductors that do not cause defects such as crystal defects even in large-area semiconductor wafers. The purpose is to provide equipment for manufacturing equipment.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造装置は、互いにほぼ平
行な内面を持つ耐熱性材料からなりボートに載置され力
半導体ウェハが挿入される内側の宮と、この内側の官が
挿入される耐熱性材料からなる外側の管と、内側の管内
に挿入され力半導体ウェハのウェハ面に対し平行にガス
が供給されるようにガス導入口およびガス導出口を設け
たものである。
The semiconductor device manufacturing apparatus according to the present invention is placed on a boat and is made of a heat-resistant material and has inner surfaces that are substantially parallel to each other. It is provided with an outer tube made of a material, and a gas inlet and a gas outlet so as to be inserted into the inner tube and to supply gas parallel to the wafer surface of the semiconductor wafer.

〔作用〕[Effect]

この発明においては、ボートに載置され力半導体ウェハ
を内側の管内に挿入し、この内側の管を外側の管内に挿
入して熱処理を行うようにしたことから、半導体ウェハ
は急熱されることがなくなり、急熱によるウェハ面の加
熱の不均一を防ぎ、熱歪みによる結晶欠陥の発生を防止
する。
In this invention, the semiconductor wafer placed on a boat is inserted into an inner tube, and this inner tube is inserted into an outer tube to perform heat treatment, so that the semiconductor wafer is not heated rapidly. This prevents uneven heating on the wafer surface due to rapid heating, and prevents crystal defects due to thermal distortion.

また、ガス流はウェハ面に対して均一に流れるので、ウ
ェハ面に均一に不純物が供給されろ。
Furthermore, since the gas flow is uniform over the wafer surface, impurities can be uniformly supplied to the wafer surface.

〔実施例〕〔Example〕

第1図(al  (b)はこの発明の一実施例を示す半
導体装置の製造装置の正面断面図および側面断面図であ
る。この図において、第4図と同一符号は同しものを示
し、7は前記外側の石英管1の内部に押入された内側の
石英管であり、この内側の石英管7の内面7aは互いに
ほぼ平行になってお’)、内I7aとSiウェハ3のウ
ェハ面3aもほぼ平行となっている。
FIG. 1(b) is a front sectional view and a side sectional view of a semiconductor device manufacturing apparatus showing an embodiment of the present invention. In this figure, the same reference numerals as in FIG. 4 indicate the same things, Reference numeral 7 denotes an inner quartz tube pushed into the outer quartz tube 1, and the inner surfaces 7a of the inner quartz tube 7 are substantially parallel to each other. 3a is also almost parallel.

次に動作について説明する。Next, the operation will be explained.

Siつ工へ3は内側の石英管7全通して加熱されるが、
Siウェハ3のウェハ面3aは内側の石英管7の内面7
aとほぼ平行になっているので、熱流はウェハ面3aに
対して直角方向に流れしたがって、ウェハ面3aは均一
に加熱されることになる。石英ボート2は内側の石英管
7の内部に挿入されているが、この石英ボート2にSi
ウェハ3を保持することにより、Siウェハ3が内側の
石英w7の内部に挿入されることになる。外側の石英管
1は炉体4によって一般には、あらかじめ加熱されてい
るが、そのあらかじめ加熱されている外側の石英w1の
内部にSiウェハ3が設置された内側の石英管7が挿入
されるが、この時Siウェハ3は外側の石英管1の持つ
熱容量のなめに急激に加熱されることはない。したがっ
て、急熱による熱歪みの発生を防ぐことができるので、
熱歪みによる結晶欠陥の発生やSiウェハ3の変形を防
ぐことができる。また、内側の石英管7を外側の石英管
1からの引き出す場合でも、Siウェハ3は内側の石英
管7の持つ熱容量のために急激には冷却されない。した
がって、前述と同様の効果を有する。このようにSiウ
ェハ3は場所的には均一に、時間的にはなめらかに加熱
、冷却がなされる。
The silicon tube 3 is heated through the entire inner quartz tube 7,
The wafer surface 3a of the Si wafer 3 is the inner surface 7 of the inner quartz tube 7.
Since the heat flow is substantially parallel to a, the heat flow flows in a direction perpendicular to the wafer surface 3a, so that the wafer surface 3a is uniformly heated. The quartz boat 2 is inserted into the inner quartz tube 7;
By holding the wafer 3, the Si wafer 3 is inserted into the inner quartz w7. The outer quartz tube 1 is generally preheated by the furnace body 4, and the inner quartz tube 7 on which the Si wafer 3 is installed is inserted into the preheated outer quartz w1. At this time, the Si wafer 3 is not heated rapidly due to the heat capacity of the outer quartz tube 1. Therefore, it is possible to prevent thermal distortion caused by rapid heating.
Generation of crystal defects and deformation of the Si wafer 3 due to thermal strain can be prevented. Furthermore, even when the inner quartz tube 7 is pulled out from the outer quartz tube 1, the Si wafer 3 is not cooled rapidly due to the heat capacity of the inner quartz tube 7. Therefore, it has the same effect as described above. In this way, the Si wafer 3 is heated and cooled uniformly in terms of location and smoothly in terms of time.

第2図(a))(b)はこの発明の他の実施例を示す正
面断面図および側断面図である。この図において、第1
図と同一符号は同じものを示し、8は前記石英ボート2
が挿入される内側の石英管で、矩形状に形成されている
。11は前記内側の石英管8と同様の形状に形成された
外側の石英管で、その内部に内側の石英管8が挿入され
ている。
FIGS. 2(a) and 2(b) are a front sectional view and a side sectional view showing another embodiment of the present invention. In this figure, the first
The same reference numerals as in the figure indicate the same things, and 8 is the quartz boat 2.
The inner quartz tube is inserted into a rectangular shape. Reference numeral 11 designates an outer quartz tube formed in the same shape as the inner quartz tube 8, into which the inner quartz tube 8 is inserted.

内側p石英管8の内面8aは互いにほぼ平行であり、こ
の内面8aとSiウェハ3のウェハ面3aもほぼ平行と
なっている。さらに、外側の石英管11の内面11aも
互いにほぼ平行であり、内面11aと内側の石英管8の
内面8aおよびウェハ面3aもほぼ平行となっている この実施例では、Siウェハ3のウェハ面3aは内側の
石英管8の内面8aとほぼ平行になっているのみならず
、さらにその外側の石英管11の内面tfaともほぼ平
行になっているので、熱流はウェハ面3aに対してより
直角方向となり易(、ウェハ面3aは第1図の実施例よ
り均一に加熱されることになる。
The inner surfaces 8a of the inner p-quartz tube 8 are substantially parallel to each other, and the inner surfaces 8a and the wafer surface 3a of the Si wafer 3 are also substantially parallel. Further, in this embodiment, the inner surfaces 11a of the outer quartz tubes 11 are also substantially parallel to each other, and the inner surfaces 11a, the inner surfaces 8a of the inner quartz tubes 8, and the wafer surface 3a are also substantially parallel. 3a is not only substantially parallel to the inner surface 8a of the inner quartz tube 8, but also substantially parallel to the inner surface tfa of the outer quartz tube 11, so that the heat flow is more perpendicular to the wafer surface 3a. (The wafer surface 3a is heated more uniformly than in the embodiment shown in FIG. 1.)

第3図(a)、(b)はこの発明のさらに他の実施例を
示す正面断面図および側断面図である。
FIGS. 3(a) and 3(b) are a front sectional view and a side sectional view showing still another embodiment of the present invention.

この図において、第1図2第2図と同一符号は同じもの
を示し、12は外側の石英管で、これに内側の石英管9
が挿入される。内側の石英管9は、その外周面の所要個
所にガス導入部9aとガス導出部9bが形成され、ガス
導入部9aにはガス導入口5aが、ガス導出部9bには
ガス導出口5bがそれぞれ設けられている。そして、内
側の石英管9のガス導入側の内壁10aにはガスを噴出
する多数の小孔からなるガス供給用小孔10bが形成さ
れ、ガス導入側の内壁10cにはガス排出用小孔10d
がそれぞれ形成されている。そして、内壁10aの内壁
面と内壁10bの内壁面とは対向して形成され、Slウ
ェハ3に対しガスの流れが均一になるように構成されて
いる。また、内側の石英管9の石英ボー)−2の挿入1
」6には管内に供給ガス以外の外部雰囲気が混入しない
ようにするために管内を密閉するキャップ13が装着さ
れ、ガス導入口5aに可撓性配管14が接続されている
。この可撓性配管14を用いる乙とにより内側の石英f
f9の出し入れが容易となる。なお、内側の石英管9内
に外部雰囲気が混入しない構造になっている限り内壁1
0a、10cは外側の石英管12と一体である必要はな
い。
In this figure, the same reference numerals as in FIG. 1, FIG. 2, and FIG.
is inserted. The inner quartz tube 9 has a gas inlet 9a and a gas outlet 9b formed at required locations on its outer peripheral surface, the gas inlet 9a has a gas inlet 5a, and the gas outlet 9b has a gas outlet 5b. Each is provided. A small gas supply hole 10b consisting of a large number of small holes for ejecting gas is formed in the inner wall 10a on the gas introduction side of the inner quartz tube 9, and a small gas discharge hole 10d is formed in the inner wall 10c on the gas introduction side.
are formed respectively. The inner wall surface of the inner wall 10a and the inner wall surface of the inner wall 10b are formed to face each other, so that the gas flow is uniform with respect to the Sl wafer 3. In addition, insert 1 of the quartz bow)-2 of the inner quartz tube 9.
6 is fitted with a cap 13 for sealing the inside of the pipe to prevent external atmosphere other than the supply gas from entering the pipe, and a flexible pipe 14 is connected to the gas inlet 5a. By using this flexible piping 14, the inner quartz f
It becomes easy to put in and take out f9. Note that as long as the structure is such that external atmosphere does not mix into the inner quartz tube 9, the inner wall 1
0a and 10c do not need to be integral with the outer quartz tube 12.

なお、上記実施例では、半導体ウェハとしてSiウェハ
3の場合について説明したが、GeやGaAs等の他の
半導体ウェハでもよい。
In the above embodiment, the case where the Si wafer 3 is used as the semiconductor wafer has been described, but other semiconductor wafers such as Ge and GaAs may also be used.

また、上記各実施例では、石英管について説明したが、
管の材料としては、ポリSiや、グラフーノ・イト等の
他の耐熱性の材料で構成してもよい。
In addition, in each of the above embodiments, a quartz tube was explained, but
The tube may be made of other heat-resistant materials such as poly-Si or graphite.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明は、互いにほぼ平行な内面
を持つ耐熱性材料からなりボートに載置され力半導体ウ
ェハが挿入される内側の管と、この内側の管が挿入され
る耐熱性材料からなる外側の管と、内側の管内に挿入さ
れ力半導体ウェハのウェハ面に対し平行にガスが供給さ
れるようにガス導入口およびガス導出口を設けたので、
ウェハを均一に加熱することができ、したがって加熱に
よるウェハの結晶欠陥や変形を防ぐことができる。
As explained above, this invention consists of an inner tube made of a heat-resistant material with inner surfaces substantially parallel to each other and placed on a boat into which a semiconductor wafer is inserted, and a heat-resistant material into which this inner tube is inserted. An outer tube is inserted into the inner tube, and a gas inlet and a gas outlet are provided so that the gas is supplied parallel to the wafer surface of the semiconductor wafer.
The wafer can be heated uniformly, and therefore crystal defects and deformation of the wafer due to heating can be prevented.

また、ウェハを設置した管をさらに加熱した管に挿入す
る場合、ガス供給口および排出口を互いに対向させるこ
とにより、ガスの流れも均一にすることができるので、
ウェハ面を均一に反応処理することができる。
In addition, when inserting the tube with the wafer installed into a further heated tube, the gas flow can be made uniform by arranging the gas supply and discharge ports to face each other.
The wafer surface can be uniformly subjected to reaction treatment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a )、 (b )はこの発明の一実施例を示
す半導体装置の製造装置の正面断面図および側面断面図
、第2図(a)、(b)はこの発明の他の実施例を示す
正面断面図および側断面図、第3図(a)。 (b)はこの発明のさらに他の実施例を示す正面断面図
および側断面図、第4図(a)、(b)は従来の半導体
装置の製造装置舎示す正面断面図および側面図である。 図において、1,11.12は外側の石英管、2は石英
ボート、3はSiウェハ、3aはウェハ面、4は炉体、
5はガス供給口、5aはガス導入口、5bはガス導出口
、6は石英管の挿入口、7゜8.9は内側の石英管、7
a、8a、11 aは内面、9aはガス導入部、9bは
ガス導出部、10a、10cは内壁、10bはガス供給
用小孔、10dはガス排出用小孔である。 なお、 各図中の同一符号は同一または相当部分を示す。
1(a) and 1(b) are a front sectional view and a side sectional view of a semiconductor device manufacturing apparatus showing one embodiment of the present invention, and FIGS. 2(a) and 2(b) are another embodiment of the present invention. FIG. 3(a) is a front sectional view and a side sectional view showing an example. (b) is a front sectional view and a side sectional view showing still another embodiment of the present invention, and FIGS. 4(a) and 4(b) are a front sectional view and a side view showing a conventional semiconductor device manufacturing equipment building. . In the figure, 1, 11, 12 are outer quartz tubes, 2 is a quartz boat, 3 is a Si wafer, 3a is a wafer surface, 4 is a furnace body,
5 is a gas supply port, 5a is a gas inlet, 5b is a gas outlet, 6 is a quartz tube insertion port, 7°8.9 is an inner quartz tube, 7
a, 8a, 11 a is an inner surface, 9a is a gas inlet, 9b is a gas outlet, 10a, 10c are inner walls, 10b is a small hole for gas supply, and 10d is a small hole for gas discharge. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] ボートに載置された半導体ウェハを加熱処理する半導体
装置の製造装置において、互いにほぼ平行な内面を持つ
耐熱性材料からなり前記ボートに載置された半導体ウェ
ハが挿入される内側の管と、この内側の管が挿入される
耐熱性材料からなる外側の管と、前記内側の管内に挿入
され力半導体ウェハのウェハ面に対し平行にガスが供給
されるようにガス導入口およびガス導出口を設けたこと
を特徴とする半導体装置の製造装置。
A semiconductor device manufacturing apparatus that heat-processes semiconductor wafers placed on a boat includes an inner tube made of a heat-resistant material and having inner surfaces substantially parallel to each other, into which the semiconductor wafers placed on the boat are inserted; An outer tube made of a heat-resistant material into which the inner tube is inserted, and a gas inlet and a gas outlet so as to be inserted into the inner tube and to supply gas parallel to the wafer surface of the semiconductor wafer. A semiconductor device manufacturing apparatus characterized by:
JP29396088A 1988-11-21 1988-11-21 Manufacture of semiconductor device Pending JPH02139919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29396088A JPH02139919A (en) 1988-11-21 1988-11-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29396088A JPH02139919A (en) 1988-11-21 1988-11-21 Manufacture of semiconductor device

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JPH02139919A true JPH02139919A (en) 1990-05-29

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JP29396088A Pending JPH02139919A (en) 1988-11-21 1988-11-21 Manufacture of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159873A (en) * 1995-03-30 2000-12-12 F.T.L. Co., Ltd. Method for producing semiconductor device and production apparatus of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6159873A (en) * 1995-03-30 2000-12-12 F.T.L. Co., Ltd. Method for producing semiconductor device and production apparatus of semiconductor device

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