JPH02138431U - - Google Patents
Info
- Publication number
- JPH02138431U JPH02138431U JP1989047552U JP4755289U JPH02138431U JP H02138431 U JPH02138431 U JP H02138431U JP 1989047552 U JP1989047552 U JP 1989047552U JP 4755289 U JP4755289 U JP 4755289U JP H02138431 U JPH02138431 U JP H02138431U
- Authority
- JP
- Japan
- Prior art keywords
- convex portions
- transistor chip
- metallized
- fused
- heat dissipation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
第１図はこの考案の一実施例を示す半導体装置
の断面図、第２図は従来の半導体装置を示す断面
図である。
図において、１……放熱フイン、１ａ……凸部
、２，４……セラミツクス、３……メタライズ部
、５……リード端子、６……トランジスタチツプ
、７……金属細線、７ａ……接地細線である。な
お、各図中の同一符号は同一または相当部分を示
す。
FIG. 1 is a sectional view of a semiconductor device showing an embodiment of this invention, and FIG. 2 is a sectional view of a conventional semiconductor device. In the figure, 1...Radiation fin, 1a...Protrusion, 2, 4...Ceramics, 3...Metalized part, 5...Lead terminal, 6...Transistor chip, 7...Metal thin wire, 7a...Grounding It is a thin line. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
け、前記２箇所の凸部間の中央部に表裏両面にメ
タライジングが施されたセラミツクスを介してト
ランジスタチツプを融着し、少なくとも前記トラ
ンジスタチツプと２箇所の凸部とを接地細線によ
り接続したことを特徴とする半導体装置。 Two convex portions are provided on a heat dissipation fin made of metal, and a transistor chip is fused to the central portion between the two convex portions via ceramics that are metallized on both the front and back surfaces, so that at least the transistor chip and two convex portions are connected by a thin ground wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989047552U JPH02138431U (en) | 1989-04-20 | 1989-04-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989047552U JPH02138431U (en) | 1989-04-20 | 1989-04-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02138431U true JPH02138431U (en) | 1990-11-19 |
Family
ID=31563580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989047552U Pending JPH02138431U (en) | 1989-04-20 | 1989-04-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02138431U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629356A (en) * | 1991-06-13 | 1994-02-04 | Nec Yamagata Ltd | Enclosure for semiconductor device |
-
1989
- 1989-04-20 JP JP1989047552U patent/JPH02138431U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0629356A (en) * | 1991-06-13 | 1994-02-04 | Nec Yamagata Ltd | Enclosure for semiconductor device |