JPH02137229A - Formation of metallic wiring - Google Patents
Formation of metallic wiringInfo
- Publication number
- JPH02137229A JPH02137229A JP29144788A JP29144788A JPH02137229A JP H02137229 A JPH02137229 A JP H02137229A JP 29144788 A JP29144788 A JP 29144788A JP 29144788 A JP29144788 A JP 29144788A JP H02137229 A JPH02137229 A JP H02137229A
- Authority
- JP
- Japan
- Prior art keywords
- needless
- layers
- resist film
- metallic
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000000853 adhesive Substances 0.000 claims description 11
- 230000001070 adhesive effect Effects 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- 239000000463 material Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000007738 vacuum evaporation Methods 0.000 abstract description 2
- 239000007769 metal material Substances 0.000 description 5
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- PBKONEOXTCPAFI-UHFFFAOYSA-N 1,2,4-trichlorobenzene Chemical compound ClC1=CC=C(Cl)C(Cl)=C1 PBKONEOXTCPAFI-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- BZHJMEDXRYGGRV-UHFFFAOYSA-N Vinyl chloride Chemical compound ClC=C BZHJMEDXRYGGRV-UHFFFAOYSA-N 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/143—Masks therefor
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、微細な金属配線の形成に適したりフトオフ法
の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in a foot-off method suitable for forming fine metal wiring.
（ロ）従来の技術
従来、微細な金属配線を形成する為の技術としては、例
えば特開昭６２−３６８４５号公報（ＨＯＩＬ ２１／
８８）に記載されているリフトオフプロセスが知られて
いる。(b) Conventional technology Conventionally, as a technology for forming fine metal wiring, for example, Japanese Patent Laid-Open No. 62-36845 (HOIL 21/
The lift-off process described in 88) is known.
このプロセスは、先ず第２図Ａに示す様ニ、絶縁基板又
はシリコン酸化膜等の下地絶縁基板（１）の上にレジス
ト膜（２）を形成し、このレジスト膜（２）に所望の配
線パターンに対応した開孔部をその側壁にオーバーハン
グが生ずるように形成し、次に第２図Ｂに示す様に、こ
のオーバーハングを有するレジスト膜（２）をマスクと
して下地絶縁基板（１）上に選択的に金属を被着して金
属配線層（３）を形成し、続いて第２図Ｃに示す様に、
レジスト膜（２）及びその上の被着金属層り４）を除去
するようにしたものである。In this process, as shown in FIG. 2A, a resist film (2) is first formed on a base insulating substrate (1) such as an insulating substrate or a silicon oxide film, and a desired wiring is formed on this resist film (2). An opening corresponding to the pattern is formed so that an overhang occurs on its side wall, and then, as shown in FIG. A metal wiring layer (3) is formed by selectively depositing metal thereon, and then as shown in FIG. 2C,
The resist film (2) and the metal layer 4) deposited thereon are removed.
（ハ）発明が解決しようとする課題
しかしながら、前記オーバーハングをコントロールする
ことが難しいことから、金属配線層（３）とレジスト膜
（２）上の被着金属層（４）とが完全に切断されないこ
とが多く、その為レジスト膜（２）をリフトオフしても
その上の被着金属層（４）が残る事故が多発する欠点が
あった。また、金属配線層（３）とレジスト膜（２）上
の金属配線層（４）との間隔が極めて狭い為、レジスト
膜り２）のエツチングに時間がかかる欠点があった。(c) Problems to be Solved by the Invention However, since it is difficult to control the overhang, the metal wiring layer (3) and the metal layer (4) deposited on the resist film (2) are completely disconnected. Therefore, even if the resist film (2) is lifted off, there are many accidents in which the deposited metal layer (4) remains on the resist film (2). Furthermore, since the distance between the metal wiring layer (3) and the metal wiring layer (4) on the resist film (2) is extremely narrow, there is a drawback that etching the resist film 2) takes time.
（ニ）課題を解決するための手段
本発明は上記従来の課題に鑑み成されたもので、粘着シ
ート（１５）でレジスト膜（１２）上の金属配線層（１
４）を除去することにより、不要金属層（１４）を容易
に除去できる金属配線の形成方法を提供するものである
。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems.
By removing 4), a method for forming a metal wiring is provided in which the unnecessary metal layer (14) can be easily removed.
（＊）作用
本発明によれば、金属配線層（１３）とレジスト膜（１
２）上の金属配線層（１４）とが薄い金属配線材料でつ
ながっていても、粘着シート（１５）の粘着力により強
制的にはがすので、不要金属層（１４）を完全に且つ簡
単に除去することができる。(*) Function According to the present invention, the metal wiring layer (13) and the resist film (1
2) Even if the upper metal wiring layer (14) is connected to the metal wiring layer (14) by a thin metal wiring material, it is forcibly removed by the adhesive force of the adhesive sheet (15), so the unnecessary metal layer (14) can be completely and easily removed. can do.
（へ）実施例 以下、本発明の一実施例を説明する。(f) Example An embodiment of the present invention will be described below.
先ず第１図Ａに示す様に、ＧａＡｓ基板やガラス基板等
の絶縁基板又は表面にシリコン酸化膜を形成したシリコ
ン基板等の絶縁基板（１１）の表面にホトレジストを塗
布し、これに所望の配線パターンを露光により転写し、
現像することにより配線形成用マスクとしてのホトレジ
スト膜（１２）を形成する。この場合、−例としては富
士ハントエレクトロニクステクノロジー株式会社から’
ＨＰＲ１１８２Ｊとして販売されているポジレジストを
用い、現像はＭＩＦ現像液（２５％）で６０秒程度とし
た。他にも日立化成株式会社から「ＲＵ １１００Ｊと
して販売されているネガレジストや富士薬品工業株式会
社から’ＬＭＲＪとして販売されているネガレジスト等
が使用できる。First, as shown in FIG. 1A, a photoresist is applied to the surface of an insulating substrate (11) such as an insulating substrate such as a GaAs substrate or a glass substrate, or a silicon substrate on which a silicon oxide film is formed, and desired wiring is formed on this. Transfer the pattern by exposure,
By developing, a photoresist film (12) is formed as a mask for wiring formation. In this case - for example, from Fuji Hunt Electronics Technology Co., Ltd.'
A positive resist sold as HPR1182J was used, and development was performed for about 60 seconds with an MIF developer (25%). In addition, a negative resist sold as RU 1100J from Hitachi Chemical Co., Ltd. and a negative resist sold as LMRJ from Fuji Pharmaceutical Co., Ltd. can also be used.
次に第１図Ｂに示す様に、真空蒸着法又はスパッタ法に
よりアルミニウム等の配線用金属を基板（１１）上面に
被着する。このとき、基板り１１）上にはレジスト膜（
１２）をマスクとして選択的に金属が被着され、金属配
線層〈１３）が形成される。レジスト膜（１２）上には
不要金属層（１４）が被着される。これらはレジスト膜
（１２）の膜厚と側壁のオーバーハングの働きによって
分離されるので、金属配線層（１３）と不要金属層り１
４）とが薄い金属材料でつながったままの不良箇所が発
生し易い。Next, as shown in FIG. 1B, a wiring metal such as aluminum is deposited on the upper surface of the substrate (11) by vacuum evaporation or sputtering. At this time, the resist film (
Using 12) as a mask, metal is selectively deposited to form a metal wiring layer <13). An unnecessary metal layer (14) is deposited on the resist film (12). These are separated by the thickness of the resist film (12) and the side wall overhang, so the metal wiring layer (13) and unnecessary metal layer 1
4) Faulty parts are likely to occur where the parts and parts remain connected by a thin metal material.
次に第１図Ｃに示す様に、金属配線Ｎ（１３）と不要金
属Ｊｆｉ （１４）との高さの差を利用して不要金属層
（１４）に接着するように粘着シート（１５）を貼付け
る。場合によってはローラー等により圧着する。Next, as shown in FIG. 1C, an adhesive sheet (15) is attached to the unnecessary metal layer (14) by utilizing the difference in height between the metal wiring N (13) and the unnecessary metal Jfi (14). Paste. Depending on the case, it may be crimped using a roller or the like.
この粘着シート（１５）は、膜厚５０〜１００μｍのポ
リエステルフィルム又は塩化ビニルフィルムを基材とし
た半導体ウェハ固定・保護用の粘着フィルムであり、例
えば日東電気工業株式会社からニレツブホルダー’ＢＴ
５０，５１Ｊとして販売きれているものや、三井東圧化
学株式会社からイクロステーブｒＳＢタイプ」として販
売されているものが使用できる。This adhesive sheet (15) is an adhesive film for fixing and protecting semiconductor wafers, which is made of polyester film or vinyl chloride film with a film thickness of 50 to 100 μm as a base material.
50, 51J, and those sold by Mitsui Toatsu Chemical Co., Ltd. as ``ICROSTABE rSB type'' can be used.
次に第１図りに示す様に、粘着シート（１５）の粘着力
を保持したままで（ＵＶ処理や熱処理を処さないで）粘
着シート（１５）を引はがすことにより、不要金属層（
１４）をレジスト膜（１２）上から除去する。この時、
不要金属層（１４）と金属配線層（１３）とが薄い金属
材料でつながっていても、粘着シート（１５）を強制的
に引はがすことにより、前記薄い金属材料を分断する。Next, as shown in the first diagram, by peeling off the adhesive sheet (15) while maintaining its adhesive strength (without UV treatment or heat treatment), remove the unnecessary metal layer (
14) is removed from the resist film (12). At this time,
Even if the unnecessary metal layer (14) and the metal wiring layer (13) are connected by a thin metal material, the thin metal material is separated by forcibly peeling off the adhesive sheet (15).
尚、強度的不安が残るような材料であれば、金属材料被
着後に前記薄い金属材料を溶かすだけの軽いエツチング
を行えば済む。Incidentally, if the material is of a type in which there are concerns about its strength, it is sufficient to perform a light etching process that merely melts the thin metal material after the metal material has been deposited.
そして第１図Ｅに示す様に、残ったレジスト膜（１２）
をトリクロルベンゼン等の有機溶剤でウェット方式によ
り除去するか、又はＯ，アッシング等のドライ方式によ
り除去する。尚、本工程でドライ方式を採用すれば、レ
ジスト現像を含み全ての工程をドライ化できる。Then, as shown in Figure 1E, the remaining resist film (12)
is removed by a wet method using an organic solvent such as trichlorobenzene, or by a dry method such as O, ashing. Note that if a dry method is adopted in this step, all steps including resist development can be made dry.
以上に説明した本願構成によれば、粘着シート（１５）
により不要金属層（１４）の除去を行うので、不要金属
Ｊ’！（１４）を確実に且つ容易に除去できる。また、
不要金属層（１４）を除去した後はレジスト膜（１２）
が完全に露出するので、レジスト膜（１２）の除去スピ
ードが速く従って処理速度も速くできる。さらに、粘着
シート（１５）により、リフトオフ手法を完全にドライ
化することが可能である。According to the configuration of the present application explained above, the adhesive sheet (15)
Since the unnecessary metal layer (14) is removed by the unnecessary metal J'! (14) can be reliably and easily removed. Also,
After removing unnecessary metal layer (14), resist film (12)
Since the resist film (12) is completely exposed, the removal speed of the resist film (12) is fast, and the processing speed can also be increased. Furthermore, the adhesive sheet (15) allows the lift-off technique to be completely dry.
（ト）発明の詳細
な説明した如く、本発明によれば粘着シートク１５）を
利用するこ、とにより、不要金属層（１４）を確実に且
つ容易に除去できる利点を有する。また、レジスト膜（
１２）が完全に露出されるので、完全なドライ化にも対
応できる利点を有する。従って、確実な除去ができるこ
ととドライ化に対応できることから、自動化処理に好適
である利点をも有する。(G) As described in detail, the present invention has an advantage in that the unnecessary metal layer (14) can be reliably and easily removed by using the adhesive sheet (15). In addition, resist film (
12) is completely exposed, so it has the advantage of being completely dry. Therefore, it has the advantage of being suitable for automated processing because it can be removed reliably and can be dried.
第１図Ａ乃至第１図Ｅは夫々本発明を説明する為の断面
図、第２図Ａ乃至第２図Ｃは夫々従来例を説明する為の
断面図である。1A to 1E are sectional views for explaining the present invention, and FIGS. 2A to 2C are sectional views for explaining a conventional example.
Claims (2)
を有するレジスト膜を形成する工程と、前記レジスト膜
をマスクとして前記基板の上に選択的に金属を被着して
金属配線層を形成する工程と、 前記レジスト膜の上に残った金属膜に粘着シートを貼付
け、これを剥離することにより前記レジスト膜の上の金
属膜を除去する工程と、 前記レジスト膜を除去する工程とを具備することを特徴
とする金属配線形成方法。(1) Forming a resist film having openings corresponding to a predetermined wiring pattern on the substrate, and selectively depositing metal on the substrate using the resist film as a mask to form a metal wiring layer. A step of attaching an adhesive sheet to the metal film remaining on the resist film and removing the metal film on the resist film by peeling it off; A step of removing the resist film. A method for forming metal wiring, comprising:
トオフプロセスを全てドライ化したことを特徴とする請
求項第１項に記載の金属配線形成方法。(2) The metal wiring forming method according to claim 1, wherein the resist film is removed by dry etching, and the lift-off process is entirely dry.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29144788A JPH02137229A (en) | 1988-11-17 | 1988-11-17 | Formation of metallic wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29144788A JPH02137229A (en) | 1988-11-17 | 1988-11-17 | Formation of metallic wiring |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02137229A true JPH02137229A (en) | 1990-05-25 |
Family
ID=17768986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29144788A Pending JPH02137229A (en) | 1988-11-17 | 1988-11-17 | Formation of metallic wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02137229A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121402A (en) * | 1991-06-06 | 1993-05-18 | Internatl Business Mach Corp <Ibm> | Method of forming pattern thin-film on substrate |
| JP2007098662A (en) * | 2005-09-30 | 2007-04-19 | Aoki Technical Laboratory Inc | Mold unit comprising neck mold and core mould |
-
1988
- 1988-11-17 JP JP29144788A patent/JPH02137229A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05121402A (en) * | 1991-06-06 | 1993-05-18 | Internatl Business Mach Corp <Ibm> | Method of forming pattern thin-film on substrate |
| JP2007098662A (en) * | 2005-09-30 | 2007-04-19 | Aoki Technical Laboratory Inc | Mold unit comprising neck mold and core mould |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5240878A (en) | Method for forming patterned films on a substrate | |
| JPH02137229A (en) | Formation of metallic wiring | |
| JPS6240458A (en) | Exposing method for thin film pattern | |
| JPH06105686B2 (en) | Method for manufacturing semiconductor device | |
| US3551176A (en) | Method for providing holes in glass | |
| JPS59232423A (en) | Pattern formation | |
| JPH11204414A (en) | Pattern formation method | |
| JP2001168096A (en) | Method of forming wiring pattern | |
| JPH02137224A (en) | Formation of fine pattern | |
| JPH04179124A (en) | Manufacture of semiconductor device | |
| JPH04349461A (en) | Photomask | |
| JPH0713955B2 (en) | Method for manufacturing semiconductor device | |
| JPS6032203A (en) | Method of patterning transparent thin film | |
| JPH01149435A (en) | Manufacture of semiconductor device | |
| JPS61129848A (en) | Manufacture of semiconductor device | |
| JPH04257238A (en) | Manufacture of semiconductor device | |
| JPS5984550A (en) | Manufacture of semiconductor device | |
| JPH03173181A (en) | Manufacture of photoconductive infrared detector | |
| JPH0282527A (en) | Manufacture of semiconductor device | |
| JPS58196035A (en) | Formation of electrode for semiconductor element | |
| JPS58153495A (en) | Production of ribbon diaphragm | |
| JPS6343347A (en) | Manufacture of semiconductor device | |
| JPH0468531A (en) | Manufacture of semiconductor device | |
| JPH0479213A (en) | Manufacture of semiconductor device | |
| JPS6187332A (en) | Manufacture of semiconductor device |