JPS6187332A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6187332A JPS6187332A JP20913684A JP20913684A JPS6187332A JP S6187332 A JPS6187332 A JP S6187332A JP 20913684 A JP20913684 A JP 20913684A JP 20913684 A JP20913684 A JP 20913684A JP S6187332 A JPS6187332 A JP S6187332A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- metal
- pattern
- chemical etching
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000003486 chemical etching Methods 0.000 claims abstract description 11
- 238000000206 photolithography Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005516 engineering process Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 1
- 230000007261 regionalization Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 150000002739 metals Chemical class 0.000 abstract description 3
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N phosphoric acid Substances OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、シリコン集積回路等の半導体装置の製造方法
に係り、特にアルミニクム（Ａｔ）等のメタルのフォト
リソグラフィ技術による微細加工に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing semiconductor devices such as silicon integrated circuits, and particularly to microfabrication of metals such as aluminum (At) by photolithography technology.
第２図Ｃ：従来のフォトリソグラフィ技術による微細パ
ターン加工方法の１つである９フトオフ法を示す。図Ａ
でシリコン基板１上（二、フォトリングラノイ技術によ
り、フォトレジストのパターン２を形成し、図Ｂでその
上に真空蒸着法等により全面ｌ二Ａｔ等のメタル３を付
着させる。次に図Ｃでレジストはぐり液等ζ二より、フ
ォトレジストを除去し、同時にフオトレジスト膜２上の
Ａ１４のメタル３も除去する。このとき残存しているＡ
１４のメタル３が所望の配線等のパターンとなっている
。FIG. 2C: shows the 9-foot-off method, which is one of the micropattern processing methods using conventional photolithography technology. Diagram A
A photoresist pattern 2 is formed on the silicon substrate 1 (2) using the photoresist technique, and a metal 3 such as At is deposited on the entire surface using a vacuum evaporation method as shown in Figure B. At C, the photoresist is removed using a resist stripping solution, etc., and at the same time, the metal 3 of A14 on the photoresist film 2 is also removed.At this time, the remaining A
The 14 metals 3 form a pattern of desired wiring, etc.
る。Ru.
第３図に他の従来のフォトリソグラフィ技術による微細
パターン形成技術の化学エッチ法を示す。FIG. 3 shows another conventional chemical etching method for forming fine patterns using photolithography.
図Ａでシリコン基板１上に、全面（二真空ρに着法等イ
ニよりＡＩ等のメタル３を付着する。図Ｂでフォトリソ
グラフィ技術により、フォトレジスト２のパターンを形
成する。図ＣでＡｔ等のメタル６の露出部を化学エツチ
ング（９ン酸等によるウェットエッチ又はＣＣｔ、ガス
等によるドライエラｙ″）により除去する。最後（二、
フォトレジスト２を除去することにより、図Ｄｔ二示す
７３１１等のメタル６の所望のパターンが得られる。In Figure A, a metal 3 such as AI is deposited on the entire surface of the silicon substrate 1 (in a two-vacuum ρ method, etc.). In Figure B, a pattern of photoresist 2 is formed by photolithography technology. In Figure C, a pattern of photoresist 2 is formed by photolithography. The exposed parts of the metal 6, etc., are removed by chemical etching (wet etching with 9-phosphoric acid, etc., or dry etching with CCt, gas, etc.).Finally (2,
By removing the photoresist 2, a desired pattern of the metal 6, such as 7311 shown in FIG. Dt2, is obtained.
ところが、上述の各フォトリソグラフィ技術１ユおいて
は、フォトレジスト膜゛のパターンを形成する際、フォ
トマスクのきず又はウェハ上へのゴミの付着等Ｃ：より
、フォトレジストのパターン間にブリッジが起こりやす
い。そのため、リフトオフ法においては、メタルの断線
がおこり、化学エッチ法においてはメタルのショートが
おこり易く、歩留りが低下する。However, in each of the above-mentioned photolithography techniques, when forming the pattern of the photoresist film, bridges are formed between the photoresist patterns due to scratches on the photomask or adhesion of dust on the wafer. It's easy to happen. Therefore, in the lift-off method, metal disconnection occurs, and in the chemical etching method, metal short-circuiting tends to occur, resulting in a decrease in yield.
本発明に３いては、シリコン集積回路等の半導体装置の
製造（二おいてアルミニクム等のメタルを微細パターン
に加工する場合、以下の■〜■の工程３有する。In the third aspect of the present invention, when manufacturing a semiconductor device such as a silicon integrated circuit (second step), when processing a metal such as aluminum into a fine pattern, the following steps 1 to 3 are included.
■ 予め所定のメタルのパターン間に位置する場所に、
フォトレジスト等のパターンを形成しておく。■ At the location between the predetermined metal patterns,
A pattern of photoresist or the like is formed in advance.
■ その後、シリコン基板上全面に、真空蒸着法等によ
りメタルを付着する。(2) Thereafter, metal is deposited on the entire surface of the silicon substrate by vacuum evaporation or the like.
■ 通常の化学エッチ法により、所望のメタルパターン
を形成する。■ Form the desired metal pattern using standard chemical etching methods.
■ 最後（二■のフォトレジストを除去することにより
、■で部分的に残存するメタルのブリッジのうちフォト
レジスト上に存在するメタルも同時に除去する。すなわ
ち、部分的に残存するメタルブリッジを切断する。■ By removing the photoresist at the end (2), the metal existing on the photoresist among the partially remaining metal bridges in (■) is also removed at the same time. In other words, the partially remaining metal bridges are cut off. .
第１図Ａにおいて、シリコン基板１１上にフォトリング
ラフィ技術によりフォトレジスト１２のパターンを形成
する。第１図Ｂｌ：おいて、真空蒸着等Ｌ：よりＡｔ等
のメタル１６をシリコン基板全面に形成する。＄１図Ｃ
において、上記シリコン基板上に、再びフォトリソグラ
フィ技術により、フォトレジスト１４（第２のフォトレ
ジスト）のパターンを形成する。このフォトレジスト１
４のパターンは、最終的に得たいメタルのパターンに対
応するものであり、図Ａのフォトレジスト１２のパター
ンは、第２のフォトレジスト１４のパターンの間に位置
するものとなる。図りにおいて、化学エッチ法によりフ
ォトレジスト１４のパターンに対応してメタル１３をエ
ツチングする。最後に図Ｅでフォトレジスト１２及び１
４を除去する。In FIG. 1A, a pattern of photoresist 12 is formed on a silicon substrate 11 by photolithography technology. In FIG. 1, a metal 16 such as At is formed on the entire surface of the silicon substrate by vacuum evaporation or the like. $1 Diagram C
Then, a pattern of photoresist 14 (second photoresist) is formed on the silicon substrate again by photolithography. This photoresist 1
The pattern 4 corresponds to the metal pattern that is desired to be finally obtained, and the pattern of the photoresist 12 in FIG. A is located between the patterns of the second photoresist 14. In the drawing, the metal 13 is etched in accordance with the pattern of the photoresist 14 using a chemical etching method. Finally, in Figure E, photoresists 12 and 1
Remove 4.
本発明によれば、マスクのきず又はウェハ上へのゴミの
付着等によりフォトレジスト１４のパターン間にブリッ
ジが生じた場合、化学エツチング法によりメタルをエッ
チした直後は、メタルのショートが起っているが、次工
程でフォトレジスト１２を除去すると、フォトレジスト
１２上のメタルも同時（＝除去されるため、メタルのシ
ョートがなくなる。また、リフトオフ法を採用していな
い為メタルの断線もおこりにくい。According to the present invention, if a bridge occurs between the patterns of the photoresist 14 due to a flaw in the mask or dust adhering to the wafer, a short circuit in the metal will occur immediately after the metal is etched by the chemical etching method. However, when the photoresist 12 is removed in the next process, the metal on the photoresist 12 is also removed at the same time, eliminating metal short-circuits.Also, since no lift-off method is used, metal disconnections are less likely to occur. .
第１図Ａ、Ｅは本発明の実施例の製造工程図、第２図Ａ
−Ｃは従来のりフトオフ法の製造工程図、
第５図Ａ−Ｄは従来の化学エッチ法の製造工程図。
１１・・・シリコン基板
１２・・・（第１の）フォトレジスト
１３・・・（ＡＩ等の）メタルFigures 1A and E are manufacturing process diagrams of embodiments of the present invention, Figure 2A
-C is a manufacturing process diagram of the conventional lift-off method, and FIGS. 5A to 5D are manufacturing process diagrams of the conventional chemical etching method. 11...Silicon substrate 12...(first) photoresist 13...Metal (such as AI)
Claims (1)
用いた半導体装置の製造方法において、予め、最終的に
得べきメタルのパターン間に位置する半導体基板上にフ
オトレジストのパターンを形成しておき、その後該半導
体基板上全面にパターニングすべきメタルを付着し、そ
の後化学エッチングにより該メタルを所望のパターンに
形成し、その後前記フォトレジストを除去することによ
り、前記化学エッチングにおいて部分的に残存するメタ
ルのブリッジのうち前記フォトレジスト上に存在するメ
タルも同時に除去する工程を有することを特徴とする半
導体装置の製造方法。In a semiconductor device manufacturing method using a fine pattern formation method using photolithography technology, a photoresist pattern is formed in advance on a semiconductor substrate located between the metal patterns to be finally obtained, and then the semiconductor By depositing a metal to be patterned on the entire surface of the substrate, forming the metal into a desired pattern by chemical etching, and then removing the photoresist, some of the metal bridges partially remaining in the chemical etching are removed. A method for manufacturing a semiconductor device, comprising the step of simultaneously removing metal present on the photoresist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20913684A JPS6187332A (en) | 1984-10-05 | 1984-10-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20913684A JPS6187332A (en) | 1984-10-05 | 1984-10-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6187332A true JPS6187332A (en) | 1986-05-02 |
Family
ID=16567887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20913684A Pending JPS6187332A (en) | 1984-10-05 | 1984-10-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6187332A (en) |
-
1984
- 1984-10-05 JP JP20913684A patent/JPS6187332A/en active Pending
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