JPH02134913A - Scanning latch circuit with setter - Google Patents

Abstract

PURPOSE:To reduce the number of ECL circuits and to operate a circuit with a single clock by inputting a reference voltage, the latch output from a first ECL circuit, and a set signal to OR inputs of an output-side current switching path of a second ECL circuit and constituting a scan circuit of a third ECL circuit. CONSTITUTION:A latch circuit is provided with two level shift type ECL circuits 13 and 14, and the current switching path of a third ECL circuit 15 constituting the scanning circuit is directly coupled to the latch circuit. Level shift type ECL circuits 13, 14, and 15 are used to perform the operation with the ternary logic, and the latch circuit where two ECL circuits 13 and 14 are subjected to crossing feedback is used, and the latch circuit with setter and the scanning circuit are combined to obtained complementary data input parts. Thus, the scanning latch circuit with setter is realized which is operated with the single clock and has a smaller number of gates.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a scan latch circuit with a set used for testing or diagnosing LSI logic circuits and control circuits.

The aim is to realize a set scan latch circuit that operates with a single clock and has a small number of gates.

Consisting of a latch circuit and a scan circuit, the latch circuit has two level shift type ECL circuits, and the clock, clock enable, and input data are input to the OR input of the input side current switching path of the first ECL circuit. The clock, clock enable, and inverted input data are input to the logical sum input of the input side current switching path of the second ECL circuit, and the reference input is input to the logical sum input of the output side current switching path of the first ECL circuit. The voltage and the latch output from the second ECL circuit are input, and the reference voltage, the latch output from the first ECL circuit, and the set signal are input to the logical sum input of the output side current switching path of the second ECL circuit. was input, and the current switching path of the third ECL circuit constituting the scan circuit was directly coupled to the latch circuit.

[Industrial Application Field] The present invention is applicable to test 1 of LSI logic circuits and control circuits.
~Or it relates to a scan latch circuit with a set used for diagnosis, and is especially incorporated into an LSI circuit using an ECL (current switching logic circuit), selected by an address, and scan-in and scan to write and read a status value. Out (Scan IN/5can 0U
The present invention relates to a T) type set scan latch circuit.

[Conventional technology]

An outline of a conventional scan latch circuit will be explained with reference to FIGS. 5 and 6.

In FIG. 5, 1 is an LSI circuit; 2. 3. 4
1 is a scan latch circuit built into the LSI circuit 1, 5 is a common scan-in signal line for setting test state values in each scan latch circuit, and 6 is a common line for taking out the state values of each scan latch circuit. The scan-out signal line 7 is for selecting each scan latch circuit (selecting one scan latch in the LSI and enabling scan-in to that latch, or enabling scan-out reading of the latch state). This is an address line.

During the operation of the LSI circuit 1, the scan latch circuits 2, 3.4 sequentially take state values based on their original control functions or logic functions.

Each of these scan latch circuits 2, 3, and 4 has a unique address, and when a scan address is given from the address line 7 when collecting diagnostic data, one scan latch circuit, 7,000 circuits, corresponding to the given address is selected. is,
The state value is read out to the scan-out signal line 6.

Furthermore, when a test state value is applied to the scan-in signal line 5, that state value is set in the scan operation latch circuit whose address has been selected. In addition to this, the LSI circuit l is
It can be operated from any control or logic state.

FIG. 6 shows a specific example of a conventional scan latch circuit.

In FIG. 6, 8 is a latch, 9 and 10 are 3-input NOR gates, 11 and 12 are decoders, S of latch 8 is a set input, R is a 2-bit latch selection signal for reset, AO to A5 are 6 This is a bit address signal.

The 6-bit address signal is divided into the lower 3 bits AO to A2 and the upper 3 bits A3 to A5 and sent to the decoder 11 respectively.
．． 12 is input.

Decoders 11, 12 each convert the 3-bit address input into a 1 out of 8 output signal. These decoders 11
．． By selecting and combining different output signals for each latch from each of the 12 output signals, it is possible to create 2-bit latch selection signals (for example, 64 types of latch selection signals from the 6-bit address signal shown in the figure). It is possible to scan up to 64 latches.

Both of these latch selection signals ADI and AD2 are
0” (D and CNOR'r'-) 9.10 opens.

Inverting the respective inputs Sl, Q, Sl, S
Output as O. This SI is applied to the S input of latch 8 to set the state of latch 8 to a desired value.

All latches in the LSI are subject to this selective scan-in S.
By applying a positive pulse (J'L) to the common sensor I/input RESET before performing I, all RESET (Q
- preprocessed to “0”) state. Also, the SO of the selected latch is scanned out.

Problems to be solved by the invention C] In the conventional scan latch circuit, the scan-in signal Sl
Two gates were required for each latch in order to control the gates of and scan alarm 1 to signal SO, respectively. This has been a factor in increasing the amount of hardware in the LSI circuit and increasing costs. Furthermore, conventional latch circuits require two types of clocks, positive and negative, and the stability of circuit operation may be impaired due to a phase shift between the clocks.

An object of the present invention is to realize a scan latch circuit with a set that operates with a single clock and has a small number of gates.

[Means to solve the problem]

The present invention uses a level shift 1-type ECl-circuit to
By operating with value logic, the number of gates is reduced, and by using a latch circuit with feedback applied to the two ECL circuits, a complementary data input section is realized, and a single clock It allows the use of

The present invention is particularly implemented in a combination of a latch circuit with set and a scan circuit.

The basic structure of the present invention will be explained using the specific example shown in FIG.

In FIG. 1, 13 and 14 are ECL circuits forming a latch circuit, and 15 is an ECL circuit forming a scan circuit.
It is a circuit.

In addition, T1 to T21 are transistors, R1 is input data 5, D is inverted input data, VBB is a reference voltage, and S
ET is a signal to sensor 1, Q is a latch output, Q is an inverted latch output, ADI and AD2 are latch selection signals, SI is a scan-in signal, T is a scan-out signal, VER
, VT represents the power supply voltage, and GND represents the ground.

Each of the ECL circuits 13 to 15 is a level shift type ECL circuit that does not have a common resistance between the two current switching paths and GND. The high level of the signal output from the transistors forming the right current switching path (for example, T5 and T6) is higher than the high level of the signal input to T4. As a result, the ECL circuits 13 to 15
For example, it operates using three-value logic.

FIG. 2 shows the levels of each signal used in the nine circuits.

The low side level VOL is common to each signal, but there are two types of high side levels: ■○H and VOH'.CEI, CR2, C
LK, D, D, and Sl each have a level of V○■4, and Q, Q, 5ETADI, and AD2.5OUT each have a level of VOH' slightly higher than V01-1.

Returning to FIG. 1, in the ECL circuit 13, 11'1 to T4 are connected in parallel to form a logical sum input,
It forms a current switching path on the input side of the L circuit. T5 and T6 are also connected in parallel to form a logical sum input and form a current switching path on the output side.

Similarly, T8 to Tll and T12 to T14 of the ECL circuit 14. Sarani E CI-Circuit]! M)'r17 to T20 each constitute a logical sum input.

The ECL circuit 13 and the ECL circuit 14 have a 'T'6. ]'14 and emitter follower T7. Feedback is applied to the cross-over via T15, thereby realizing a latch.

Each input side current switching path of the ECL circuits 13 and 14 includes a clock enable CEI, CE2 and a clock CL.
K is commonly applied to the ECL circuit 13, and input data D is applied to the ECL circuit 13, and inverted input data D is applied to the ECL circuit 14.

These CEI, CR2, CLK are all 0FF (VOL
It has a sampling function that reads the value of D into the latch at the time of leveling.

As shown in Figure 2, Q, Q, SET
VOH' is the VO of CEI, CR2, CLK, D, D
Since it has a higher level than H, the transistor to which VOH' is input is turned on unconditionally, and its ECL
Preferentially controls the logic of the circuit.

In the ECL circuit 15 of the scan circuit, the scan-in signal Sl is input to T16 forming the input side current switching path, and the collector of T16 is connected to T5. T
It is connected so as to share the load resistance R2 with the collector of No. 6 (so-called collector dot connection).

Also, T17. which constitutes the output side current switching path of the ECL circuit 15. T18. T19. T20 includes latch selection signals ADI, AD2 . Latch output Q, VB
The base of the emitter follower T21 is connected to the commonly connected collectors of T17T1B and T19, and the scan-out signal 5OUT is taken out.

As shown in Figure 2, all of the high side registers of SI are OF.
F (VOL) to TI7. T18. Both T19 are O
T16 can be turned on when it is FF.

When T16 turns ON, the collector becomes VOL and E
Since the base of the emitter follower T7 of the CL circuit 13 is set to VOL, Q=VOL.

The latch circuit can be set to the Q-VOH' state.

Further, if Sl is VOL and ADI and AD2 are also VOL, the state of the ECL circuit 15 is controlled by the level of Q, so that state, that is, the value of VOL or VOH' of Q is outputted from T21 as 5OUT.

[For production]

The operation of the circuit of the present invention shown in FIG. 1 will be explained using the timing chart shown in FIG. In the figure, ■ to [phase] indicate waveforms for each signal type + tI to 1B indicate operation timing.

First, set the latch between tl and t4.

Next, scan out the latch and then scan it in.

During this operation, the OR of CEI/CE2 in ■ is ON (VO
H), and the clock CLK of ■ is invalidated.

tl: Set signal SET to set all latches
is set to VOH', the latch circuits of ECL circuits 13 and 14 are set, and Q and Q become as shown in ■ and ■.

t2 Set target latch ADI/AD2 to VOL for scan-in and scan-out.

As a result, the scan out signal 5OUT of ■ becomes VOH'
becomes.

t3 Set the Niscan-in signal Sl to VOH.

This sets the latch circuit and Q.

Q changes as shown in ■ and ■. Also, 5OUT is VO
It becomes H'.

t4: Return AD1/AD2 to VOL and end the scan-in and scan-out operations.

[Phase] will be described later.

The next period from t5 to t8 shows normal latch operation.

t5: CE1/CE2 OR is set to VOL, clock C
Enable LK. At this time, the value of input data D in ■ is V
OH (corresponds to logical value "1").

L6: CLK changes from VOH to VOL, and the value of D "1" is read into the latch.

t7: D changes from VOH to VOL (“’0”).

t8: cLK changes from VOH to V 01-, the value of D "0" is read into the latch, and the latch enters the set state.

〔Example〕

FIG. 4 shows a circuit according to an embodiment of the present invention. Reference numbers and symbols in the figures are commonly used in the circuit of FIG.

The circuit shown in FIG. 4 is a partial modification of the circuit shown in FIG. 1, and differs in the way the scan circuit is coupled to the latch circuit.

In FIG. 1, the latch output Q is input to T19 of the ECL circuit 15, but in the circuit of FIG. 4, the output side current switching path of the ECL circuit 15 is not connected to T17. Each collector of T18 and each collector of T1 to T4 forming the input side current switching path of the ECL circuit 13 constituting the latch circuit are coupled by common connection of R7, and the latch state is read out. .

According to such a circuit configuration, ADI and AD2 are V
When the level of OL is reached and the latch shown is selected, T17. Both T18 are turned off, and the base potential of the emitter follower T21 is determined by the potential Q2 at the common connection point of the collectors of T1 to T4. In other words, the latch output Q can be read. [Phase] in FIG. 3 indicates the scan-out signal 5OtJT in this case.

In addition, if it is desired to obtain the scan-out signal 5OUT corresponding to the latch output Q in FIG.
Change to the combination with Q2.

The state of the latch circuit may be read based on Q2.

The same scan-out signal can also be changed in the circuit shown in FIG. In this case, it becomes possible by setting the input to T19 as the 5 latch output Q.

〔Effect of the invention〕

According to the present invention, the number of ECL circuits used to configure the set scan latch circuit can be reduced to three, which can be significantly reduced compared to conventional circuits, and also uses a single clock. Therefore, high-speed logic circuits with good stability can be created.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the circuit of the present invention, FIG. 2 is a signal level diagram of the circuit of the present invention, FIG. 3 is a diagram showing a time chart of an example of the operation of the circuit of the present invention, and FIG. 4 is a diagram of the embodiment of the circuit of the present invention. Circuit diagram, 5th
The figure is a schematic explanatory diagram of a conventional scan latch circuit, and FIG. 6 is a circuit diagram of the conventional scan latch circuit. Q: Latch output Q: Inverted latch output AD1/AD2: Latch selection signal S Niscan-in signal 5OUT Niscan-out signal

Claims (1)

[Claims] Consisting of a latch circuit and a scan circuit, the latch circuit has two current switching paths on the input side and the output side, each having a plurality of OR inputs, and a latch connected to the current switching path on the output side. The input side current switching path of the first ECL circuit (13) includes two level shift type ECL circuits including an emitter follower for output and outputting a high side logic level higher than the input high side logic level. The clock, clock enable, and input data are input to the OR input of the second ECL circuit (1
The clock, clock enable, and inverted input data are input to the logical sum input of the input side current switching path of 4), and the reference voltage and the logical sum input of the output side current switching path of the first ECL circuit (13) are input. Second ECL circuit (14)
and the latch output from the second ECL circuit (14
) is configured to input the reference voltage, the latch output from the first ECL circuit (13), and the set signal to the OR input of the output side current switching path, and the scan circuit inputs the scan-in signal. a third ECL including an input current switching path for outputting a scan-out signal; an output current switching path having a logical OR input of a reference voltage and a latch selection signal; and an emitter follower for outputting a scan-out signal connected to the output current switching path. Circuit (1
5), the output of the input current switching path of the third ECL circuit (15) is directly coupled to the output of the input current switching path of the first ECL circuit (13) of the latch circuit, and the scan circuit A scan latch circuit with a set, characterized in that a latch state of a latch circuit is input to an output side current switching path of the circuit.