JPH02134917A - Ecl master slave latch circuit - Google Patents

Abstract

PURPOSE:To obtain an ECL master slave latch circuit which has a few number of gates and is operated with a single clock by operating ECL circuits with the ternary logic. CONSTITUTION:Level shift type ECL circuits 11, 12, and 13 are used and are operated with the ternary logic, and a master latch circuit where two ECL circuits 11 and 12 are subjected to crossing feedback is used to obtain complementary data input parts. That is, two level shift type ECL circuits 11 and 12 are used and crossing feedback is performed between respective output-side current switching paths to constitute a latch of the ternary logic, and this latch is coupled to a slave latch consisting of the single ECL circuit 13. Thus, the ECL master slave latch circuit is realized which has a few number of gates and is operated with the single clock.

Description

[Detailed Description of the Invention] [Summary] Regarding the BCL master/slave latch circuit configured using ECL gates, the ECL master/slave latch has fewer data than conventional circuits and operates with a single clock. In the ECL master-slave latch circuit, the master latch has two current switching paths on the input side and output side, each including an OR connection of a predetermined number of transistors, and an emitter follower transistor for output extraction. It consists of
Two level shift type ECL circuits are used to output a signal with a higher level on the high side than the high level of the input signal to the input side current switching path from the output side current switching path.

By performing cross-over feedback between the respective output side current switching paths, a three-value logic latch was constructed, and a slave latch consisting of a single ECL circuit was coupled to this.

[Industrial application field]

The present invention relates to an ECL mask slave latch circuit configured with ECLOR gates.

When master and slave latches are configured using gates of ECL (current switching logic) circuits, the number of gates is generally quite large, which limits the scale of logic functions that can be accommodated in one LSI circuit.

The present invention provides a master slave latch circuit with a small number of gates by performing ternary logic using a level shift type ECL circuit.

[Prior Art] FIG. 6 is a logic circuit diagram of a conventional mask-slave latch circuit configured using gates of an ECL circuit, where 1 is a master latch and 2 is a slave latch.

3 is an OR gate, 4 is an OR/NOR gate, 5 is a collector-dot AND gate, and 6 to 8 are NOR gates.

Here 3. 4. All of the 6 to 8 gates can be constructed from ordinary ECLOR/NOR circuits. In addition, the AND gate 5 of the collector dots is connected (coupled between collectors).
It is realized only by

In Fig. 6, gates 3 to 6 are mask clutch 1.
, and the gates 7 and 8 constitute the slider 2.

Next, the operation will be briefly explained.

Data D is transmitted to mask latch 1 along with negative clock CLK.
is input to OR gate 3 of Note that the negative clock CLK is also input to the NOR gate 6 and the NOR gate 7 of the slave latch 2.

As a result, when master latch 1 is CLK-"O",
Take in the value of D and hold it. On the other hand.

When CLK="1", the slave latch 2 takes in the value of the output Q of the mask latch 1 and holds it.

In the mask latch 1, when D changes from "O" to "l", D-"1" is taken in through the AND gate 5 and held. At this time.

The Q-"0" output from OR/NOR gate 4 is.

It is input to the NOR gate 8 of the slave latch 2.

Slave latch 2 is 5LQ-“l” when CLK="0"
” and hold “l”. D changes from “1” to “0”.
The operation when changing to ” is also similar.

[Problem to be solved by the invention]

Conventional master/slave latch circuits using ECL circuits require a large number of ECLOR gates due to their configuration, which increases the circuit scale to achieve the desired logic function. This poses a problem in that the number of gates limits the logical scale that can be realized, resulting in poor implementation efficiency and increased costs.

Furthermore, in the conventional mask slave latch circuit.

Since clocks CLK and CLK with both positive and negative polarities are used, C
A driver is required to generate LK and CLK, and a delay time difference occurs between CLK and CLK on the wiring, which may make the latch operation unstable.

An object of the present invention is to realize an ECL master/slave latch circuit that has a smaller number of gates than conventional circuits and operates with a single clock.

[Means to solve the problem]

The present invention reduces the number of gates by operating in three-value logic using a level shift type ECL circuit, and also by using a master latch circuit that performs cross-over feedback on two ECL circuits, complementary This enables the use of a single clock.

The basic structure of the present invention will be explained using a specific example shown in FIG.

In FIG. 1, 11 and 12 are ECL circuits forming a master latch circuit, and 13 is an ECL circuit forming a slave latch circuit.

Also, T1 to T19 are I-transistors, R1 to R
IO is a resistor, i is a constant current source, CE is a clock enable, CLK is a clock, D is input data, D is inverted input data, VBB is a reference voltage, RESBT is a cent signal,
SET is Sen1~Signal.

Qm represents a master latch output, Qm represents an inverted master latch output, Qs represents a slave latch output, VER and VT represent a power supply voltage, and GND represents a ground.

Each of the ECL circuits 11 to 13 is a level shift type ECL circuit that does not have a common resistance between the two current switching paths and GND.

The higher level of the signal input to the transistors (for example, T1 to T3) constituting the current switching path on the left side of the figure is higher than the level of the signal input to the current switching path on the right side (for example, T4
The high-side level of the signals output from the transistors configuring T6 to T6) is high. As a result, the ECL circuits 11 to 13 operate in three-value logic.

FIG. 2 shows the levels of each signal used in the two circuits.

The low side level VOL is common to each signal, but there are two types of high side levels: VOH and VOH'.

CB, CLK, D, and D each have a level of VOH, and Qm, Qm, Qs, RESET, and SET each have a level of VOH' slightly higher than VOH.

Returning to FIG. 1, in the ECL circuit 11, T1 to T3 are connected in parallel and form a logical OR dog J.
It forms a current switching path on the input side of the L circuit. Further, T4 to T6 are also connected in parallel to form a logical sum input and form a current switching path on the output side.

Similarly, T8 to TIO and Tll to 'T'13 of the ECL circuit 12. Furthermore, T15, T16, T17, and T18 of the ECL circuit 13 also constitute OR inputs, respectively.

The ECL circuit 11 and the ECI-circuit 12 have their T6. T13 and emitter follower T7. Feedback is applied to the cross-over via TI4, thereby realizing a latch.

A clock enable CB is commonly applied to each input side current switching path of the ECL circuits 11 and 12.
Further, input data D is applied to the ECL circuit 11, and inverted input data D is applied to the ECL circuit 12. These are C
It has a sampling function that reads the value of D into the latch when both E and CLK are OFF (turns on when the VOL level is set).

As shown in FIG. 2, Qm, QmRESET,
SET's VOH' is CE, CLK.

Since it has a higher level than the VOH of D and D, VOH'
The transistor to which is input is turned on unconditionally and controls the logic of that ECL circuit preferentially.

As a result, for example, in the ECL circuit 11.

RESET=VOL is given to T5, Qm-V○L is given to T6, and T5. When T6 is OFF (non-conducting), T1. T2. When the VOH level is applied to any one base of T3, it becomes Qm - V OH'.

However, if RESET=VOH' is given to T5 or Qm = VOH' is given to T6, VOH<V
Since OH', T5. T6 becomes ON (conducting) unconditionally, and at this time T1. If either base of T2T3 goes to VOH, that transistor cannot turn on.

This also applies to the ECL circuit 12 when SET to T12 or Qm to T13 becomes VOH'.

In other words, VOH' of Qm, Qm, RESET, SET
is E CL than D, D, CLK, CE V OH
Three-valued logic predominately governs the operation of the circuit.
7' On the other hand, V OH of D or D is valid when both CE and CLK are ■○L, but the input side current switching path is turned ON in the ECL circuit where VOH' is not input to the output side current switching path. (V
Since OH>VBB).

As a result, the master latch consisting of ECL circuits 11 and 12 can be set or reset by setting either SET or RESET to VOH', and input data D can be written using a single clock CLK. be made into

, the inverted master latch output Qm is coupled to T18 of the output side current switching path of the ECL circuit 13 of the slave latch, and the slave latch output Qs of the emitter follower T19 is divided by resistors R9 and R10, and the input side current It is fed back to the switching path 715. These resistors R9 and RIO are connected to the level VOH't-VOH of Qs.
Convert the level to .

The ECL circuit 13 reads and latches Qm when CLK is VOH. In other words, when CLK=V○H, if Qm=VOH', T15
．． T16 remains OFF and this state is latched. Also, if Qm-VOL when CLK=VOH,
T16 is ON, T17T18 is OFF, Qs=
VOH', and this state is latched.

[For production]

The operation of the circuit of the present invention shown in FIG. 1 will be explained using the time chart shown in FIG. In the figure, ■ to ■ indicate the type of signal, and t to t indicate the operation timing.

tI = When the cent signal SET is set to VOH', Qm =
VOL, Qm=VOH', and the master latch is sent.

t2: When the recent signal RESET is set to VOH', Qm-VOL, Qm=VOH', and the master latch and slave latch are reset.

t3: Cloth clock CLK is supplied, but it is not valid because clock enable CB is VOH.

ta:cE becomes VOL and CLK is enabled.

ts: cLK falls from VOH to VOL, D value VO
H is taken into the master latch.

t6: cLK rises, and since it is Qm-VOL at this time, the slave latch is sent by VOH of CLK,
Qs=VOH'.

t7: Data D changes to VOL.

te: CLK falls, D-VOL is read into the master latch, and Qm=VOH'.

tq:cLK rises, Qm - V OH' is read into the slave latch, and Qs=VOL.

〔Example〕

FIG. 4 shows an embodiment circuit of the present invention.

The illustrated embodiment circuit is a partial modification of the circuit of the present invention shown in FIG.

In FIG. 4, the transistor T18 for inputting the inverted mask latch output Qm provided in the ECL circuit 13 of the slave latch in FIG. 1 is removed and replaced with T17.
T8. of the master latch ECL circuit 12. T
9. It is directly connected to the common connection point of each collector of the TIO to perform a so-called collector dot connection. Note that C is a capacitor for stabilizing operation. Furthermore, the slave latch output Qs is added to T15 of the ECL circuit 13 without level conversion by resistor division.

As a result, Qm is applied to the base of the emitter follower T19 of the ECL circuit 13.

The operation is performed as follows.

When CLK is VOL, T17 is OFF and the base of T19 changes depending on Qm. That is, at this time Q
If m=V○H', then Qs=VOH' and 71
Turn 5 ON and this state will be changed to 7. Also CLK
If it is Qm-VOL when is VOL, it becomes Qs-VOL and T15 is also turned off, and this state is latched.

FIG. 5 is another variation of the circuit of the invention shown in FIG. 1, and shows a non-bell-shifted ECL circuit 13' used in place of the ECL circuit 13 of FIG.

In the ECL circuit 13' of FIG. 5, a common resistor R1,1 for the two current switching paths is provided on the collector side, and Q
Set the high side level of s to VOH. Therefore, the level conversion resistor RIO, which was necessary in the circuit of FIG. 1, is no longer necessary in the circuit of FIG.

〔Effect of the invention〕

According to the present invention, a basic ECL master slave latch circuit can be constructed using three ECL circuits and can be operated using only a single clock.

Therefore, compared to conventional circuits, the number of gates is significantly reduced and one circuit is simplified, making it possible to increase the logic scale that can be accommodated in one LSI circuit. Furthermore, since it can operate with a single clock, it is possible to improve the stability of high-speed operation.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the circuit of the present invention, FIG. 2 is a signal level diagram of the circuit of the present invention, FIG. Example circuit diagram,
FIG. 5 is a circuit diagram of a modified example of the circuit of the present invention, and FIG. 6 is a logic circuit diagram of a conventional mask slave latch circuit. In Fig. 1, 11 to 13: ECL circuit CE: Cloth enable CLK: Clock D Dual input data D: Inverted input data RESET: Resent signal SET: Set signal Qm: Master rasoch output Qm Bi-inverted master latch output QS Nisleh latch output

Claims (1)

[Claims] In the ECL master-slave latch circuit, the master latch consists of two current switching paths on the input side and the output side, each including an OR connection of a predetermined number of transistors, and an emitter follower transistor for output extraction. Become,
Two level shift type ECL circuits are used to output a signal with a high level higher than the high level of the input signal to the input current switching path from the output current switching path, and between the respective output current switching paths. The slave latch is configured as a three-value logic latch by performing cross-over feedback, and the slave latch has two current switching paths, an input side and an output side, which include an OR connection of a predetermined number of transistors at least on the input side, and an output side. It is configured as a latch by using an ECL circuit consisting of an emitter follower for taking out and performing feedback from its output side to its input side, and a single An ECL master slave latch circuit characterized by inputting a clock.