JPH02134914A - Scanning latch circuit with resetter - Google Patents

Abstract

PURPOSE:To reduce the number of ECL circuits and to operate a scanning latch circuit with a single clock by inputting a reference voltage and the latch output from a first ECL circuit to OR inputs of the output-side current switching path of a second ECL circuit and constituting a scanning circuit of a third ECL circuit. CONSTITUTION:A latch circuit is provided with two level shift type ECL circuits 13 and 14, and the scanning circuit consists of a third ECL circuit 15, and the current switching path is directly coupled to the latch circuit. Level shift type ECL circuits 13, 14, and 15 are used to perform the operation with the ternary logic, and the latch where two ECL circuits are subjected to crossing feedback is used, and the latch circuit with reset and the scanning circuit are combined to obtain complementary data input parts. Thus, the scan latch circuit with resetter is realized which is operated with the single clock and has a smaller number of gates.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a scan latch circuit with reset used for testing or diagnosing LSI logic circuits and control circuits.

The aim is to realize a scan latch circuit with reset that operates with a single clock and has a small number of gates.

Consisting of a latch circuit and a scan circuit, the latch circuit has two level shift type ECL circuits, and the first
The clock, clock enable, and input data are input to the logical sum of the input side current switching path of the second ECL circuit, and the clock, clock enable, and inverted input are input to the logical sum input of the input side current switching path of the second ECL circuit. data, the reference voltage, the latch output from the second ECL circuit, and the reset signal are input to the logical sum input of the output side current switching path of the first ECL circuit, and the second
The reference voltage and the latch output from the first ECL circuit are input to the OR input of the output side current switching path of the CL circuit, and the scan circuit is configured to input the latch output from the first ECL circuit.
Consists of circuits.

The current switching path was coupled directly to the latch circuit.

[Industrial application field]

The present invention relates to a scan latch circuit used for testing or diagnosing LSI logic circuits and control circuits, and in particular, it is incorporated into an LSI circuit using ECL (current switching logic circuit) and is selected by an address. Resettable scan in, scan out (Scan IN/5can) to write and read status values
01lT) type scan latch circuit.

[Conventional technology]

An outline of a conventional scan latch circuit will be explained with reference to FIGS. 5 and 6.

In FIG. 5, 1 is an LSI circuit; 2. 3. 4
is a scan latch circuit built into the LSI circuit 1, 5 is a common scan-in signal for setting test state values in each scan latch circuit, and 6 is a common scan-in signal for taking out the state value of each scan latch circuit. The scan out signal 7 is an address for selecting each scan latch circuit (selecting one scan latch in the LSI and making it possible to scan in to that latch or read out the state of that latch). be.

During the operation of the LSI circuit 1, the scan latch circuits 2, 3.4 sequentially take state values based on their original control functions or logic functions.

These scan latch circuits 2, 3.4 each have a unique address, and when a scan address is given from the address line 7 when collecting diagnostic data, one scan latch circuit corresponding to the given address is selected. The state value is read out to the scan-out signal line 6.

Furthermore, when a test state value is applied to the scan-in signal line 5, that state value is set in the scan operation latch circuit whose address has been selected. In addition to this, the LS1 circuit 1 is
It can be operated from any control or logic state.

FIG. 6 shows a specific example of a conventional scan latch circuit.

In FIG. 6, 8 is a latch, 9 and 10 are three-man NOR gates, 11 and 12 are decoders, S of latch 8 is a set input, R is a 2-bit latch selection signal for reset input, and AO to A5 are 6 This is a bit address signal.

The 6-bit address signal is divided into the lower 3 bits AO to A2 and the upper 3 bits A3 to A5 and sent to the decoder 11 respectively.
．． 12 is input.

Decoders 11, 12 each convert the 3-bit address input into a 1 out of 8 output signal. These decoders 11
．． A 2-bit latch selection signal (for example, ALII and AIJ2 shown in the figure) is selected and combined from each of the 12 output signals for each latch.
Create.

It is possible to create 64 types of latch selection signals from a 6-bit address signal, and therefore it is possible to scan up to 64 latches.

Both of these latch selection signals ADI and AD2 are '0'.
”, the NOR games 1 to 9.10 open and invert the respective inputs SI and Q to generate sr and s.

Output as . This Sl is applied to the S input of latch 8 and sets the state of latch 8 to a desired value.

Note that all latches in the LSI receive a positive pulse (
By applying 几), all RESET(Q−“′O”)
preprocessed to state. Also, the SO of the selected latch is
Scan out output.

[Problem to be solved by the invention]

In the conventional scan latch circuit, the scan-in signal SI
Two gates were required for each latch in order to control the gates of I, scan array I, and signal SO, respectively. For this reason, the amount of hardware for the LS1 circuit has increased, and this has been a factor in increasing costs. Furthermore, conventional latch circuits require two types of clocks, positive and negative, and the stability of circuit operation may be impaired due to a phase shift between the clocks.

An object of the present invention is to realize a scan latch circuit with reset that operates with a single clock and has a small number of gates.

[Failure to solve the problem]

The present invention uses a level shift type ECL circuit to operate with three-value logic to reduce the number of data points, and also uses a latch circuit with feedback applied to the two ECL circuits. This provides complementary data inputs and allows the use of a single clock. The present invention is particularly realized in a combination of a latch circuit with reset and a scan circuit.

The basic structure of the present invention will be explained using a specific example shown in FIG.

In FIG. 1, 13 and 14 are ECL circuits forming a latch circuit, and 15 is an ECL circuit forming a scan circuit.

Also, T1 to T21 are transistors R1 to R8
is the resistance, i is the constant current source, VBE and VT are the current and voltage,
CEI and CB2 are clock enable, CLK is clock, D is input data D is inverted input data, VBB is reference voltage, RESET is reset signal, Q is launch output, Q is inverted latch output, ADI and AD2 are latch selection signals, SI represents a scan-in signal, 5OUT represents a scan-out signal, VER and VT represent a power supply voltage, and GND represents a ground.

Each of the ECL circuits 13 to 15 is a level shift type ECL circuit that does not have a common resistance between the two current switching paths and GND.

The higher level of the signal input to the transistors (for example, T1 to T4) constituting the current switching path on the left side of the figure is
The high-side level of the signals output from the transistors configuring T7 to T7) is high. As a result, the ECL circuits 13 to 15 operate in three-value logic.

FIG. 2 shows the levels of each signal used in the two circuits.

The low side level VOL is common to each signal, but there are two types of 7 high side levels: VOH, VOH', CEl, CB2. C
LK, D, D, and Sr each have a VOH level,
Q, Q, RESET ADI, AD2, and 5OUT each have a level of VOH' slightly higher than VOH.

Returning to FIG. 1, in the ECL circuit 13, T1 to T4 are connected in parallel and form a logic circuit.
It forms a current switching path on the input side of the L circuit. Further, T5 to T7 are also connected in parallel to form a logical sum input and form a current switching path on the output side.

Similarly, T9 to TI2, T13 and T14 . Furthermore, T17 to T20 of the ECL circuit 15
also constitute a logical sum input.

The ECL circuit 13 and the ECL circuit 14 have their T7. Feedback is applied to the cross-over via T14 and the emitter follower TO, T15, thereby realizing a latch.

Each input side current switching path of the ECL circuits 13 and 14 includes a clock enable CEI, CE2 and a clock CL.
K is commonly applied to the ECL circuit 13, and input data D is applied to the ECL circuit 13, and inverted input data D is applied to the ECL circuit 14.

These are CEI, CB2. CLK is all 0FF (VOL
It has a sampling function that reads the value of D into the latch when the D level changes.

As shown in Figure 2, Q, Q, RE
SET VOH' is CEI, CB2. CLK, D.

Since it has a higher level than VOH of D, the transistor to which VOH' is input is unconditionally turned on, and preferentially controls the logic of the ECL circuit.

In the ECL circuit 15 of the scan circuit, the scan-in signal SI is input to T16 forming an input side current switching path, and the collector of T16 is connected to T13.
It is connected so as to share the collector of T14 and the load resistor R5 (so-called collector dot connection).

Also, T17. which constitutes the output side current switching path of the ECL circuit 15. T18. T19. T20 respectively have latch selection signals ADI, AD2 . Latch output Q and VBB are input, and T17. The emitter follower T21 is connected to the commonly connected collectors of TlB and T19, and the scan-out signal 5OUT is taken out.

As shown in Fig. 2, the SIO high side is adjusted and the OF
T17 in F (VOL). Both TlB and T19 are O
T16 can be turned on when it is FF.

When T16 turns ON, the collector becomes VOL and E
The base of the emitter follower T15 of the CL circuit 14 is set to VOL.
Since it is Q-VOL.

The latch circuit can be set to the Q-VOH' state.

Also, if Sl is VOL and ADI and AD2 are also VOL, the state of the ECL circuit 15 is controlled by the level of Q, so that state, that is, the inverted value of Q, is 5OUT from T21.
is output as

[For production]

The operation of the circuit of the present invention shown in FIG. 1 will be explained using the timing chart shown in FIG. In the figure, ■ to ■ indicate waveforms for each signal type, and tI to t8 indicate operation timings.

First, the latch is reset between tl and t4, and the latch is first scanned out and then scanned in. During this operation, the OR of CEI/CE2 in ■ is ON (VOH'
), and the clock CLK of ■ is invalidated.

tl: Reset signal R to reset all latches
ESET is set to VOH', the latch circuits of the ECL circuits 13 and 14 are reset, and Q and Q become as shown in (1) and (2).

tt Set target latch ADI/AD2 to VOL for scan-in and scan-out.

This causes the scan out signal 5OUT to become VOH'
becomes.

t3 Set the Niscan-in signal St to VOH.

As a result, the latch circuit is set and the IQ+ page changes as shown in ■ and ■. Further, 5OUT becomes VOL.

t,: Return AD1/AD2 to VOL, scan in,
Finish the scanout operation.

The next period from t5 to t6 shows a normal latch operation.

t5: Set CEI/CE2(7)OR to vOL and enable clock CLK. At this time, the value of the input data D of ■ is VOL (corresponding to the logical value "0").

t6: CLK changes from VOH to VOL, and the value of D "0" is read into the latch.

t, , :D changes from VOL to VOH (“1”).

t,: CLK changes from VOH to VOL, and D
The value "1" is read, and the latch becomes set.

〔Example〕

FIG. 4 shows an embodiment circuit of the present invention. The reference numbers and symbols in the figures are the same as those in the circuit of FIG. 1.

The circuit shown in FIG. 4 is a partial modification of the circuit shown in FIG. 1, and differs in the way the scan circuit is coupled to the latch circuit.

In FIG. 1, the latch output Q is input to T19 of the ECL circuit 15 forming the scan circuit, but in the circuit of FIG. 4, the latch output Q is input to T17. Each collector of T18 and the T that forms the input side current switching path of the ECL circuit 14 that constitutes the latch circuit.
R7 is commonly connected to the respective collectors of T1 to T4, and the latch state is read out.

According to such a circuit configuration, ADI and AD2 are V
When the level of OL is reached and the latch shown is selected, T17. Both TI8 are turned off, and the base potential of the emitter follower T21 is determined by the potential Q2 at the common connection point of the collectors of TI to T4. In other words, the output Q can be read out.

In addition, if it is desired to obtain the scan-out signal 5OUT corresponding to the latch output Q in FIG.
The state of the latch circuit may be read based on Q2 instead of coupling with Q2.

The same scanout signal modification can also be made with the circuit of FIG. In this case, it becomes possible by setting the input to T19 as the 7 latch output Q.

〔Effect of the invention〕

According to the present invention, the number of ECl circuits used to configure the scan latch circuit with reset can be reduced to three, which can be significantly reduced compared to conventional circuits, and since a single clock is used, High-speed logic circuits with good stability can be created.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the circuit of the present invention, FIG. 2 is a signal level diagram of the circuit of the present invention, FIG. 3 is a diagram showing a time chart of an example of the operation of the circuit of the present invention, and FIG. 4 is a diagram of the embodiment of the circuit of the present invention. Circuit diagram, 5th
The figure is a schematic explanatory diagram of a conventional scan latch circuit, and FIG. 6 is a circuit diagram of the conventional scan latch circuit. 13.14, 15: ECL circuit CEI/CE2: Clock enable CLK: Clock D Two-man power data D Two-inverting input data RESET: Reset signal Q: Launch output Q: Inverting latch output S ■ Niscan-in signal sou”r Niscan out signal

Claims (1)

[Claims] Consisting of a latch circuit and a scan circuit, the latch circuit has two current switching paths on the input side and the output side, each having a plurality of OR inputs, and a latch connected to the current switching path on the output side. The input side current switching path of the first ECL circuit (13) includes two level shift type ECL circuits including an emitter follower for output and outputting a high side logic level higher than the input high side logic level. The clock, clock enable, and input data are input to the logical OR of the second ECL circuit (14).
The clock, clock enable, and inverted input data are input to the OR input of the input current switching path of the first ECL circuit (13), and the reference voltage and the second The latch output and reset signal from the second ECL circuit (14) are input, and the second EC
The reference voltage and the latch output from the first ECL circuit (13) are configured to be input to the logical sum input of the output side current switching path of the L circuit (14), and the scan circuit is configured to input the scan-in signal. an output current switching path having a logical OR input of a reference voltage and a latch selection signal; and an emitter follower connected to the output current switching path for outputting a scan-out signal. ECL circuit (
15), furthermore, the output of the input side current switching path of the third ECL circuit (15) of the scan circuit is directly coupled to the output of the output side current switching path of the second ECL circuit (14) of the latch circuit, Further, a scan latch circuit with reset is characterized in that a latched state of a latch circuit is coupled to an output side current switching path of the scan circuit.