JPH02134846A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH02134846A JPH02134846A JP28946788A JP28946788A JPH02134846A JP H02134846 A JPH02134846 A JP H02134846A JP 28946788 A JP28946788 A JP 28946788A JP 28946788 A JP28946788 A JP 28946788A JP H02134846 A JPH02134846 A JP H02134846A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- terminals
- logic function
- integrated circuit
- twice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に論理機能ブロック
を有する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having logical function blocks.
従来の論理機能ブロックを内蔵する半導体集積回路の例
について図面を用いて説明する。An example of a semiconductor integrated circuit incorporating a conventional logic function block will be described with reference to the drawings.
第3図は従来の半導体集積回路の論理機能ブロック部分
の配線図である。FIG. 3 is a wiring diagram of a logic function block portion of a conventional semiconductor integrated circuit.
第3図において、IC,2C,3C,4Cはそれぞれ論
理ブロックCの入出力端子で、その間隔はいづれも配線
ピッチの2倍より小さい。LD。In FIG. 3, IC, 2C, 3C, and 4C are input/output terminals of logic block C, and the interval between them is less than twice the wiring pitch. L.D.
2D、3D、4D、5Dはそれぞれ論理ブロックDの入
出力端子で、その間隔はいづれも配線ピッチの2倍より
小さい。2D, 3D, 4D, and 5D are input/output terminals of the logic block D, and the intervals therebetween are all smaller than twice the wiring pitch.
今、端子ICとID、2Cと2D、3Cと3D、4Cと
4Dの間をそれぞれ配線し、端子5Dを他の論理機能ブ
ロック(図示せず)の端子と配線する時、第3図に示す
様に、配線−本の折れ曲がりに対して配線トラック−つ
を割当てていた。Now, when wiring between terminals IC and ID, 2C and 2D, 3C and 3D, and 4C and 4D, respectively, and wiring terminal 5D with a terminal of another logic function block (not shown), as shown in Fig. 3. Similarly, one wiring track was assigned to each bend in a wiring book.
上述した従来の論理機能ブロックの入出力端子間隔は、
特に配線ピッチの2倍以上という約束ごとで配置されて
いないので、配線ピッチの2倍以下となっている入出力
端子は、接続される配線が折れ曲がる時、他の配線と配
線トラック4を共有できず、論理機能ブロック間の配線
チャネルが大きくなり、チップサイズの増大を招くとい
う欠点がある。The input/output terminal spacing of the conventional logic function block mentioned above is
In particular, since they are not arranged according to a convention of at least twice the wiring pitch, input/output terminals whose pitch is less than twice the wiring pitch cannot share the wiring track 4 with other wiring when the connected wiring bends. First, there is a drawback that the wiring channels between logical function blocks become larger, leading to an increase in chip size.
本発明は、半導体基板上に複数個の素子により構成され
た論理機能ブロックが形成され、各論理機能ブロックの
入出力端子間を配線して成る半導体集積回路において、
前記論理機能ブロックの入出力端子間を配線ピッチの2
倍以上に隔てるようにしたものである。The present invention provides a semiconductor integrated circuit in which a logic function block composed of a plurality of elements is formed on a semiconductor substrate, and wiring is made between input and output terminals of each logic function block.
The wiring pitch between the input and output terminals of the logic function block is 2.
It was designed to be more than twice as far apart.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の第1の実施例を示す論理機能ブロック
間の配線図である。FIG. 1 is a wiring diagram between logical function blocks showing a first embodiment of the present invention.
LA、2A、3A、4Aは論理機能ブロックAの入出力
端子、IB、2B、3B、4B、5Bは論理機能ブロッ
クBの入出力端子で各々隣りの端子とは配線ピッチの2
倍の距離だけ離れている。LA, 2A, 3A, and 4A are input/output terminals of logic function block A, and IB, 2B, 3B, 4B, and 5B are input/output terminals of logic function block B.
It's twice as far away.
1は第1層配線、2は第2層配線、3は第1N配線と第
2M配線を接続するスルーホールである。1 is a first layer wiring, 2 is a second layer wiring, and 3 is a through hole connecting the first N wiring and the second M wiring.
今、端子IAとIB、2Aと2B、3Aと3B、4Aと
4Bを接続し、端子5Bと他の機能ブロック(図示せず
)を接続しようとする時、端子間に縦方向配線トラック
4を割当てられるので図に示す様に、2A−2B間、3
A−3B間の配線を交差させ、2A−2B間の配線の横
方向配線トラックを4A−4B間の距離の横方向配線ト
ラックと共有させることができる。またIA−18間の
横方向配線トラックを3A−3B間の配線の配線トラッ
クと共有させることができる。使用配線トラック数は2
である。Now, when connecting terminals IA and IB, 2A and 2B, 3A and 3B, 4A and 4B, and connecting terminal 5B to another functional block (not shown), vertical wiring track 4 is connected between the terminals. As shown in the figure, between 2A and 2B, 3
The wiring between A and 3B can be crossed, and the horizontal wiring track of the wiring between 2A and 2B can be shared with the horizontal wiring track of the distance between 4A and 4B. Further, the horizontal wiring track between IA and 18 can be shared with the wiring track between 3A and 3B. Number of wiring tracks used is 2
It is.
第2図は本発明の第2の実施例の論理機能ブロック間の
配線図である。FIG. 2 is a wiring diagram between logical function blocks in a second embodiment of the present invention.
第2の実施例は、第1の実施例に比べ、論理機能ブロッ
クBの位置がずれて端子2B、3B。In the second embodiment, compared to the first embodiment, the position of the logic function block B is shifted and the terminals 2B and 3B are located.
4Bが論理機能ブロックAの端子IA、2A。4B are terminals IA and 2A of logic function block A.
3AとX座標が同じである点が異なる。The difference is that the X coordinate is the same as 3A.
この様に上下のブロックの端子位置が揃っている場合で
も、第2図に示す様に、端子2A−2B、3A−3Bを
結ぶ配線を配線トラック2本を使うことにより、全体で
も2本の配線トラック使用で済ます事ができる。Even when the terminal positions of the upper and lower blocks are aligned in this way, as shown in Figure 2, by using two wiring tracks to connect terminals 2A-2B and 3A-3B, there are only two wires in total. You can get away with using a wiring track.
以上説明したように、本発明は、論理機能ブロックの入
出力端子間隔を配線ピッチの2倍以上に設定することに
より、端子間に配線トラックを割当てられ、横方向の配
線トラックの共有化が図れ、配線チャネル幅を最小にす
ることができるという効果を有する。As explained above, in the present invention, wiring tracks can be allocated between terminals by setting the input/output terminal spacing of a logic function block to at least twice the wiring pitch, and horizontal wiring tracks can be shared. This has the effect that the wiring channel width can be minimized.
5B、IC−4C,ID−5D・・・入出力端子。5B, IC-4C, ID-5D... Input/output terminal.
Claims (1)
能ブロックが形成され、各論理機能ブロックの入出力端
子間を配線して成る半導体集積回路において、前記論理
機能ブロックの入出力端子間を配線ピッチの2倍以上に
隔てたことを特徴とする半導体集積回路。In a semiconductor integrated circuit in which a logic function block composed of a plurality of elements is formed on a semiconductor substrate, and the input and output terminals of each logic function block are wired, the wiring pitch between the input and output terminals of the logic function block is A semiconductor integrated circuit characterized by being separated by at least twice the distance.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28946788A JPH02134846A (en) | 1988-11-15 | 1988-11-15 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28946788A JPH02134846A (en) | 1988-11-15 | 1988-11-15 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02134846A true JPH02134846A (en) | 1990-05-23 |
Family
ID=17743652
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28946788A Pending JPH02134846A (en) | 1988-11-15 | 1988-11-15 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02134846A (en) |
-
1988
- 1988-11-15 JP JP28946788A patent/JPH02134846A/en active Pending
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