JPS62291136A - Wiring method for integrated circuit - Google Patents

Abstract

PURPOSE:To alleviate the complexity of a wiring route and to further reduce wiring regions by wiring only by first layer wiring in a logic function block, and wiring between the blocks by second and third layer wirings. CONSTITUTION:A diffused layer 1, a polysilicon 2, a first layer wiring 3 and a connecting hole 4 for connecting the layer 1 with the polysilicon 2 and the wiring 3 are formed in a logic function block, and external input/output terminal point 5 is set at the position of the lattice point 10 of the wiring track of a lattice pattern of a predetermined pitch P predetermined in both horizontal and vertical directions with respect to a logic function block origin 7. The second and third layer wirings are disposed along the lattice line 12 necessary for the wiring track of the temporary lattice pattern, and wired between the blocks. Thus, the complexity of the wirings between the blocks can be reduced, and since the second and third layer wirings can be formed by freely passing over the blocks to some degree, the designing term and the designing mistake can be reduced.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a wiring method for a semiconductor integrated circuit having a three-layer metal wiring structure.

[Conventional technology]

Conventional semiconductor integrated circuits, especially semiconductor integrated circuits such as general-purpose one-chip microprocessors, have a one-layer or two-layer metal wiring structure due to the difficulty of manufacturing three-layer metal wiring layers on a semiconductor substrate. was the mainstream.

[Problem that the invention seeks to solve]

When designing a general-purpose one-chip microprocessor using the conventional one-layer or two-layer wiring technology described above, it is currently necessary to minimize the chip area and increase speed.
There is no choice but to create two-layer and two-layer wiring. When attempting to design a general-purpose one-chip microprocessor, etc. using the three-layer wiring technology using the manual design method described above, in addition to the complexity of the conventional wiring route, the number of wiring layers increases by I Jiii. The complexity of the interconnection is intertwined, which increases the complexity of the design, prolongs the design period, and increases the number of design errors. There was a drawback that the reduction could not be achieved.

[Means for solving problems]

To wire a semiconductor integrated circuit using the three-layer wiring structure of the present invention, the inside of the logic function block is implemented using only the first layer wiring, and the wiring between the logic function blocks is performed using the second and third layer wiring. The second and third layer wirings are carried out using arbitrary grid lines of wiring tracks that create a grid pattern wiring route with a predetermined partial pitch. By connecting the wires, the complexity of the wiring route is reduced, and the wiring area is also made more compact.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1 to 4 are plan views for fully explaining an embodiment of the present invention. FIG. 1 is a mask pattern diagram of a logical functional block of the present invention. In FIG. 1, the logic function block includes a diffusion layer 1, polysilicon 2, first layer wiring 3,
The diffusion layer 1, the polysilicon 2, and the first layer interconnection 3 are connected to each other through a connection hole 4, and the logic function block origin 7 is formed in advance in both the horizontal and vertical directions as shown in FIG. An external person sets an output terminal point 5 at the position of a grid point 10 of a grid pattern wiring track with a predetermined partial pitch P. FIG. 2 is a chip configuration diagram in which the origin 7 of each of the plurality of logic function blocks 9 is arranged with respect to the chip origin 11 at an arbitrary lattice center 10 of the lattice pattern with a partial pitch P shown in FIG. It is. FIG. 3 is a part of the chip configuration diagram of FIG. 2, and is a configuration diagram in which wiring tracks are arranged in a lattice pattern at a constant pitch P. FIG. 4 shows how the second layer wiring 13 and the third layer wiring 14 are arranged along the necessary grid lines 12 of the virtual grid pattern wiring track shown in FIG. This is the wiring result.

〔Effect of the invention〕

As explained above, the present invention designs a logic function block in a semiconductor integrated circuit having a three-layer wiring structure using only the first layer wiring, and furthermore, the input/output terminal positions are arranged on grid pattern wiring tracks with a constant pitch. The inside of the chip is configured with such multiple logic function blocks, and the wiring between the logic function blocks is set at an arbitrary grid point position that virtually covers the entire chip surface. By using a wiring method that connects the second and third layer wiring by cutting out the necessary parts of the pattern wiring track, it is possible to reduce the complexity of the wiring between logical function blocks, and to connect the logical function blocks. Since the 2nd and 3rd layer wiring can pass over the block freely to some extent, the design period can be lengthened and design errors can be reduced, making it possible to create a design that takes full advantage of the advantages of the 3-layer wiring structure. effective.

[Brief explanation of drawings]

FIG. 1 is a mask pattern diagram of a logic function block according to an embodiment of the present invention, FIG. 2 is a chip configuration diagram according to an embodiment of the present invention, and FIG. 3 is an example of the chip configuration diagram of FIG. 2. FIG. 4 is a plan view showing a state in which lattice pattern wiring tracks with a partial pitch are arranged in a section, and FIG. 4 is a wiring configuration diagram between logical function blocks according to an embodiment of the present invention. 1.-diffusion layer, 2.. polysilicon, 3.. first layer metal scrap wiring, 4.. connection hole, 5.. input/output terminal, 7.
・Logic function block origin, 8・Chip peripheral area, 9・
...Logic function block, 10.. Grid point, 11.. Chip origin, 12.. Grid line, 13.. Second layer wiring, 14.
...Third layer wiring. X X
X

Claims (1)

[Claims] The wiring of a semiconductor integrated circuit in which a plurality of logical function blocks each having a plurality of transistors are formed on one semiconductor substrate is arranged in three layers from the bottom: the first layer, the second layer, and the third layer. (a) The wiring within each of the logical function blocks described above is performed using the wiring of the first layer, and the origin of each of the functional blocks and the position of the external input/output terminal are set within the board. Placement at any grid point on a predetermined predetermined pitch grid pattern wiring track that defines the wiring route. (b) The connection wiring between each functional block through the input/output terminals of each functional block uses the wiring of the second and third layers, and these wirings are any arbitrary wires taken out from the wiring track. Do it along the grid lines. An integrated circuit wiring method characterized by: