JPH02134844A - Method for dicing semiconductor wafer - Google Patents

Method for dicing semiconductor wafer

Info

Publication number
JPH02134844A
JPH02134844A JP63289436A JP28943688A JPH02134844A JP H02134844 A JPH02134844 A JP H02134844A JP 63289436 A JP63289436 A JP 63289436A JP 28943688 A JP28943688 A JP 28943688A JP H02134844 A JPH02134844 A JP H02134844A
Authority
JP
Japan
Prior art keywords
dicing
semiconductor wafer
wafer
pellet
pellets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63289436A
Other languages
Japanese (ja)
Inventor
Fumimaro Ikeda
池田 史麻呂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63289436A priority Critical patent/JPH02134844A/en
Publication of JPH02134844A publication Critical patent/JPH02134844A/en
Pending legal-status Critical Current

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  • Dicing (AREA)

Abstract

PURPOSE:To eliminate unnecessary dicing and reduce the time required for dicing by a method wherein positions of street lines including four sides around an acceptable pellet in a semiconductor wafer are calculated from the addresses and electrical characteristics data of the respective pellets in the semiconductor wafer which is diced along those street lines only. CONSTITUTION:In a dicing method by which a semiconductor wafer 2 is divided into individual pellets 3, positions of street lines 6 including four sides around an acceptable pellet 4 in the semiconductor wafer 2 are calculated from the addresses and electrical characteristics data of the respective pellets 3 in the semiconductor wafer 2 which are obtained in processes before a dicing process and the semiconductor wafer 2 is diced along only the street lines 6 including the four sides around the acceptable pellet 4. For instance, the wafer 2 is diced along the X- and Y-direction of the wafer 2 only at the positions of the street lines 6 including the four sides around the acceptable pellet 4. If one acceptable pellet 4 exists in the wafer 2, dicing lines 5 after dicing are as shown in the figure.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体ウェハを個々のペレットに分割する際
のダイシング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dicing method for dividing a semiconductor wafer into individual pellets.

〔従来の技術〕[Conventional technology]

従来、半導体ウェハ(以下ウェハと記す)を個々のペレ
ットに分割する際には、ダイシングステージ上のウェハ
を、カメラを用いた自動認識によりウェハを位置合せし
た後、高速回転するブレードを用いて、ウェハのX、Y
方向でペレット寸法に応じたストリートラインに沿って
、ウェハの端の方から順次ダイシングを行い、個々のペ
レットに分離していた。
Conventionally, when dividing a semiconductor wafer (hereinafter referred to as wafer) into individual pellets, the wafer is aligned on a dicing stage by automatic recognition using a camera, and then a blade rotating at high speed is used to separate the wafer into individual pellets. Wafer X, Y
Dicing was performed sequentially from the edge of the wafer along a street line corresponding to the pellet size in the direction, and the pellets were separated into individual pellets.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のダイシング方法は、ウェハ上のペレット
寸法に応じたストリートラインに沿って、ウェハ内のス
トリートラインの総てをダイシングしているために、良
品ペレットが少ない場合、又は、良品ペレットがウェハ
上で偏って存在する場合は、ダイシングを不要とするス
トリートラインが増加し、ダイシングにかかる不要な時
間が増加するという欠点がある。特に、近年の高集積化
及びウェハの大径化に伴い、大きな問題となっている。
In the conventional dicing method described above, all of the street lines in the wafer are diced along the street lines according to the pellet dimensions on the wafer. If they are present unevenly on the top, there is a disadvantage that the number of street lines that do not require dicing increases, and the unnecessary time required for dicing increases. In particular, this has become a big problem with the recent trend toward higher integration and larger wafer diameters.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、半導体ウェハを明々のペレットに分割するダ
イシング方法において、ダイシング工程以前の工程で得
られた半導体ウェハ内の各ペレットのアドレス及び電気
的特性データに基づいて前記半導体ウェハ内の良品ペレ
ット周囲囲の四辺を含むストリートライン位置を算出し
、このペレット周囲の四辺を含むストリーI・ラインの
みをダイシングする半導体ウェハのダイシング方法、及
び前記方法において、半導体ウェハ内の良品ペレット周
囲の四辺のみをダイシングする半導体ウェハのダイシン
グ方法である。
In a dicing method for dividing a semiconductor wafer into clear pellets, the present invention provides a dicing method for dividing a semiconductor wafer into clear pellets based on address and electrical characteristic data of each pellet in the semiconductor wafer obtained in a process before the dicing process. A semiconductor wafer dicing method in which the street line position including the four sides of the pellet is calculated and only the street line including the four sides around the pellet is diced, and in the method, only the four sides around the good pellet in the semiconductor wafer are diced. This is a method for dicing semiconductor wafers.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(^)、(B)はそれぞれ本発明の一実施例を説
明する平面図及び断面図である。ダイシングステージ1
上に搬送されたウェハ2は、カメラを用いて自動認識が
行われ、ウェハ2の位置補正が行われる。
FIGS. 1(^) and 1(B) are a plan view and a sectional view, respectively, illustrating an embodiment of the present invention. Dicing stage 1
The wafer 2 transported above is automatically recognized using a camera, and the position of the wafer 2 is corrected.

次に、前工程で得られているウェハ2内の各ペレット3
のアドレス及び電気的特性データを外部記憶装置又はホ
ストコンピュータより入力し、ストリートライン6の中
から良品ペレット4の周囲の四辺を含むストリートライ
ン位置を算出する。
Next, each pellet 3 in the wafer 2 obtained in the previous process
address and electrical characteristic data are input from an external storage device or host computer, and the street line position including the four sides around the good pellet 4 is calculated from among the street lines 6.

そして、この良品ペレット4の周囲の四辺を含むストリ
ートライン位置のみを、ウェハ2のX方向及びY方向で
ダイシングを行い、良品ペレット4のみをウェハ2から
分離する。第1図は、ウェハ2内に良品ペレット4が1
個存在した場合の、ダイシング後のダイシングライン5
を示す。
Then, only the street line position including the four sides around the good pellet 4 is diced in the X and Y directions of the wafer 2, and only the good pellet 4 is separated from the wafer 2. In FIG. 1, there is one good pellet 4 in the wafer 2.
Dicing line 5 after dicing if there are
shows.

なお、ウェハ内の同一ストリートラインに沿って、良品
ペレットが複数個存在する場合の共通するダイシングラ
イン及び良品ペレットが連続して存在する場合の共有す
るダイシングラインは、重複したダイシングを行わず、
1回のダイシングを行う。
Note that, along the same street line in the wafer, duplicate dicing is not performed on a common dicing line when there are multiple good pellets, and on a shared dicing line when there are consecutive good pellets.
Perform 1 dicing.

第2図(A)、(B)はそれぞれ本発明の他の実施例を
説明する平面図及び断面図である。ウェハ2内の良品ペ
レット4の周囲の四辺を含むストリートライン位置を算
出した後、良品ペレット4周囲の四辺上のX方向ストリ
ートライン位置にダイシングブレードを位置させ、ダイ
シングブレードを下降させ、ストリートラインに切り込
む。
FIGS. 2(A) and 2(B) are a plan view and a sectional view, respectively, illustrating another embodiment of the present invention. After calculating the street line position including the four sides around the good pellet 4 in the wafer 2, the dicing blade is positioned at the X direction street line position on the four sides around the good pellet 4, and the dicing blade is lowered to meet the street line. Cut in.

次に、ダイシングステージ1をペレット寸法と同距離だ
け駆動し、ダイシングを行い、ダイシングブレードを上
昇させる。同様の動作を良品ペレット4周囲の四辺のY
方向ストリーI・ライン上で行い、良品ペレット4のみ
をウェハ2から分離する。
Next, the dicing stage 1 is driven by the same distance as the pellet size to perform dicing, and the dicing blade is raised. Similar operation is performed on the four sides of the good pellet 4.
It is performed on the direction streak I line, and only the good pellets 4 are separated from the wafer 2.

ここで、良品ペレットが2個以上連続して存在する場合
は、共通のストリートラインを連続してダイシングし、
又、共有するストリートラインは、重複せず一回のダイ
シングを行う。
Here, if there are two or more good pellets in a row, dice the common street line continuously,
Also, shared street lines are diced once without duplication.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ウェハ上の良品ペレット
周囲のストリートラインのみをダイシングすることによ
り、不要なダイシングを省略できるため、ダイシング時
間が短縮できる。又、同時にダイシングブレードの消耗
量も少なくなり、ダイシングブレードの交換頻度が少な
くなる。
As described above, according to the present invention, unnecessary dicing can be omitted by dicing only the street lines around the good pellets on the wafer, thereby shortening the dicing time. Moreover, at the same time, the amount of wear of the dicing blade is reduced, and the frequency of replacing the dicing blade is reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)、(B)はそれぞれ本発明の一実施例を説
明する平面図及び断面図、第2図(A)、(B)はそれ
ぞれ本発明の他の実施例を説明する平面図及び断面図で
ある。 1・・・ダイシングステージ、2・・・ウェハ、3・・
・ペレット、4・・・良品ペレット、5・・・ダイシン
グライン、6・・・ストリートライン。
FIGS. 1(A) and (B) are a plan view and a sectional view, respectively, illustrating one embodiment of the present invention, and FIGS. 2(A) and (B) are plane views, respectively, illustrating another embodiment of the present invention. They are a figure and a sectional view. 1... Dicing stage, 2... Wafer, 3...
- Pellet, 4... Good pellet, 5... Dicing line, 6... Street line.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体ウェハを個々のペレットに分割するダイシ
ング方法において、ダイシング工程以前の工程で得られ
た半導体ウェハ内の各ペレットのアドレス及び電気的特
性データに基づいて前記半導体ウェハ内の良品ペレット
周囲の四辺を含むストリートライン位置を算出し、この
良品ペレット周囲の四辺を含むストリートラインのみを
ダイシングすることを特徴とする半導体ウェハのダイシ
ング方法。
(1) In a dicing method in which a semiconductor wafer is divided into individual pellets, the area around the good pellets in the semiconductor wafer is determined based on the address and electrical property data of each pellet in the semiconductor wafer obtained in a process before the dicing process. A method for dicing semiconductor wafers, which comprises calculating the street line position including the four sides and dicing only the street line including the four sides around the non-defective pellet.
(2)半導体ウェハ内の良品ペレット周囲の四辺のみを
ダイシングする請求項(1)記載の半導体ウェハのダイ
シング方法。
(2) The method for dicing a semiconductor wafer according to claim (1), wherein only the four sides around the good pellets in the semiconductor wafer are diced.
JP63289436A 1988-11-15 1988-11-15 Method for dicing semiconductor wafer Pending JPH02134844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63289436A JPH02134844A (en) 1988-11-15 1988-11-15 Method for dicing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63289436A JPH02134844A (en) 1988-11-15 1988-11-15 Method for dicing semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH02134844A true JPH02134844A (en) 1990-05-23

Family

ID=17743229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63289436A Pending JPH02134844A (en) 1988-11-15 1988-11-15 Method for dicing semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH02134844A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012099660A (en) * 2010-11-02 2012-05-24 Disco Abrasive Syst Ltd Chip segmentation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4891975A (en) * 1972-03-08 1973-11-29
JPS558072A (en) * 1978-07-03 1980-01-21 Mitsubishi Electric Corp Selection of semiconductor pellet
JPS62165963A (en) * 1986-01-17 1987-07-22 Matsushita Electronics Corp Manufacture of semiconductor integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4891975A (en) * 1972-03-08 1973-11-29
JPS558072A (en) * 1978-07-03 1980-01-21 Mitsubishi Electric Corp Selection of semiconductor pellet
JPS62165963A (en) * 1986-01-17 1987-07-22 Matsushita Electronics Corp Manufacture of semiconductor integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012099660A (en) * 2010-11-02 2012-05-24 Disco Abrasive Syst Ltd Chip segmentation method

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