JPS61229341A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To array all the cell blocks without any unavailable region by a method wherein, in the arrangement structure of cell block according to a building block system, the number of the parallel arrangement stages of the polycell-structure arrays of each cell block is properly modified and the configurations of the respective cell blocks are prescribed. CONSTITUTION:When blocks B1-B9, in each of which plural pieces of polycell- structure arrays C1-C5 are arrayed in parallel to one another across each wiring region L, are arrayed, the number of the parallel stages of the polycell- structure arrays belonging to each block is properly modified and the configurations of the respective blocks are prescribed. For example, when a block 8 and a block 9 are arranged, the numbers of the parallel stages of the polycell-structure arrays of the blocks 8 and 9 are respectively modified for eliminating an unavailable region I2 to generate on the boundaries of both of the blocks 8 and 9 and a block 5 and the configurations of the blocks 8 and 9 are modified so as to fill the above-mentioned unavailable region. Hereby the unavailable region to generate between each blocks is activated and the utilization efficiency of the substrate can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a cell block arrangement structure using a building block method, and particularly to a semiconductor integrated circuit having an efficient polycell arrangement structure.

(Prior Art) In a conventional polycell structure semiconductor integrated circuit based on the building block method, all cell blocks (hereinafter simply referred to as blocks) are arranged in a unified rectangular shape. That is, on one semiconductor substrate, rectangles formed in various sizes depending on the size of the blocks are arranged in combination with each other.

(Problem to be Solved by the Invention) However, when rectangles of various sizes are arranged in a defined semiconductor substrate area in this way, no cell array is formed at all no matter how effective the combination is. A remaining area is created. If this area is called an invalid area, this invalid area can be found in two locations: near the boundary between blocks and at the corner of the block itself. No cells are disposed within this invalid area, which is, so to speak, an idle area on the semiconductor substrate, which significantly reduces the utilization efficiency of the substrate surface. In other words, the size of the chip is made larger than necessary.

(Means for Solving the Problem) A semiconductor integrated circuit with a polycell structure array according to the present invention is a cell in which a polycell structure array of a plurality of logic circuit cells having different circuit functions is arranged in parallel in multiple stages. - Consisting of a plurality of arrays of blocks, each of the cell blocks defines its respective shape by selectively adjusting the number of parallel stages of the polycell structure array, and defines boundaries with respect to each other within a defined area of the semiconductor substrate. The arrangement includes being arranged in adjacent arrays that touch each other.

That is, according to the present invention, the shapes of the blocks are not unified into one rectangular shape as in the conventional art. In the block according to the present invention, the shape of each block is defined by appropriately changing the number of parallel stages of the polycell structure array belonging to the block. Here, changing the number of parallel stages does not necessarily mean that the number of cells arranged in one stage is always the same. That is, the shape of each block is defined by appropriately changing the number of cells included in each array stage of a polycell structure array arranged in parallel in a plurality of stages. Therefore, these blocks are modified from a one-dimensional rectangle to take on various deformed shapes. Typically, these transformation techniques are performed at boundaries with other adjacent blocks. That is,
Cells are transferred from one side of the adjacent ports to the ineffective areas created at the two locations already mentioned, and activation of this area is attempted. Therefore, if this deformation technique is repeated for each block in turn, almost all the blocks will be placed within the defined semiconductor substrate area, bordering each other, and the friend invalid area that always exists in the conventional layout structure. almost disappears.

The blocks whose shape has been determined by the above-described modification method are arranged so as to be in contact with each other on the boundary line, just like the picture blocks in a "hame" picture, so that the total area of the ineffective region on the semiconductor substrate is significantly reduced.

The present invention will be described in detail below with reference to the drawings.

(*Stream side) Figure wL1 is a block layout structure diagram showing an embodiment of the semiconductor integrated circuit of the present invention. In this embodiment, nine blocks 81 to B9 are included. Here, the numerical symbols written in each block are written for convenience in order to facilitate understanding. In each block, a plurality of polycell structure arrays C1-Cs are arranged in parallel with wiring areas in between, respectively, as shown in the example in which one block Bxt is selected. Naturally, the number of cells included in a block is determined by the size of the block. Since this block Bl has a short polycell structure array Cs, if the conventional method is followed, an invalid area will be generated between it and the block B6. However, this block 86 changes the number of cell arrangement stages within the block and performs cell relocation within this invalid area.
4 and activate this invalid area by defining the shape so that it touches the boundary line. Here, 11 indicates this activated invalid area.

In exactly the same way, invalid areas that occur near the boundaries between blocks of conventional rectangular blocks are also activated. For example, blocks 8 and 9 each perform cell relocation within the invalid area that occurs at the boundary with block 5, and define their shapes so that they are in contact with block 5, respectively, and
Activate each of these invalid areas. Here, I2 indicates this activated invalid area. As explained above, the activation of the nine invalid regions is repeated sequentially among all blocks, and the blocks B1 to B9 are each defined in a shape that touches the boundary line with each other, and are arranged adjacently within the defined nine semiconductor regions. be done.

FIG. 2 is a diagram showing an example of the chip structure of the semiconductor integrated circuit of the present invention, which is composed of nine blocks whose boundaries are in contact with each other, as in Figure @1. Here, P is a nine back electrode arranged at the periphery.

(Effects of the Invention) According to the present invention, almost all of the invalid regions that occur in conventional rectangular blocks are activated and used as cell formation regions, so the efficiency of semiconductor substrate usage can be significantly improved. .

FIG. 3 is a comparative structure diagram of a conventional block arrangement using rectangular blocks, showing how invalid areas 11 and I2 occur near the boundaries between blocks and inside pull blocks, respectively.

Since these invalid areas only increase the size of the chip in vain, the activation and utilization of the invalid areas according to the present invention can have a significant effect in reducing the size of the chip.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a block layout structure of one side of the semiconductor integrated circuit of the present invention, FIG. 2 is a diagram showing the chip structure of the semiconductor integrated circuit of the present invention, and FIG. 3 is a comparison of block layouts using conventional rectangular blocks. It is a structure side view. Bl~B9...Cell block, 01~CII
...Polycell structure arrangement, L...Wiring area% h I I2...Invalid area% II
+ ”2...Activated invalid area, P.
...Pad electrode.

Claims (1)

[Claims] It consists of a plurality of arrays of cell blocks each having a plurality of polycell structure arrays of logic circuit cells having different circuit functions arranged in parallel in a plurality of stages, each of the cell blocks having a polycell structure array of a plurality of logic circuit cells having different circuit functions. A semiconductor integrated circuit characterized in that the number of parallel stages is selectively adjusted to define the shape of each semiconductor integrated circuit, and the semiconductor integrated circuits are arranged in an adjacent array with boundary lines touching each other within a defined area of a semiconductor substrate.