JPH02132541A - Interruption controller - Google Patents

Abstract

PURPOSE:To reduce the chip size by transmitting the control signals outputted in response to the request signals given from a CPU to plural peripheral devices in a bus form. CONSTITUTION:The control signals CLEN outputted in response to the request signals given from a CPU 2 are transmitted to plural peripheral devices 22a - 22n in a bus form. When an interruption sequence of the CPU 2 carried out by an interruption request of a resource 22c, for example, is through, an interruption controller 20 outputs the control signal corresponding to a clear request to a decoder 23c as a resource number via lines 21b - 21f. At the same time, the controller 20 activates the signal CLEN and sends it to the decoder 23c. Thus the resource 22c is cleared based on the signal CLEN. In such a way, the control signals for cancel of the interruption are outputted to the resources 22a - 22n from the controller 20 in a bus form. As a result, many resources are treated with the small number of control lines. Then the number of control lines are extremely reduced and the chip size is reduced.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art (Figures 3 and 4) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems An Embodiment of the Invention ( Figures 1 and 2) Effects of the invention [Summary] Regarding an interrupt controller, it is an object of the present invention to provide an interrupt controller that can support a large number of peripheral devices with a small number of control lines and that can reduce the chip size. The purpose is to capture interrupt inputs IR Q+ -IR QR from multiple peripheral devices located outside the CPU, select one peripheral device, request an interrupt to the CPU, and when the CPU interrupt processing is completed. In an interrupt controller that receives a request signal from a CPU and outputs a control signal CLEN corresponding to the request signal to a peripheral device to control the peripheral device, the control signal CLEN output in response to the request signal from the CPU is provided. Configure it so that it communicates to multiple peripheral devices in bus format. [Industrial Application Field] The present invention relates to an interrupt controller, and more specifically, to a CPt controller.
The present invention relates to an interrupt controller that controls interrupts of peripheral devices that generate interrupts for J.

As the field of application for micro combiators expands, the demands on their functionality will inevitably increase, and as a result, new high-performance CPUs will appear one after another, while at the same time assisting the CPU to perform certain functions. Various dedicated LSIs, so-called peripheral chips, have been developed.

These chips include, for example, interrupt controllers and bus controllers directly related to the functionality of the CPU, as well as chips for communication, peripheral system control, and so on.

CPU support chips related to the CPU control circuit include clock generators, timer counters, DMA controllers, and interrupt controllers. This is a circuit for controlling the CPU's response to various events.This controller has two or more input pins that can be assigned to various events, and it is possible to set priorities among these human inputs.

In recent years, one-chip microcontrollers that implement interrupt controllers have become more multifunctional and faster, resulting in an increase in chimp size. However, there is a need to reduce the chip size from a cost perspective, and therefore it is necessary to simplify the circuits, wiring, etc. inside the chip as much as possible.

[Conventional technology]

Examples of conventional interrupt controllers include those shown in FIGS. 3 and 4. FIG. 3 is a diagram showing a control system of an interrupt controller for various peripheral devices. In this figure, 1a to 1n are peripheral devices having various functions, such as an I/O boat, a timer, an A/D converter, and the like. The peripheral devices 1a-In generate interrupts to the CPU 2 as necessary during data processing, and these interrupt requests are output as interrupt inputs to an interrupt controller (INTC) 4 through lines 3a-3n. The interrupt controller 4 outputs an interrupt request INT to the CPU 2 based on the interrupt input from the peripheral devices 1a to 1n, in accordance with the determination of the request destination, the priority order of interrupt permission, and the like.

The CPU 2 uses the interrupt request INT to start an interrupt sequence created by the user and performs various arithmetic processing, and when accepting an interrupt, interrupt permission INT is activated.
A is sent to the interrupt controller 4, and when the interrupt processing is completed, a clear request is output to the interrupt controller 4. When the interrupt controller 4 receives the interrupt permission INTA, it outputs the interrupt vector number etc. corresponding to the peripheral devices 13-in to the CPtJ2 through the bus 5, and
Bus 5 between U2 and any one of the peripherals Rla to In
Interrupt processing is executed by exchanging data, etc. via the . In addition, the interrupt controller 4
When a clear request is received from the PU 2, a control signal corresponding to the clear request is output to any one of the peripheral devices 1a-1n via lines 6a-6n to release the interrupt state.

Next, the detailed configuration of the interrupt controller 4 will be explained based on FIG. 4. In the figure, the interrupt controller 4 includes a latch 11, a mask circuit 12, a priority determination circuit 13,
It is composed of an encoder 14, a vector circuit 15, and a gate 16. Interrupt inputs from external peripheral devices 1a to 1n are input to the interrupt controller 4 through n lines, a latch 11 temporarily latches these interrupt inputs, and a mask circuit 12 masks specific interrupt inputs. . When there are a plurality of interrupt inputs, the priority determining circuit 13 selects the highest level interrupt, determines the priority, and outputs an interrupt request INT to the CPU 2. The encoder 14 encodes the interrupt input to generate a vector (interrupt vector number) and sends it to the vector circuit 15, and the vector circuit 15 outputs the generated vector to the bus 5. The gate 16 is a general gate, and when there is a clear request from the CPU 2, it outputs a clear request control signal to the peripheral devices 1a to 1n.

Note that interrupt permission INTA from CPU2 is latch 1.
1 and the vector circuit 15, and the latch 11
When the interrupt enable INTA is input, the vector circuit 15 latches the external interrupt input, and the vector circuit 15 inputs the interrupt enable INTA.
If there is an NTA, the generated vector is output. Also,
In the figure, n and m represent the number of wires, and n is the peripheral device 1a~
The same number of interrupt inputs from 1n, m is encoder 14
and the number of wires output from the vector circuit 15. There is a relationship n>m, for example, if n=8, m=
Set to 3.

Therefore, for the interrupt controller 4, the peripheral device 1
When there is an interrupt input from a-1 n, the mask circuit 12
The priorities of the interrupts are checked by the priority determination circuit 13, and the one with the highest priority is sent to the encoder 14 as the final interrupt input, and the interrupt request IN
T is sent to CPU2.

After that, a vector is generated by the encoder 14 based on the sent value, and the value is outputted to the bus 5 through the vector circuit 15, and sent from the bus 5 to the CPU 2, where one peripheral device is selected and interrupt processing is performed. is executed. In the case of this example, the circuit shown in FIG. 3 is assembled into one chip and integrated as a so-called one-chip microcoit roller.

[Problem to be solved by the invention]

However, such conventional interrupt controllers have a configuration in which a control signal corresponding to a clear request when canceling an interrupt is output for each individual peripheral device. If there are a large number of built-in peripheral devices, a large number of control signals will be output, and as a result, the inside of the chip cannot be simplified, and the chip size will increase due to the large number of control lines. There was a point.

Note that the above conventional example is a case in which the peripheral devices and CPU are integrated into one chip together with the interrupt controller, but even if only the interrupt controller is integrated into a single IC, the number of output pins corresponding to the control lines increases, so the same problem occurs. There is a problem.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an interrupt controller that can support a large number of peripheral devices with a small number of control lines and that can reduce the chip size.

[Means to solve the problem]

In order to achieve the above object, the interrupt controller according to the present invention takes in interrupt input IRQ, ~IRQ, from a plurality of peripheral devices arranged outside the CPU, selects one peripheral device, and requests an interrupt to the CPU, In an interrupt controller that receives a request signal from the CPU when the CPU interrupt processing is completed, and outputs a control signal CLEN corresponding to the request signal to the peripheral device to control the peripheral device,
The control signal CLEN output in response to a request signal from the CPU is configured to be transmitted to a plurality of peripheral devices in a bus format.

[Effect]

In the present invention, when there is a request signal from the CPU, a control signal for controlling the peripheral devices is transmitted to a plurality of peripheral devices in a bus format.

Therefore, in the bus format, for example, each peripheral device can be assigned a number and distinguished by that number, so when a request (request signal) to clear an interrupt cause is received from the CPU, the interrupt cause is cleared. (Control of peripheral devices)
It becomes possible to output the number of the desired peripheral device in a bus format, and it is possible to target a large number of peripheral devices with fewer control lines, thereby reducing the chip size.

[Embodiment] FIGS. 1 and 2 are diagrams showing an embodiment of an interrupt controller according to the present invention. In explaining this embodiment, the same components as those of the conventional example are designated by the same numbers, and the explanation thereof will be omitted.

FIG. 1 is an overall configuration diagram of a microcontroller to which an interrupt controller of one embodiment is applied, and the microcontroller in this case is applied to, for example, various arithmetic processing and control devices.

In FIG. 1, 20 is an interrupt controller, and the internal configuration of the interrupt controller 20 will be described in detail later.
A bus consisting of six lines 21a to 21f connects n peripheral devices (hereinafter simply referred to as resources) 22a to 22.
Connected to n. Interrupt requests from resources 22a to 22n are sent to interrupt controller 20 through lines 3a to 3n, as in the conventional example, and interrupt controller 20 receives IRQ. The number ~IRQn identifies which of the resources 22a to 22n the interrupt request is from. Further, the resources 22a to 22n are assigned numbers consisting of 5 bits as shown in the following table, and control signals corresponding to the numbers are sent from the interrupt controller 20 to the decoders 23a to 23n through lines 21a to 21f. Sent to the side.

Note that this resource number is RSNOO from the lower bit side.
~RSNO4.

Decoders 23a to 23 are installed at the terminals of lines 21a to 21f.
n are provided corresponding to the respective resources 22a to 22n, and the decoders 23a to 23n are connected to the lines 21a to 22n.
Analyzes the resource number sent from the interrupt controller 20 through 1r, outputs a signal to clear the interrupt to the corresponding one of the resources 22a to 22n, and outputs the signal CLEN sent from the interrupt controller 20. do. Resources 22a to 22n
learns that it is selected for clearing the interrupt factor based on the clear signal, and clears its own factor by activating the signal CLEN.

Next, the detailed configuration of the interrupt controller 20 will be explained using FIG. 2. In FIG. 2, the configurations of the latch 11, mask circuit 12, priority determining circuit 13, encoder 14, and vector circuit 15 are the same as in the conventional example, but the configuration related to the gate 24 is different. That is, the interrupt vector generated by the encoder 14 is input to the gate 24 through m signal lines, and the gate 24 selects the resources 22a to 22a whose interrupt is selected by the interrupt vector.
22n, it also accepts a clearing request from the CPU 2, and outputs the resource number for which the interrupt should be cleared and a signal CLEN to the resources 22a-22n through lines 21a-21f. In this case, line 21a~
The number of 21f is m trees. When signal CLEN becomes active, it clears the resources 22a-22n. Note that the interrupt vector number used is the same as the resource number.

Next, the effect will be explained.

While the CPU 2 is executing arithmetic processing, the external resource 22a
When an interrupt factor occurs in one of the resources 22n, for example, the resource 22c, an interrupt request from the resource 22c is sent to the interrupt controller 20 through the line 3C, and the interrupt controller 20 identifies the interrupt request corresponding to the line 3C. Determine from the number ■R Q z. Next, as in the conventional example, the interrupt controller 20 and the CPU
An interrupt request INT and an interrupt permission INTA are exchanged between the CPU 2 and the CPU 2 to execute an interrupt sequence.

After that, when the interrupt sequence in the CPU 2 ends, a clear request is sent from the CPU 2 to the interrupt controller 20.
The interrupt controller 20 outputs a control signal corresponding to the clear request as a resource number (00010) to the decoder 23c from lines 2lb to 21f, and activates the signal CLEN to output the control signal to the decoder 23c.
Output to. As a result, the decoder 23c analyzes the selection of the resource 22c from resource number 1:00010) and requests the resource 22c to clear the interrupt factor, and the resource 22c clears the interrupt factor based on the activated signal OLEH.

As described above, in this embodiment, a control signal corresponding to a clear request for canceling an interrupt is output from the interrupt controller 20 to each of the resources 22a to 22n in the form of a bus.

Specifically, when there are six lines 21a to 21f, one is used for the signal CLEN, and the remaining five are used for RSNOO-RS.
NO41. Since m corresponds to 5 bits and 7 bits, 25=3
2, n-32 resources, that is, resources 22a~
6 control lines (lines 21a to 21
f). Incidentally, in the conventional example, n-3
In the case of two, 32 control lines are required.

From the above, a large number of resources can be targeted with a small number of control lines, and the number of control lines can be significantly reduced compared to the conventional method. As a result, the interrupt controller 20
It is possible to reduce the chip size, including the size of the chip.

Note that in the above embodiment, the interrupt controller 20 and the CPU 2
This is an example in which all the resources 22a to 22n are integrated in the same chip.
Of course, it can also be applied when it is made into a single chip, and in this case, the number of output pins of control lines to resources is reduced,
Similarly, the effect of reducing the chip size can be obtained.

Further, in the above embodiment, the resource is controlled by clearing the interrupt factor, but other controls that reflect the function of the resource may be performed. For example, the resource is activated by activating the resource number without providing the signal CLEN. It may also be controlled.

In this case, the chip size can be further reduced compared to the above embodiment, for example, the number of resources can be reduced to 1.
If there are 5 control lines, 4 control lines (2'=1
6), and if the number of resources is 60, then 6
Instead of 0 control lines, only 6 (from 26=64) are required.

Furthermore, although a dedicated bus is provided to output the resource number, the number of control lines can be further reduced by outputting the resource number through a data path instead of a dedicated bus.

〔effect〕

According to the present invention, control signals corresponding to request signals can be sent to a large number of peripheral devices with a small number of control lines, and the size of a chip including an interrupt controller can be reduced.

[Brief explanation of drawings]

1 and 2 are diagrams showing one embodiment of the interrupt controller according to the present invention. FIG. 1 is an overall configuration diagram of a microphone port controller to which the interrupt controller is applied, and FIG. 2 is a block diagram of the interrupt controller. , FIG. 3 is an overall configuration diagram of a microcontroller to which a conventional interrupt controller is applied, and FIG. 4 is a block diagram of a conventional interrupt controller. 2...cpu, 3a-3n...line, 5...bus, 11...latch, 12...mask circuit, 13. ...Priority determining circuit, 14...Encoder, 15...Vector circuit, 20...Interrupt controller, 21a to 21f
... Line (control line), 22a to 22n...
...Resources (peripheral devices), 23a to 23n...
...Decoder, 24...Gate.

Claims (1)

[Claims] A plurality of peripheral devices (2) disposed outside the CPU (2).
Interrupt inputs IRQ_1 to IR from 2a) to (22n)
Q_n, select one peripheral device, and execute CPU (
2), and when the interrupt processing of the CPU (2) is completed, receives a request signal from the CPU (2), and outputs a control signal CLEN corresponding to the request signal to the peripheral devices (22a) to (22n). In the interrupt controller (20), which controls the peripheral devices (22a) to (22n), a control signal CLEN outputted in response to a request signal from the CPU (2) is transmitted to the plurality of peripheral devices (22a) to (22n). 22
An interrupt controller characterized in that the interrupt controller is configured to transmit information to the interrupt controller (21a) to (21f) in the form of buses (21a) to (21f).