JPS58114222A - Input/output device controlling system - Google Patents
Input/output device controlling systemInfo
- Publication number
- JPS58114222A JPS58114222A JP21460381A JP21460381A JPS58114222A JP S58114222 A JPS58114222 A JP S58114222A JP 21460381 A JP21460381 A JP 21460381A JP 21460381 A JP21460381 A JP 21460381A JP S58114222 A JPS58114222 A JP S58114222A
- Authority
- JP
- Japan
- Prior art keywords
- common
- input
- groups
- address
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Abstract
Description
【発明の詳細な説明】
(1)軸−の技術分舒
本発明は主処理装置の制御下にある複数の入出力装置に
対し各別の外グループ毎のS択信号によ)共通1III
IIIlで龜る入出力装置制御方式に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (1) Axis technology division The present invention provides common control (1III) for a plurality of input/output devices under the control of a main processing unit using an S selection signal for each separate outgroup.
This relates to an input/output device control method that is slowed down by III.
(鴫従来技留と閥一点
従来、主処理装置(CPU) OIFMI下に複数の入
出力*t(Ilo)があル場合、各I10 毎に−1ぞ
れ制御用レジスタを有し、CPUから各I10個別の選
択信号が送られて制御が行なわれる。しかし、九とえば
、複数I10の1場用の表示*置の477igJ盾爾の
設定等は同一命令であるにも拘らず、CPUで制御する
ためには各別の選択信号を与え個別制御14れるから煩
雑となる。この場合共通制御基れることが望ましい。(Conventional technique and one point) Conventionally, main processing unit (CPU) If there are multiple input/output *t (Ilo) under OIFMI, each I10 has a -1 control register, and from the CPU Control is performed by sending an individual selection signal to each I10.However, for example, the setting of the 477igJ shield in the display * position for multiple I10s is performed by the CPU even though the same command is used. In order to control, separate selection signals must be given to each individual control unit 14, which is complicated.In this case, it is desirable to use common control.
(3)発明の目的
本発@OWA的は主処場義to制御下にあみ債畝O入出
力装離に対し、各別の外共通の選択信号によn11m5
で1する入出力制御方式を蝿供すゐことである。(3) Purpose of the Invention The present invention @OWA is operated under the control of the main processing area for the input/output device of the input/output unit, and uses a common selection signal outside each separate n11m5.
The purpose is to provide an input/output control method that achieves 1.
(4)発@O構成
前記目的を連成するため、本発明の入出カー置制御方式
は主処理装置よp共通バスを通して複数の入出力装置に
個別選択信号を与えて各別に制御する入出力装置制御方
式において、複数の入出力装置を単一まえは複数のグル
ープに分は主処理輌1tI/c4!?グループ対応の選
択信号を発生する手IRを設け、鍍轟グループO入出力
装置を共通制御することを特徴とするものである。(4) I/O configuration In order to achieve the above-mentioned objectives, the input/output car placement control method of the present invention is such that the main processing unit applies individual selection signals to a plurality of input/output devices through a common bus to control each input/output device individually. In the device control method, if multiple input/output devices are divided into multiple groups, the main processing vehicle 1tI/c4! ? The present invention is characterized in that it is provided with a hand IR that generates a selection signal corresponding to a group, and that the input/output devices of the group O are commonly controlled.
(5)発@O実施例 図は本発明の実施例の構成説明図である。(5) Issu @O implementation example The figure is a configuration explanatory diagram of an embodiment of the present invention.
1111図において、CPU1O共通パス4に接続され
る41畝ffl九とえば2!1LOI10グループ2,
5を考える。各グループはそれぞれl102s〜2.お
よび11051〜3mよpanlそれぞれの170には
各別OI!IIIIll用レジスタを有し、CPU1よ
ルのアドレスを付し九命令が実線で示す個別制御lll
5t−介してIX轟110に送られ鯛別制mされる。以
上は従来0111111IB1方式でhゐが、本発明で
はグループアドレスとしてそのグループKJIIする各
l10C)アドレスのたとえば上位桁を共通アドレスと
して指定し下位をオール@0”として鍍グループを選択
して共、41IIl#を行なうことがで龜る。すなわち
、CPUIに設は喪共通アドレスレジスタ11を通して
fi定のグループアドレスを付した命令が破線で示す共
通−#* 12を介して威轟グループ、のIloに送ら
れ、グループ母O共通制御が行なわれる。実施例では両
−一を夷−と砿■で区別して示し九が、これは共通線と
してI10内の制御によル処虐することがで禽る。In Figure 1111, 41 ridgesffl9 connected to CPU 1O common path 4, for example 2!1 LOI 10 group 2,
Think about 5. Each group is l102s~2. And 170 of each panl from 11051 to 3m has a separate OI! It has a register for IIIll, and the nine instructions with the address of CPU1 are indicated by solid lines.
It is sent to IX Todoroki 110 via 5t and processed by Taibetsu. The above is based on the conventional 0111111IB1 method, but in the present invention, the upper digits of each l10C) address are specified as a common address, the lower digits are all @0'', and a group is selected. In other words, when the CPU is set up, an instruction with a fixed group address of fi is sent to Ilo of the prestige group via the common address register 11 indicated by a broken line. The group mother O common control is carried out. In the embodiment, both 1 and 2 are distinguished by 夿 and 翿■, and this can be treated as a common line by the control within I10. .
全I10を一括共通制一とする場合には共通制御である
ことを示す全共通符号貧村して送出するだけでよい。When all I10s are to be commonly controlled at once, it is sufficient to send all the common codes indicating that the control is common.
(6)発明の効果
以上説明したように1本発明によれば、 CPUよルグ
ループ@0共通信号を与えることにより、共!1111
鉤を行なうことが回目となる。このようにして、初期設
定等の同一命令の場合各別制御でなく−fimu−を行
なうことによ)、プログラムの間易化、高速化処理が夷
橋で鳶る。さらに、各々のIloに対して時間差なしで
セットアツプされ、見かけ上セットアツプ時間の短縮と
なる効果もめる。(6) Effects of the Invention As explained above, according to the present invention, by providing a common signal to the CPU group @0, it is possible to achieve a common signal between the CPUs and the group @0. 1111
This is the third time to perform the hook. In this way, in the case of the same command such as initialization, by performing -fimu- instead of controlling each command separately, the program can be simplified and processed faster. Furthermore, each Ilo is set up without any time difference, which apparently reduces the setup time.
図は本!ii@の実施例O1l成説明図でるる。図中、
1は主処場装置、2,3は入出力装置グループ、21〜
21115H〜5mは入出力懺置、4は共通パス、5紘
儂別1111麹−111は共通アドレスレジスタ、12
#i共通1sIl@麿を示す。The diagram is a book! An explanatory diagram of the example O1l of ii@ is shown. In the figure,
1 is the main processing equipment, 2 and 3 are input/output equipment groups, 21~
21115H to 5m are input/output registers, 4 is a common path, 5 is a common address register, 1111 is a common address register, 12
#i common 1sIl@maro is shown.
Claims (1)
に個別選択信号を与えて各別に制御する入出力装置制御
方式において、I[aの入出力l1I7&rItを単一
まえは複鎖Oグループに分は主処埴装置に谷グループ対
応の選択信号を発生する手段を設け、威幽グループの入
出力装置を共通WIJf/Rすることを特倣とする入出
力装置制御方式。In the input/output device control method in which individual selection signals are given to multiple input/output devices through a common bus to control each device separately, the input/output l1I7&rIt of I[a are divided into single and double-chain O groups. This is an input/output device control method in which the main processing unit is equipped with a means for generating a selection signal corresponding to the valley group, and the input/output devices of the Weiyu group are used as a common WIJf/R.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21460381A JPS58114222A (en) | 1981-12-28 | 1981-12-28 | Input/output device controlling system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21460381A JPS58114222A (en) | 1981-12-28 | 1981-12-28 | Input/output device controlling system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58114222A true JPS58114222A (en) | 1983-07-07 |
Family
ID=16658440
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21460381A Pending JPS58114222A (en) | 1981-12-28 | 1981-12-28 | Input/output device controlling system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58114222A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6435249A (en) * | 1987-07-30 | 1989-02-06 | Jeol Ltd | Control system for nmr apparatus |
-
1981
- 1981-12-28 JP JP21460381A patent/JPS58114222A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6435249A (en) * | 1987-07-30 | 1989-02-06 | Jeol Ltd | Control system for nmr apparatus |
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