JPH02128517A - Cmos inverter circuit - Google Patents
Cmos inverter circuitInfo
- Publication number
- JPH02128517A JPH02128517A JP63283000A JP28300088A JPH02128517A JP H02128517 A JPH02128517 A JP H02128517A JP 63283000 A JP63283000 A JP 63283000A JP 28300088 A JP28300088 A JP 28300088A JP H02128517 A JPH02128517 A JP H02128517A
- Authority
- JP
- Japan
- Prior art keywords
- cmos inverter
- rise
- inverter circuit
- drive capability
- fall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000630 rising effect Effects 0.000 claims description 7
- 230000005855 radiation Effects 0.000 abstract description 9
- 101100286980 Daucus carota INV2 gene Proteins 0.000 abstract description 2
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 abstract description 2
- 101150110971 CIN7 gene Proteins 0.000 abstract 1
- 101150110298 INV1 gene Proteins 0.000 abstract 1
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 101100113576 Arabidopsis thaliana CINV2 gene Proteins 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、入力信号の反転信号を出力信号として出力す
るCMOSインバータ回路に関するものであり、特に、
輻射ノイズを低減したCMOSインバータ回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a CMOS inverter circuit that outputs an inverted signal of an input signal as an output signal, and in particular,
This invention relates to a CMOS inverter circuit that reduces radiation noise.
〈従来の技術〉
現在LSIは超微細加工技術による高集積、高速化が進
み、これに伴い、輻射ノイズによる問題が起こり、この
問題につき無視できない状態にある。<Prior Art> Currently, LSIs are becoming more highly integrated and faster due to ultra-fine processing technology, and this has led to problems due to radiation noise, which cannot be ignored.
従来のCMOSインバータ回路に於いては、第2図に示
す様に、一種類のPチャネル、Nチャネ)vMO3)ラ
ンジスタTP、TNで構成されていた。同図−は回路図
、同図(b)はタイミングチャトである。In the conventional CMOS inverter circuit, as shown in FIG. 2, it is composed of one type of P-channel, N-channel)vMO3) transistors TP and TN. In the same figure, - is a circuit diagram, and in the same figure (b) is a timing chart.
〈発明が解決しようとする課題〉
上記の様に、従来のCMOSインバータ回路は一種類の
PチャネlV、Nチャネ/L/MOSトランジスタで構
成していたために、輻射ノイズ低減の為、トランジスタ
サイズを小さくして立ち上り・立ち下り時間を遅くすれ
ば、ドライブ能力が小さくなり、また、速くすれば、ド
ライブ能力は大きくなるが、輻射ノイズの問題が起こり
、問題解決はできない。すなわち、従来の方式では一種
類のPチャネル、NチャネルMO8+−ランジスタで構
成しているため、ドライブ能力を重視するか、又は輻射
ノイズ対策を重視するかにより、どちらかの問題点が残
る。<Problem to be solved by the invention> As mentioned above, since the conventional CMOS inverter circuit is composed of one type of P-channel LV, N-channel/L/MOS transistor, the transistor size has to be reduced in order to reduce radiated noise. If the rise and fall times are made smaller and the rise and fall times are delayed, the drive capacity will be reduced, and if the rise and fall times are made faster, the drive capacity will be increased, but the problem of radiation noise will occur and the problem cannot be solved. That is, since the conventional system is configured with one type of P-channel and N-channel MO8+- transistors, problems remain depending on whether emphasis is placed on drive capability or radiation noise countermeasures.
本発明は、上記問題点に鑑みてなされたものであり、こ
の問題点を解決したCMOSインバータ回路を提供する
ことを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a CMOS inverter circuit that solves these problems.
く課題を解決するだめの手段〉
本発明のCMOSインバータ回路は、入力信号の反転信
号を出力信号として出力するCMOSインバータ回路に
於いて、第1図に示すように、立ち上シ・立ち下シ用の
第1のCMOSインバータINV2 (TP2.TN2
: )うyジy、pサイス小)と、ドライブ能力用の
第2のCMOSインバタINVI (TPI、TNI
: )ランジy、pサイズ大)とを組み合わせて構成し
たことを特徴とするものである。A CMOS inverter circuit according to the present invention is a CMOS inverter circuit that outputs an inverted signal of an input signal as an output signal.As shown in FIG. The first CMOS inverter INV2 (TP2.TN2
) and a second CMOS inverter INVI (TPI, TNI) for drive capacity.
: ) lunge y, p size large).
〈作 用〉
本発明は、第1図の様に、2種類のトランジスタ(TP
I、TNIとTP2.TN2 )を使用するので、立ち
上り・立ち下り用と、ドライブ能力用とに分けることが
でき、これにより、ドライブ能力、輻射ノイズの対策を
行うことができる。<Operation> As shown in FIG. 1, the present invention uses two types of transistors (TP
I, TNI and TP2. Since TN2) is used, it can be divided into one for rising/falling and one for drive capacity, and thus measures can be taken against drive capacity and radiation noise.
〈実施例〉
第1図は本発明の一実施例を示すものであり、同図(a
)は回路図、同図(b)はタイミングチャートである。<Embodiment> FIG. 1 shows an embodiment of the present invention, and FIG.
) is a circuit diagram, and (b) is a timing chart.
第1因りの回路図に於いて、Pチャネ/L/MOSトラ
ンジスタTP2.Nチャネ)vMOSトランジスタTN
2が立ち上シ・立ち下り用で、トランジスタサイズを小
さめに、また、Pチャネ/I/MOSトランジスタTP
I、Nチャネ/L/MOSトランジスタTNIがドライ
ブ能力用で、トランジスタサイズを大きめにしておく。In the circuit diagram of the first cause, P channel/L/MOS transistor TP2. N channel) vMOS transistor TN
2 is for rising and falling, the transistor size is small, and P channel/I/MOS transistor TP
The I and N channel/L/MOS transistors TNI are for drive capability, and the transistor size is set to be large.
入力信号Aの変化が遅延回路DELAYIによって遅延
された信号A′により、TP2.TN2がオン・オフさ
れ、出力信号Yが立ち上り・立ち下りの変化を行い、そ
の後、さらに遅延回路DELAY2によって遅延された
信号Anによシ、TPI、TNIのどちかがオンされ、
ドライブ能力を大きくする。ORはオアゲート、AND
はアンドゲートである。また、入力信号Aの変化によっ
てTPI、TNIのどちらかがオフされる(第1図(b
)のタイミングチャート参照)。TP2. TN2 is turned on and off, the output signal Y changes between rising and falling, and then either TPI or TNI is turned on by the signal An delayed by the delay circuit DELAY2.
Increase drive ability. OR is or gate, AND
is an and gate. Also, depending on the change in input signal A, either TPI or TNI is turned off (Fig. 1(b)
)).
この動作により、出力信号Yの立ち上り・立ち下り期間
はTPI、TNI共にオフし、トランジスタサイズ小の
TP2.TN2によシ立ち上シ・立ち下りを制御し、輻
射ノイズを低減し、また、出力信号YがH,Lの期間中
は、トランジスタサイズ大のTPI又はTNIがオンし
、所定のドライブ能力を確保することができる。With this operation, both TPI and TNI are turned off during the rising and falling periods of the output signal Y, and TP2. TN2 controls the rising and falling edges to reduce radiation noise. Also, during the period when the output signal Y is H or L, TPI or TNI, which has a large transistor size, is turned on to maintain the specified drive capability. can be secured.
〈発明の効果〉
以上詳細に説明したように、本発明によれば、所定のド
ライブ能力を有すると共に、輻射ノイズも低減された極
めて有用なCMOSインバータ回路を提供することがで
きるものである。<Effects of the Invention> As described above in detail, according to the present invention, it is possible to provide an extremely useful CMOS inverter circuit that has a predetermined drive ability and also has reduced radiation noise.
第1図は本発明の一実施例を示すものであり、同図−)
は回路図、同図卸はタイミングチャートである。第2図
は従来回路を示すものであり、同図Ia)は回路図、同
図(b)はタイミングチャートである。
符号の説明
INVI: ドライブ能力用のCMOSインバタ、 I
NV2 :立ち上り・立ち下り用のCMOSインバータ
。
代理人 弁理士 杉 山 毅 至(他1名)(b)
第
(’Q)
!
図
Cb)
第
図FIG. 1 shows an embodiment of the present invention, and the same figure shows an embodiment of the present invention.
is a circuit diagram, and the same figure is a timing chart. FIG. 2 shows a conventional circuit, where Ia) is a circuit diagram and FIG. 2B is a timing chart. Code Description INVI: CMOS inverter for drive capacity, I
NV2: CMOS inverter for rising and falling. Agent Patent Attorney Takeshi Sugiyama (1 other person) (b) No. ('Q)! Figure Cb) Figure
Claims (1)
OSインバータ回路に於いて、 立ち上り・立ち下り用の第1のCMOSインバータと、
ドライブ能力用の第2のCMOSインバータとを組み合
わせて構成したことを特徴とするCMOSインバータ回
路。[Claims] 1. CM that outputs an inverted signal of an input signal as an output signal
In the OS inverter circuit, a first CMOS inverter for rising and falling;
A CMOS inverter circuit characterized in that it is configured in combination with a second CMOS inverter for drive capability.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63283000A JP2690760B2 (en) | 1988-11-08 | 1988-11-08 | CMOS inverter circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63283000A JP2690760B2 (en) | 1988-11-08 | 1988-11-08 | CMOS inverter circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02128517A true JPH02128517A (en) | 1990-05-16 |
JP2690760B2 JP2690760B2 (en) | 1997-12-17 |
Family
ID=17659919
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63283000A Expired - Fee Related JP2690760B2 (en) | 1988-11-08 | 1988-11-08 | CMOS inverter circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2690760B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0529328A2 (en) * | 1991-07-29 | 1993-03-03 | Fujitsu Limited | Pulse generator circuit for producing simultaneous complementary output pulses |
US5270580A (en) * | 1991-07-29 | 1993-12-14 | Fujitsu Limited | Pulse generator circuit for producing simultaneous complementary output pulses |
JP2011071979A (en) * | 2009-09-28 | 2011-04-07 | Samsung Electronics Co Ltd | Signal input circuit and semiconductor device containing the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63240208A (en) * | 1987-03-27 | 1988-10-05 | Nec Corp | Output buffer circuit |
-
1988
- 1988-11-08 JP JP63283000A patent/JP2690760B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63240208A (en) * | 1987-03-27 | 1988-10-05 | Nec Corp | Output buffer circuit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0529328A2 (en) * | 1991-07-29 | 1993-03-03 | Fujitsu Limited | Pulse generator circuit for producing simultaneous complementary output pulses |
US5270580A (en) * | 1991-07-29 | 1993-12-14 | Fujitsu Limited | Pulse generator circuit for producing simultaneous complementary output pulses |
JP2011071979A (en) * | 2009-09-28 | 2011-04-07 | Samsung Electronics Co Ltd | Signal input circuit and semiconductor device containing the same |
Also Published As
Publication number | Publication date |
---|---|
JP2690760B2 (en) | 1997-12-17 |
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