JPH02127040U - - Google Patents

Info

Publication number
JPH02127040U
JPH02127040U JP3719589U JP3719589U JPH02127040U JP H02127040 U JPH02127040 U JP H02127040U JP 3719589 U JP3719589 U JP 3719589U JP 3719589 U JP3719589 U JP 3719589U JP H02127040 U JPH02127040 U JP H02127040U
Authority
JP
Japan
Prior art keywords
wiring
bumps
metal substrate
chip
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3719589U
Other languages
English (en)
Other versions
JPH0648873Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3719589U priority Critical patent/JPH0648873Y2/ja
Publication of JPH02127040U publication Critical patent/JPH02127040U/ja
Application granted granted Critical
Publication of JPH0648873Y2 publication Critical patent/JPH0648873Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Description

【図面の簡単な説明】
第１図は本考案の一実施例、第２図は従来の一
例の構造図である。 図において、１はチツプ、２，２１，２５は配
線、３，３２，３５，３６はパツド、４，４１は
バンプ、５，５５は絶縁層、６，６５は放熱部材
、７は金属基板、８，８５は絶縁基板、９はワイ
ヤボンデイング、３１，３７はリード端子、６１
はフイン、６２は基板、８１はシール部材、８６
は端子板、８７は保護コートである。

Claims (1)

  1. 【実用新案登録請求の範囲】 片面に複数個の半導体装置或いは固体装置のチ
    ツプ１をダイボンデイングさせ、余白部に相互接
    続配線２とパツド３を具え、該配線２上の外部接
    続位置にバンプ４を形成させた絶縁層５を設け、
    該チツプ１のパツドと該絶縁層５のパツド３とを
    ワイヤボンデイング９させ、他面に放熱部材６を
    固着或いは一体に成形させた金属基板７と、 片面に配線２１と、該配線２１上の所定位置に
    バンプ４１を形成させ、他面の所定位置に該配線
    ２１に接続した外部接続用のリード端子３１を突
    設させた絶縁基板８とから構成され、 該金属基板７と該絶縁基板８とを対向させ、該
    バンプ４，４１同士を一体に接合し、所定間隔に
    保持してなることを特徴とするマルチチツプ実装
    構造。
JP3719589U 1989-03-30 1989-03-30 マルチチップ実装構造 Expired - Lifetime JPH0648873Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3719589U JPH0648873Y2 (ja) 1989-03-30 1989-03-30 マルチチップ実装構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3719589U JPH0648873Y2 (ja) 1989-03-30 1989-03-30 マルチチップ実装構造

Publications (2)

Publication Number Publication Date
JPH02127040U true JPH02127040U (ja) 1990-10-19
JPH0648873Y2 JPH0648873Y2 (ja) 1994-12-12

Family

ID=31544087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3719589U Expired - Lifetime JPH0648873Y2 (ja) 1989-03-30 1989-03-30 マルチチップ実装構造

Country Status (1)

Country Link
JP (1) JPH0648873Y2 (ja)

Also Published As

Publication number Publication date
JPH0648873Y2 (ja) 1994-12-12

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