JPH02125462A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the current amplification factor of a bipolar transistor and to suppress the irregularity by insularly sequentially diffusing a first conductivity type collector layer, a second conductivity type base layer and a first conductivity type emitter layer in an isolated region. CONSTITUTION:High concentration N<+> type buried layers 2a, 2b, 2c are formed on a P-type semiconductor substrate 1. Then, a N<-> type epitaxial layer is grown, and a P-type isolating layer 4 is formed by a selective diffusing technique to form isolating regions 3a, 3b, 3c. Thereafter, a P<-> type collector layer 25 and a P<-> type well layer 13 are simultaneously formed. Then, after the part of the layer 25 of an insulating oxide film 7 is opened with a window, impurity ions are implanted, heat-treated to insularly form an N-type base layer 26 in a P<-> type collector layer 5. Subsequently, a polysilicon layer is deposited on the surface, and a polysilicon gate layer 27 remains only on a part to be a gate by photolithography. The source and drain of a P-channel FET (Fp) are formed of the layer 27 by a self-aligning method.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a bipolar transistor and a MOS FET on the same chip, and a method for manufacturing the same.

[Conventional technology]

Semiconductor integrated circuit devices are classified into bipolar and M type depending on their structure.
It is classified into OS type. There are two types of active devices in the bipolar type: NPN) transistors and PNP) transistors. On the other hand, there are two types of MOS type active elements: an N-channel field effect transistor (N-channel FET) and a P-channel field-effect transistor (P-channel FET). Furthermore, in recent years, a Bi-CMOS type O3 circuit device in which a bipolar type element and a complementary pair of MOS type elements coexist on an l chip has been realized.

FIG. 3 is a vertical cross-sectional view showing an example of a conventional Bi-CMOS type O3 circuit device.
A P-channel FET (Fl) and an N-channel FET (Fn) constituting a MOS type element are built into the same chip. The method for manufacturing this Bi-CMOS type O3 circuit device is to first form an insulating oxide film on a P-type semiconductor substrate 1, photolithography, and diffusion, and then selectively fill N-type high-concentration impurity buried diffusion layers 2a, 2b, After forming 2a, an N-type epitaxial layer is grown thereon.

Next, the P type isolation layer 4 is deeply diffused so as to connect to the substrate 1 to define an isolation region, and the N
PN) transistor Tn (P type base layer 5, N'' type emitter layer 6, N+ type collector contact layer 7) is placed in another isolation region 3b.
(p-type emitter layer 8.P-type collector Fi9.N+JB base contact layer 10) and a P-channel FET (P-type source layer 11.P-type drain layer 12> and N channel FE
T (P-type well layer 13. N-type source layer 14.
An N'' type drain layer 15) is formed.

[Problem to be solved by the invention]

However, in the above conventional Bi-CMOS type O3 circuit device, the PNP transistor Tp is a so-called lateral PNP transistor in which the emitter layer 8 and the collector layer 9 are arranged side by side.
Since it has a transistor structure, its current amplification factor (hp
t) has a low value of lO~50.

However, the current amplification factor can be improved by narrowing the base width between the emitter gamma junction and the collector junction, but due to the horizontal PNP structure, the accuracy of the base width depends on the microfabrication technology using photolithography. The narrower the width, the greater the variation in current amplification factor. With current photolithography technology, the base width is 0,
5 μm is the control limit.

The present invention solves the above-mentioned problems, and its purpose is to provide a Bi-CMOS in which the current amplification factor of the bipolar transistor is larger than that of the conventional one and its variation is suppressed.
An object of the present invention is to provide a type semiconductor integrated circuit device and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention provides a second semiconductor integrated circuit device grown on a semiconductor substrate of a first conductivity type.
A first conductive layer is formed in an island shape and sequentially diffused in an isolation region which is junction-separated by a first conductivity type isolation layer in an epitaxial layer of a conductivity type, and has a buried layer of a second conductivity type at the bottom. The semiconductor integrated circuit device includes a vertical bipolar transistor having a collector layer of a conductivity type, a base layer of a second conductivity type, and an emitter layer of a first conductivity type. After providing a buried layer of a second conductivity type in a semiconductor substrate and growing an epitaxial layer of a second conductivity type thereon, an isolation layer of a first conductivity type is formed to define an isolation region. and a collector layer of a first conductivity type and a channel MOSFET of a second conductivity type in the corresponding isolation region.
A first conductivity type well layer of T is simultaneously diffused, then a second conductivity type base layer is diffused, and then a first conductivity type emitter layer and a first conductivity type channel are formed. MOS type F
The source layer and drain layer of ET are simultaneously formed by diffusion.

[Effect]

According to the semiconductor integrated circuit device having such a configuration, since it includes a vertical bipolar transistor made by thermal diffusion technology instead of a horizontal bipolar transistor, the base width between the emitter junction and the collector junction can be set narrowly with high precision, and the bipolar transistor The current amplification factor can be significantly improved compared to the conventional method, and its variation can also be reduced.

Furthermore, according to the manufacturing method of the present invention, the diffusion formation of the base layer of the second conductivity type is performed independently of the diffusion formation of the MOS type element, so that flexibility can be provided in the selection of base conditions. This makes it easy to obtain the desired current amplification factor. Although there is an independent formation step of the base layer, the formation of the collector layer of the first conductivity type and the well layer of the first conductivity type are performed simultaneously, and the emitter layer of the first conductivity type and the first conductivity type well layer are formed simultaneously. Since the formation of the source layer and drain layer is performed simultaneously, the number of manufacturing steps is not increased compared to the conventional method, and a high-performance semiconductor integrated circuit device can be provided at low cost.

〔Example〕

Next, embodiments of the present invention will be described based on the accompanying drawings.

FIG. 1 is a longitudinal cross-sectional view of the main manufacturing steps of the first embodiment of the present invention, and FIG. 1(e) shows the manufactured semiconductor integrated circuit device. In this example, PNP
) Since the vertical structure of the transistor reduces the base width, forms the base layer independently, and minimizes the number of steps, the structure will be explained by following each step in turn. Note that the same parts in FIG. 1 as those shown in FIG. 3 are given the same reference numerals.

First, as shown in FIG. 1(a), a P-type semiconductor substrate ((1
A C2P silicon substrate having a 00) surface, an impurity source of boron, and a resistivity of 10 to 20 Ωcm) are prepared, and an insulating oxide film is formed thereon, photolithography, and thermal diffusion are performed to form a highly concentrated N+ type buried layer 2a, 2b.

2c (enlargement 11, depth 3-5 μm, surface impurity concentration 5-1
0XIO"am-3, root resistance 20 to 50 Ω/2, impurity source antimony). Left side buried layer 2al'
! NPN) for transistor Tn, the central buried layer 2b is PN
P) For transistor Tp, the relatively wide buried layer 2C on the right side is for P channel FET (Fp) and N channel FET
(Fn). Next, an N-type epitaxial layer (growth thickness 3-10 μm, resistivity 2-5 Ωcm,
After that, a P-type separation layer 4 (diffusion depth 4-12 μm 1 surface impurity concentration 5-10 × 1
0 "am-', impurity source boron) is formed by selective diffusion technology (formation of insulating oxide film 7, photolithography, ion implantation, thermal diffusion) to form isolation regions 3a, 3b, 3c.
form. Thereafter, a P-type collector layer 25 and a P-type well layer 13 are simultaneously formed. Specifically, boron is introduced by ion implantation from 1 to 10XIO"am-2,
Diffusion depth 2-8μm 1 surface impurity concentration 1-8μm by heat treatment
Formed as 10XIO"cl'.

Next, as shown in FIG. 1(b), a window is opened in a part of the P-type collector layer 25 of the insulating oxide film 7 by photolithography, and then impurity ions are introduced by ion implantation or the like and heat treatment is performed. , an N-type base layer 26 is formed in the shape of an island within the P-collector layer 5. Specifically, phosphorus is introduced to a depth of 1 to 1'OX 1011 cm by ion implantation, and the diffusion depth is 1 to 5 μm by heat treatment.

The surface impurity concentration is set to 1 to 10XIO"Cm-". Since this island-like diffusion formation of the N-type base layer 26 into the P-type collector layer 25 is performed independently from the formation of the N-channel FET (Fn), the PNP configured as a vertical structure is ) The element characteristics of the transistor Tp can be optimized.

Next, as shown in FIG. 1(C), a polysilicon layer is deposited on the surface by the CVD method, and a polysilicon gate layer 2 is deposited only on the portion that will become the gate by photophosphorography.
Leave 7. Next, NPN) the part that should become the base of the transistor Tn, PNP) the part that should become the emitter and collector of the transistor Tp, and the P-channel FET (Fp)
Open a window in the part that should become the source and drain of the
other parts are covered with a photoresist mask layer 28;
A P-type ion implantation layer 30 is formed by implanting P-type ions 29 .

Here, the polysilicon gate layer 27 allows a P-channel F
The formation of the source and drain of ET (Fp) is realized by a self-line technique.

Next, as shown in FIG. 1(d), a P-type ion implantation layer 30
After formation of the P-type base layer 5. of the NPN) transistor Tn by heat treatment. PNP) P-type emitter layer 31, P-type collector contact layer 32 and P-channel F of transistor Tp
A source layer 11 and a drain layer 12 of ET (Fp) are simultaneously formed by diffusion. Specifically, the diffusion depth is 0.4 to 4.
μm1 surface impurity concentration is 1 to 1 OXIO"cm-3. In the isolation region 3b, a P-type collector layer 25, an N-type base layer 26, and a P-type emitter layer 31 are sequentially diffused into an island shape, and these are vertically formed. It constitutes a type NPN transistor.The base width in the vertical structure is 0.1 to 1.0 μm, and this width can be controlled with high precision by diffusion heat treatment.The current amplification factor (Li) is determined by the base width and the emitter layer 31. Although it depends on the concentration of the base layer 26, since these can be controlled relatively easily, a current amplification factor of 100 to 300 can be obtained.Also, the concentration and depth of the collector layer 25 can be adjusted at the same time as the N-channel FET. The concentration and depth of the emitter layer 31 are related to the concentration and depth of the P-type well layer 13 (Fn), and the concentration and depth of the emitter layer 31 are related to the source layer 11 and drain layer 1 of the P-channel FET (Fp).
2, and these are related to the concentration and depth of P-channel FET (
Since it is a factor that determines the device characteristics of Fp) and N-channel FET (Fn), it is difficult to change it freely. By optimizing the conditions for forming the base, it is possible to optimize the device characteristics of the vertical transistor.

Next, the emitter and collector of the NPN transistor Tn and the source of the N-channel FET (Fn).

In order to implant impurities into the drain, the other portions are covered with a photoresist mask layer 28, and N-type ions 33 are implanted to form an ion implantation layer 34 with a thickness of about l=lOX 10''am-'.

Next, as shown in FIG. 1(e), the introduced impurity is thermally diffused into the emitter layer 35 of the NPN transistor Tn. Collector contact layer 36 and N-channel FET (Fn
) source layer 37. A drain layer 38 is formed. Each layer has a diffusion depth of about 0.2 to 2 μm and a surface impurity concentration of l.
= lOX about 10" cm-3. Next, the window for electrode formation is made using IJ Sogelafy, and NPN transistor T is formed by aluminum evaporation.
n emitter E, base B, collector C electrodes, PN
The emitter E, base B, and collector C electrodes of the P transistor Tn, the source S of the P channel FET (Fp),
Gate G, drain D electrodes and N-channel FET (
After forming the source S, gate G, and drain D electrodes of Fn), the electrode wiring is completed by photolithography.

According to the above manufacturing method, it is possible to obtain a semiconductor integrated circuit device with a high current amplification factor as originally intended, but since the N-type base layer 26 is formed alone, the number of man-hours increases accordingly. , P-type collector layer 25 of PNP transistor Tp and P-type well layer 13 of N-channel FET Tn.
Since the P-type emitter layer 31 of the PNP transistor Tp and the source layer 11 and drain layer 12 of the P-channel FET (Fp) are simultaneously formed, there is no need to increase the overall man-hours. This makes it possible to realize high-performance, low-cost semiconductor integrated circuit devices.

FIG. 2 is a longitudinal sectional view showing a second embodiment of the semiconductor integrated circuit device according to the present invention.

This shows the state in which the electrode wiring has been completed, but the difference from the first embodiment is that an N-type collector all layer 40 of the NPN transistor Tn is formed. The formation of this collector all layer 40 is performed using a PN layer shown in FIG. 1(b).
P) This is performed simultaneously with the formation of the N-type base layer 26 of the transistor Tp. That is, the formation process of the N-type base layer 26 is performed separately from the CMOS element formation due to the element characteristics, but in order to reduce the collector resistance of the NPN transistor Tn, the collector all layer 40 is also formed. They are formed simultaneously.

〔Effect of the invention〕

As explained above, in the semiconductor integrated circuit device according to the present invention, in a semiconductor integrated circuit having a bipolar transistor and a MOS FET on the same chip, a collector layer of a first conductivity type and a collector layer of a second conductivity type are sequentially provided in an isolation region. Since it has a vertical bipolar transistor formed by diffusing a base layer of a conductivity type and an emitter layer of a first conductivity type into an island shape, the base width can be set narrower with higher precision than in the past. The current amplification factor can be made considerably large.

Further, the manufacturing method for realizing the above semiconductor integrated circuit device is as follows:
Optimization of the vertical bipolar transistor is realized by forming the base layer of the second conductivity type independently from the formation of each layer of the MOS FET and optimizing the base conditions relatively freely. Furthermore, since each layer of the vipolar transistor and each layer of the MOS FET are formed at the same time, despite the existence of an independent formation process for the base layer, the increase in man-hours can be suppressed and high performance can be achieved at low cost. A semiconductor integrated circuit device can be provided.

Furthermore, if the collector all layer of the second conductivity type is formed simultaneously with the formation of the base layer of the second conductivity type, a semiconductor integrated circuit device with reduced collector resistance can be obtained without increasing the number of manufacturing steps.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are vertical cross-sectional views showing the main manufacturing process in the first embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. 1 is a longitudinal sectional view showing a first embodiment of a semiconductor integrated circuit device according to the present invention; FIG. FIG. 2 is a longitudinal sectional view showing a second embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 3 is a vertical cross-sectional view showing an example of a conventional semiconductor integrated circuit device. I P type semiconductor substrate, 2a, 2b, 2cm N'' type buried layer, 3a, 3b, 3c isolation region, 4 isolation layer, 5 P
type base layer, 7 insulating oxide film, 11P type source layer, 12
P-type drain layer, 13- P-type well layer, 25P
- type collector layer, 26 - N type base layer, 27 polysilicon gate layer, 28 photoresist mask layer, 2
9 P-type ion, 30 P-type ion implantation layer, 31 P-type emitter layer, 32-P-type collector contact Ii! ,
33. ,,, N-type ion, 34 N-type ion implantation layer,
35N+ shaped mitsuta layer, 36- N+ type collector contact layer, 37N''' source layer, 38N+ drain layer, T
n -NPN) transistor, Tp, , -PNP
) transistor, Fp P channel FET, F n
--N channel FET02a, 2b, 2c buried layer 30.3b, 3C isolation region] Figure button Fp n Figure

Claims (1)

[Claims] 1) An epitaxial layer of a second conductivity type grown on a semiconductor substrate of a first conductivity type, which is junction-separated by a separation layer of the first conductivity type, and has a second conductivity layer at the bottom. A semiconductor integrated circuit device in which a bipolar transistor and a MOS FET are built in an isolation region having a shaped buried layer, wherein a collector of a first conductivity type is sequentially diffused in an island shape within the isolation region. A semiconductor integrated circuit device comprising a vertical bipolar transistor having a base layer of a second conductivity type and an emitter layer of a first conductivity type. 2) Providing a buried layer of a second conductivity type on a semiconductor substrate of a first conductivity type, growing an epitaxial layer of a second conductivity type thereon, and then forming a separation layer of a first conductivity type. A method for manufacturing a semiconductor integrated circuit device, in which a collector layer of a first conductivity type and a collector layer of a second conductivity type are formed to define an isolation region, and then a bipolar transistor and a MOS FET are respectively formed in the isolation region. a step of simultaneously diffusing and forming a first conductivity type well layer of a type channel MOS type FET;
a step of diffusion forming a base layer of conductivity type;
1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of simultaneously diffusing an emitter layer of a conductivity type and a source layer and a drain layer of a channel MOS FET of a first conductivity type. 3) The semiconductor integrated device according to claim 2, wherein in the second conductivity type base layer diffusion forming step, a second conductivity type collector wall layer is simultaneously formed in another separation layer. A method of manufacturing a circuit device.