JPS62247558A - Monolithic integrated semiconductor device containing bipolar junction transistor,cmos and dmos transistor and diode with little leakage - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates generally to monolithic integrated circuits consisting of different types of components, and in particular to MO3/bipolar type components and MOS type components. It relates to components, more precisely integrated circuits including OMO3 and complementary DMOS components, and methods of manufacturing the same.

PRIOR ART AND ITS PROBLEMS The multiple and unique requirements of analog circuits for signal handling, or complex systems consisting of e.g. measurements, signal handling, calculations, logic and other similar functions, clearly Semiconductor devices having very different structures and typically manufactured in different ways can be filled separately in an effective manner. For example, in analog circuits, active components manufactured by bipolar technology are often Preferable to CMOS parts. Conversely, the 0MO3 transistor, although not comparable to certain characteristics of the bipolar transistor (L),
It allows for greater density, higher noise thresholds and lower waste, making it particularly suitable for logic and memory circuits. Furthermore, the vertical DMOS transistor is
It is particularly suitable where relatively high voltage operation is required and high switching speeds are required.

On the other hand, the method of integrating all components of a particular circuit on a single chip of monocrystalline semiconductor material limits the adoption of components with compatible structures, thereby making it difficult to integrate them on the same substrate of semiconductor material. enable.

This means that all the components of the circuit to be integrated must be able to be manufactured on the same substrate in a series of working steps, said steps being essential from a compatibility point of view, using photolithography techniques. is equivalent to the use of a number of masks performed in a certain order to define zones on the surface of a wafer of semiconductor material, through which the necessary implantation and diffusion of acceptor or donor dopants can take place. the desired spatial arrangement in the semiconductor;
A number of zones or regions are created that have size and electrical properties, as well as compartments for the formation of electrodes, contacts, and active elements such as capacitors, resistors, etc.

Therefore, insofar as designing a particular circuit section requires the selection of special manufacturing techniques for the integrated circuit to overcome such requirements, the most suitable for the various sections of the circuit. There are limitations in manufacturing economically viable parts of the same type.

Recently, methods of manufacturing integrated circuits have been devised that make it possible to form several bipolar-type components together with several CMOS-type components on the same chip.
And some more recent MOS type components have also been devised which are more suitable for high operating voltages.

“Electron Design” March 31, 1982
icDesign) "Mixed Processes Deliver High Power Under Fine Control" by Tortus E. Ruggles and Gary W. Fye, J.
ss PutsHigh Power Under F
ine Control) J, February 9, 19-84, “News of Electro
The rDMOSCMOS process by Stephen Oh found in nic Design)J is oriented towards the highest power rate for smart power control (D
MOS CMOS Process Ports T
o Highest Power Rating For
'Smart'Power Control) J,
“IEEE Interaction of Electronic Devices 01EEE Tra
ns-action on Electron Dev
``An Analog Technology Integrating Bipolar-1CMO8 and High-Voltage DMOS Transistors'' by Surinder Krishna, James Kuo and Isaura Selvin Gaeta, J (No. 1, Volume 31, January 1984).
Integrates Bipolar.

CMOS and High Voltage 0MO
3Transistors) J, and publications such as '
European Patent Application No. 8 entitled ``Semiconductor Devices''
No. 2902544.4 (Public Notice No. 0117867A1)
, “Transistor Bipol operated by the field effect of an insulating grid.
Aire a Commandepar Effect
de Champ au Moyen d'une G
European Patent No. 0068945B1 entitled "High Voltage Mos/Bipolar Power Transistor Device" and European Patent Application No. 84400220.4 entitled "Logic
U.S. Pat. No. 4,546 entitled "Monolithic Integration of Control and High Voltage Interface Circuits."
No. 370 is an example of a number of manufacturing methods that allow the formation of specific components of different structure in the same integrated circuit by manufacturing operations known per se.

The inventors have recognized that there are important limitations in known proposals. For example, many of the devices mentioned above are metal games) CM
Considered as a basis for the fabrication sequence typical of OS processes, this results in a single part with properties significantly inferior to those obtained by more refined silicon gate processes. On the other hand, many such devices with a single level of metal cannot form capacitors with high reproducibility of capacitance values.

Furthermore, the severe limitations of such known devices are that none of these offer integrated circuit designers a truly complete scope for monolithic integration onto high-quality analog or analog/digital signal handling circuit sections on a single chip. This is due to the fact that it is not possible to make use of existing parts.

OBJECTS OF THE INVENTION It is an object of the invention to provide a semiconductor device which is capable of containing a more complete range of active and passive components of different types in integrated form on the same substrate than is provided in known devices. It is an object of the present invention to provide a method for manufacturing such a device that requires fewer masking steps.

(Structure of the Invention) The device that is the object of the present invention is integrated on a single chip, and includes a lateral CMOS transistor, a complementary vertical DMOS transistor, and a complementary vertical DMOS transistor.
It may include one or more of each of the following circuit components: a transistor, a vertical NPN transistor, a vertical PNP transistor with isolated collector, and a low leakage junction diode.

The gate electrode of the MO3 component is made of polycrystalline silicon (poly) and preferably the device has high fidelity components such as a capacitor (utilizing two levels of poly as armature) and a resistor in the same device. Polycrystalline silicon substrates allow easy integration of sensitive passive components and also provide field plates to reduce the strength of locally enhanced electric fields corresponding to the edges of the DMOS structure. 2 levels are given.

The device of the invention has the advantage that a collection of circuit components of different types can be formed on a single integrated structure,
The components are characterized by special capabilities that allow them to individually meet the different requirements of specific circuit sections of complex systems.

Vertical DMOS, both p-channel and n-channel, with a particularly high breakdown voltage, as well as lateral CMOS transistors characterized by high switching speeds and therefore suitable for use in control, decision (intelligence) and signal handling circuits. Transistors can be used insofar as the latter is substantially determined by the large resistance of the drain region and by the degree of curvature of the p-n junction, compared to what occurs in lateral MOS transistors. Furthermore, vertical DMOS transistors have remarkable switching speeds and thermal stability, and these characteristics make them capable of exceeding 10% even on strong capacitive loads.
It is particularly suitable for an output stage where the voltage can be controlled on the order of 0 volts.

Furthermore, the devices of the present invention both have a range of 0.5 to 1°5 GH.
A vertical NPN bipolar transistor with a separated collector presents a cut-off frequency of the order of z and has a high current gain, which is very useful for obtaining wide band amplifiers, for example. May contain.

Another circuit component that can be included in the device and is extremely useful in very frequently occurring circuit conditions (i.e. driving inductive loads) is a low leakage junction diode.

As a matter of fact, in integrated circuits, the diodes utilized by the circuit themselves often have large leakage towards the substrate, due to the switching on of the associated parasitic transistor under forward bias conditions of the diode, which causes leakage of current towards the substrate. It is the main source of current. Conversely, low leakage diodes are characterized by structures that provide a "screen" effect that minimizes such leakage currents.

The presence of a double layer of "poly" (or polycrystalline silicon) is very constant when the poly double layer level is utilized as the armature of a capacitor.
Mil 2 (A mil is 2-tenths of an inch) 5.4
It is possible to obtain a highly reproducible capacitor giving a specific capacitance per section light equal to x 10-'' mm).

The possibilities for providing resistors can also be expanded by the use of two separate layers of poly, each individually manufactured to have different resistances.

The device according to the invention was first found in monolithic integration in providing complex systems for signal handling, and - low leakage junction diodes (L L D) - lateral P
- MOS transistor 1 horizontal type N-MOS transistor (these two are 0MOS transistors) - vertical type N
- DMOS transistors - Vertical P-DMOS transistors - Vertical NPN bipolar transistors and vertical PNP bipolar transistors with separate collectors to best meet the requirements of virtually any circuit represented by We provide a series of parts.

The use of a device made in accordance with the present invention consisting of the seven separate components described above provides significant advantages to the integrated circuit designer.

Since there are suitable components for any circuit condition, in principle any design can be made without compromise. There is a correct part for each requirement. Of course, it is not necessary to use all of these parts all the time, but
Decide which and how many of the above seven parts to use on a case-by-case basis. In order to better illustrate the features and advantages of the invention, some application examples of devices made according to the invention are presented below.

Example: In a telephone, for example, the lowest possible supply voltage (approximately 2-3 volts) is used to amplify low-level audio signals, and the circuit and capsule that serves as the loudspeaker for the telephone receiver are There is a need for a circuit capable of filtering an output stage with a large dynamic characteristic of the voltage of the output signal to provide the drive current. Suitable components for satisfying such technical requirements are bipolar transistors in the input stage due to their low noise and residual deviation characteristics, CMOS transistors for the filter section using switched capacitor technology,
and again bipolar transistors (vertical PNP with separate collector and vertical NPN) in the output stage to obtain high power and high output current.

In the current state of the art, these functions are performed using two "chips", one bipolar and the other CMOS. A CMOS transistor manufactured according to the present invention,
According to a device comprising bipolar vertical transistors NPN and PNP with separate collectors:
It is possible to form the entire circuit on a single "chip".

In the area of control and trimming systems there are many possibilities for the application of "intelligent" circuits for driving inductive loads. For these applications, bipolar transistors are used for the input stage, CMOS transistors for the signal handling section and for "talking" with the microprocessor, and finally in the output stage for driving loads at high levels of current. A bipolar transistor, preferably of vertical type, is required.

Furthermore, it is necessary to use a circulating diode to avoid the output moving above and below the supply voltage due to the VIIE (of the clamp diode).

In these circuit conditions, low leakage diodes (LLDs) should be used to reduce power dissipation that would be excessive in normal types of diodes due to the balastic PNP transistors being excited and losing current towards the substrate. is required.

Again, vertical NPN and vertical PNP, CMOS, fabricated according to the invention and with separate collectors
Devices containing bipolar junction transistors consisting of transistors and LLD diodes allow the integration of entire circuits on a single chip.

The circuit sections for driving displays vary widely in the nature of the loads being driven, while higher levels of output voltage are required. For these applications, the device manufactured according to the invention can contain lateral CMOS transistors for the section that handles the signals in an exclusively digital manner, while the output stage has about 40 to 50
Complementary vertical DMOS that enables operation with output voltages of volts
Advantageously manufactured with transistors.

1 to 12 are schematic longitudinal cross-sectional views showing the general structure of the device of the invention by sequentially illustrating how the different components are integrated on the same substrate.

The series of drawings from Figures 1 to 12, necessarily in a diagrammatic manner, show that the seven different components mentioned above are shown in a single piece through a series of longitudinal cross-sectional views of the wafer being processed. The abbreviated nomenclature of said seven components is intended to represent successive manufacturing operations or steps in the manufacturing method that is the subject of the present invention by illustrating one after another how they are formed on a monolithic substrate. are shown at the bottom corresponding to each area of the combined drawing group. The illustration is simplified and does not include anything particularly well-known, such as selective ion implantation operations, special techniques for opening contacts, etc. Furthermore, the diffusion of doping elements may actually be hindered in some cases due to the ion implantation from the gas phase or other operations of deposition, and the torturous heat in which the devices being fabricated are processed. Although it may not be complete until the end of the cycle, it was considered complete within the relevant cross section. In order to avoid overcrowding of the symbols in the drawings, especially those relating to the final stages of manufacture, the types of electrical conductivity of the various regions are repeated in all areas or regions of a single crystal of semiconductor material. Not there. If this is not clearly indicated, the type of conductivity can be determined by looking at the preceding drawings, since the series of drawings represents the various modifications that the wafer undergoes during the manufacturing process as a series of "same" cross-sections. can be easily guessed.

According to a presently preferred embodiment of the device of the invention, the starting material is a <100> slice or wafer of p-silicon, a single crystal of silicon obtained by the Czochralski method, with a resistance between 1 and 5 Ω·craO. .

After the oxidation of the surface of the wafer has proceeded, a photosensitive material (commonly referred to as "photoresist" or more simply "resist") is deposited on the surface and a pre-prepared mask (typically This layer is irradiated through a suitable one (often made of a glass plate coated with an opaque material, i.e. chromium) to define the shape or contour of the compartment, or if a negative resist is used. A first masking operation according to known techniques consists of removing the unirradiated photosensitive material or, conversely, exposing a zone to be defined on the surface of the wafer if a positive resist is used. It will be done.

The layer of resist left on the sections is removed by subsequent technical operations, namely the implantation of antimony ions into the silicon single crystal corresponding to the unmasked sections and the subsequent so-called buried layer. Approximately 6 at approximately 1200 °C for formation
Construct a mask, which is the masking material for the diffusion heat treatment (performed after removing the remaining resist layer), which is performed for 0 minutes. Such an operation is illustrated in FIG. 1, where a starting material slice of p-silicon is indicated at 1 and a preformed oxide (SiO
□), antimony atoms being implanted into a photoresist mask (resist) and the atoms after diffusion into the single crystal are shown.

A new layer of photoresist is then deposited and a second mask is then prepared following the same technique as described above. Then the oxide (SiO
□) Plasma attack the masked wafer until the layer is completely removed, thereby exposing the single crystal.

As shown in FIG. 2, boron ions are implanted through the p-buried layer and associated sections to form the bottom isolation.

The photoresist and oxide residues are then completely removed by plasma attack, preferably to a resistance of 1 to 3 Ω.
A layer of n-silicon (indicated by 2 in the drawing) having a thickness of between 9 and 11 micrometers between cIll and 100 nm is epitaxially grown on the surface of the starting single crystal of p-silicon. Next, about 1,500 people worked on silicon oxide (
92 in the presence of water vapor until a layer is formed.
The surface is then treated and oxidized at a temperature of 0°C using the same technique as described above, through which the vertical PNPs of the body fiI region of N-MOS, the drain region of P-DMOS and the separate collector are oxidized. ) Ripple Diffusion Transif! , the so-called p-tub (p-well) that constitutes the collector region of the tar (ICV PNP 3D)
A third masking operation is performed to define the areas in which regions of p-silicon are to be formed. As shown in FIG. 3, the total impurity per unit area in the crystal Q = 10"cm-
After removing the resist that formed the mask during the boron implantation for the p-tub, a brief heat treatment is performed on the partial diffusion. , about 3000 nm thick silicon nitride (usually from the vapor phase) is deposited on the surface of the wafer being processed.
SiJt) eyebrows are attached. A fourth masking operation delimits the regions intended for the formation of continuous diffusions with the resist and performs a plasma attack until the nitride is completely removed from the regions not protected by the resist mask.

After these operations, the cross-section itself becomes as shown in FIG.

A fifth masking operation, shown in FIG. 5, followed by a simple attack to remove the S40g layer creates a deep n" for electrical connection with the respective n" buried layer.
"Pre-fabricate a wafer for the phosphorus implantation necessary to realize the sinker J diffusion. The implantation results in a total impurity of approximately Q-1016 cm-" per unit area in the crystal in the diffusion region. This is done at 80 KeV. Simultaneously with these operations, and in addition to the preformation of the sinker diffusion, the structure of the deep n" diffusion region and the low leakage diode (L L D) of the electrical connection, which was later made into a continuous wall shape, A portion that will serve as a shield for the anode region of is formed in advance.

A sixth masking operation, as shown in FIG. 6, prepares the wafer for the boron implant needed to create the deep p' diffusion in contact with the p buried layer and for top isolation. The boron implant has a unique charge convention Q in the region.
= 10 lScm-”ly<40K as obtained
carried out at eV.

At the same time, the wafer is further implanted with boron corresponding to the region that will become the anode region of the p4 silicon of the low leakage diode (LLD) in the form of a wall region located inside the n-wall region of the contact and shield. , to make it, the associated phosphorus injection was done in the previous operation.

After removing the masking resist, the original oxide (Si
n2) thickening of the field oxide in the sections not coated with nitride (SiJ4) by treatment at about 1000 °C in the presence of water vapor until the layer grows and reaches a thickness of at least about 1 micrometer; Grow layers.

Diffusion of the dopant implanted in the previous operation continues, p
1 isolation region, p-drain, n” sinker diffusion, and the desired extension of the p-a and node wall regions of the low leakage diode (LLD) structure. Then to completely remove the nitride. Perform a chemical attack and continue it to attack the silicon oxide until the silicon in the interzone compartments covered by a thick layer of field oxide is exposed. Under special conditions free of impurities, the vapor A gate oxide is formed by processing at about 875° C. in the presence of a silicon oxide layer and proceeds to form a layer of about 700 silicon oxides.

The cross-section at the end of such processing is itself shown as in FIG.

As can be seen in the figure, the top isolation p1 diffusion joins with the bottom p isolation diffusion to form the desired separation wall between the various adjacent components being fabricated.

Furthermore, other deep diffusions, namely a sinker n' diffusion in contact with an n' buried layer, a p' contact diffusion with a p buried layer, a p-
The tub region and the wall-like p'anode region of the LLD diode simultaneously expanded until they reached a size that substantially determined the desired spatial arrangement for the deep diffusion region.

The next step is to deposit a layer of polycrystalline silicon approximately 4,500 nm thick from the vapor phase, followed by topping the polysilicon layer with phosphorus and removing the polysilicon from unmasked areas. The masking resist is removed and treated in an oxidizing atmosphere at about 1100° C. for about 20 minutes to form the first layer of polycrystalline silicon (Bottom) on the surface. The first layer or first level of such poly (polycrystalline) is a series of operations in which portions of the first level of such poly are It is called gate poly as long as it is configured as a gate electrode.

In addition to forming the gate electrode of a MoS transistor, the poly 1 may also be used in other zones on the surface of a silicon die, for example to form passive elements such as capacitors and resistors. In fact, by repeating the operations of deposition, doping, masking (apparently using a well-prepared mask) and successive plasma attacks, the use of two levels of poly as armatures is easily reproducible and accurate. positioning a polycrystalline silicon 21if (II poly) on top of the I poly (the surface of which, as mentioned above, has been deliberately oxidized) corresponding to the section in which a capacitor with a capacitance of a certain value is to be formed; is possible.

The gate poly, the I-poly, is preferably doped with phosphorus to obtain a sheet with a resistance of about 30-40 Ω/sheet, while the poly is doped to a lesser extent than the I-poly, and/or the resistance of the sheet is It is advantageous to have a small thickness so that the value is determined to be a larger value, preferably about 80-90 Ω/sheet. Such measures allow increasing the possibilities of choice for designing and forming integrated resistors.

After these operations are completed, the cross-section appears as shown in FIG. 8, and the manufacturing process proceeds to form shallow diffusions corresponding to the "active" areas of the various components.

The new masking operation allows the P-0 MO3 transistor, the drain enhancement region of the N-0 MO3 transistor, the collector enhancement region of the NPN transistor, and the I
The section for forming the n-body region of the base region of the CV PNP 3D transistor is defined. The oxide is attacked until the silicon is exposed in such regions, and then phosphorus is implanted through such regions at 100 KeV, as illustrated in FIG. The total amount of impurities is Q#1016cm
-2, and further heat treatment for diffusion is performed.

After removing the resist mask and reoxidizing the silicon surface in the compartments that were implanted with phosphorus during the previous fabrication operation,
A new masking operation is performed, followed by the body of the N-0 MOS transistor, the reinforcement of the anode contact of the low leakage diode of the base of the NPN transistor, and the P-0
Boron implantation operation and diffusion heat treatment to form enhancement p-regions for source and drain enhancement of MOS transistors, enhancement regions of emitter and collector of ICV PNP 3D transistors and contacts of well-like regions of N-MOS transistors. is performed as shown in FIG. Boron implantation occurs at 80Ke■, approximately Q=
5 x l Q 13(, 1-2 charge amount is obtained.

A new masking operation allows the channels of P-MOS transistors (located between the p drain and source regions and the field oxide adjacent to these regions) to
Many shallow n'' regions associated with the 7par n4al region, enhancements for connection of the body of F'-0MOS transistors, source and drain regions of N-MOS transistors, source and drain enhancements of N-0MOS transistors region, for the formation of the emitter of the NPN transistor, and of the n″ region of the contact associated with the collector of the NPN transistor, and of the ICV PNP
The compartments for the formation of the base of the 3D transistor and the anode and cathode of the LLD diode are limited. The oxide is attacked in a plasma until the silicon is exposed in such a compartment, and then the total impurity concentration per unit Q"' 5 in solid or through said exposed compartment as shown in FIG. 11. X 10 I
50 to obtain a charge amount corresponding to “scm-”.
After implanting arsenic with KeV and removing the masking resist, a heat treatment for diffusion is performed.

Thereafter, approximately 5000
The first layer of silicon oxide is man-thick, and about 5000
Phosphorus and boron doped silicon oxide (commonly PhousphorusBoron 5i) with human thickness
The insulating layer is deposited by depositing a second layer of silicone (known by the abbreviation PBSG from Licon Glass).

A new masking operation confines the section where many electrodes will be formed, leading to plasma attack of the corresponding insulating layer until the unmasked section exposes the underlying silicon through which the electrodes will be formed. Create the desired hole (open the contacts).

A metal layer thereon, preferably At(99%)/5t(I
%) by the sputtering technique and the deposited metal is attacked and completely removed from the unmasked areas by a new masking operation,
By this method various electrodes of different integrated components are formed.

FIG. 12 shows a cross section of the device at this point in the manufacturing process. The various electrodes of the different parts are indicated with conventional distinctive letters.

The manufacturing process further includes a heat treatment to favor the formation of an AI/Si alloy at the interface between the electrode and the silicon, a final insulating layer of phosphorus-doped silicon oxide or an insulating layer of silicon nitride. It is contemplated to open the pad contacts, which are the compartments for the electrical connection of the various conductors of the integrated circuit, by adhesion from the phase and at least by performing further masking operations.

The different regions formed in a single crystal of silicon to form the seven integrated circuit components of the device according to the invention generally have the following properties:

-p-tub region: Dopant boron; 8×1012≦
Q≦2×10 “cm-”;-P-DMOS,P
N-body region dopant dopant in base of NP and drain of N-0MO8; 10I3≦Q≦3 X 10 “cm-”;-N-D
p-region dopant for body of MOS, base of N P N, source and drain of P-MOS and emitter of PNP Boron; 4X1013≦Q≦7 X 10 “cm-2; n” region associated with shallow diffusion - punt Arsenic; 1015≦Q≦1016 cm −”; The values of the physical parameters of regions and layers, and the processing conditions given elsewhere throughout the specification, apply to embodiments of the device of the invention using the described substrate materials. By way of example, reference is intended to particularly preferred conditions and values, which are therefore not intended to limit the invention.

The method of manufacturing a device according to the invention has been described for a particular example in which the integrated circuit includes seven different component protrusions. As already mentioned in connection with the illustration of some embodiments of the use of devices made in accordance with the invention, in many applications it is not required that all seven different components be present in the circuit. , thus the device contemplated by the present invention does not necessarily include a seven-part convex plate, but it differs from the prior art in that it has fewer (and vertical bipolar) elements with separate collectors. a PNP junction transistor, a vertical bipolar-NPN junction transistor or a low leakage diode, and at least a vertical P-MO3 or N-M
OS transistor or vertical N-DMOS or P-DM
It is characterized by including an OS transistor.

[Brief explanation of drawings]

1 to 12 are schematic longitudinal cross-sectional views illustrating the general structure of the device of the invention by sequentially illustrating how different components may be integrated on the same substrate; , FIG. 1 shows the cross section after the first masking operation, FIG. 2 shows the cross section after the second masking operation, FIG. 3 shows the cross section after the third masking operation, and FIG. Figure 4 is
The cross section after the fourth masking operation is shown, and FIG.
FIG. 6 shows a cross section after the sixth masking operation, FIG. 7 shows a cross section with silicon oxide exposed after the sixth masking,
Figure 8 shows a cross section after ■poly formation, Figure 9 shows a cross section during phosphorus implantation, Figure 10 shows a cross section during boron implantation and diffusion heat treatment, and Figure 11 shows arsenic implantation. FIG. 12 shows a cross section during electrode formation.

Claims (1)

Claims: 1. A semiconductor substrate having a plurality of circuit components formed on a single monolithic substrate of semiconductor material and having a low doping level of impurities of a first type of conductivity. and an epitaxial layer with a low doping level of impurities of a second type of conductivity, at least a vertical PNP with a separated collector.
Bipolar junction transistors and vertical NPN bipolar junction transistors and/or low leakage diodes, and at least lateral P-MOS and N-MO
S transistor and vertical N-DMOS and P-DMO
A semiconductor device characterized in that it consists of other components belonging to the group consisting of S transistors. 2. The semiconductor material substrate with a low doping level is boron-doped with a resistance value between 1 and 5 Ω·cm.
^ - A slice of single-crystal silicon in which the epitaxially grown layer has a resistance value between 1 and 3 Ω·cm and a resistance between 9 and 1.
2. A device according to claim 1, wherein the device is antimony-doped n^-silicon with a thickness of between 1 micrometer and the gate electrode of the MOS transistor is polycrystalline silicon. 3. At least the claims contain each appropriate one of the circuit components belonging to the group consisting of vertical NPN and PNP bipolar junction transistors, lateral CMOS transistors and vertical N-DMOS and P-DMOS transistors. The device according to item 1. 4. At least vertical NPN and PNP bipolar junction transistors, low leakage diodes and horizontal CMs
Claim 1 containing each appropriate one of the circuit components belonging to the group consisting of OS transistors
Devices listed in section. 5. Formed on a single substrate, and lateral P-MOS transistor and lateral N-MOS transistor (CMOS
), vertical P-DMOS transistor, vertical N-DMO
A method of manufacturing a semiconductor device comprising a plurality of circuit components belonging to the group consisting of S transistors, vertical NPN transistors, vertical PNP transistors with separated collectors and low leakage junction diodes (LLDs), the method comprising: ) The P-MOS, N-DMOS, P-DMOS,
an n^+ buried layer on a p^- single crystal silicon substrate corresponding to the section where the NPN and PNP transistors and the LLD diode are to be formed; a p silicon buried layer corresponding to the section where the N-MOS transistor is to be formed; ,
and the n corresponding to the section where the P-DMOS and PNP transistors and the LLD diode are formed.
^+ a p-silicon buried layer adapted to rest on the buried layer, and further a bottom isolation region of p-silicon around said buried layer and away from the same epitaxially grown n^-silicon layer; (B) The entire surface of the device is thinly oxidized, and the N-M
(C) depositing a layer of silicon nitride over the active regions of the circuit component being fabricated; D) implanting phosphorus ions for a deep n^+ diffusion to define the section and form a connection region with the n^+ buried layer and an anode shield region of the LLD diode; Boron ions are implanted to define the section and form a deep p^+ diffusion region for forming an upper isolation region, an anode region of the LLD diode, and a connection region with the p silicon buried layer, and (F) nitriding. growing a surface layer of oxide in the areas not covered by the oxide layer to form a thick field oxide isolation structure;
The expansion of the p^-tab region by diffusion is continued until it joins the upper part of the buried layer, and the steps (D) and (E) are continued.
) to diffuse the implanted phosphorus and boron ions and attack the oxide and nitride until the thin layer of nitride and underlying oxide is completely removed, exposing the silicon surface, (G) forming a gate oxide layer on the exposed sections of silicon and forming a first level (gate) of polycrystalline silicon corresponding to at least the sections of gate electrodes of the CMOS and DMOS transistors; (H) defining the section and implanting phosphorus ions into the n-body region of the P-DMOS transistor;
heat treating the base region of the transistor and the drain region of the N-DMOS transistor to diffuse it; (I) defining the section and implanting boron ions; and p-body region of the N-DMOS transistor, the NPN
heat treating to diffuse the base region of the transistor, the source and drain regions of the P-MOS transistor and the emitter region of the PNP transistor; (J) defining the section and implanting arsenic ions;
The N-M of the main body contact of the P-DMOS transistor of the channel stopper of the MOS transistor
of the source and drain regions of the OS transistor, and of the source and contact of the N-MOS transistor, of the emitter of the NPN transistor, of the contact region associated with the collector region of the NPN transistor, and to the base region of the PNP transistor; Said LL
(K) depositing an insulating layer, defining said zones, drilling holes in said insulating layer corresponding to said defined zones; A method comprising forming on the sections electrodes of the sources and drains of said CMOS and DMOS transistors, of the bases, emitters and collectors of said NPN and PNP transistors, and of the anodes and cathodes of said LLD diodes. 6. After step (G) is completed, superficially oxidize the first level of polycrystalline silicon to at least oxidize said first level of superficially oxidized silicon on the sections where passive circuit components are to be formed.
6. The method of claim 5, wherein a second level of polycrystalline silicon is formed on a second level of polycrystalline silicon. 7. Claim 6 in which 14 different masks are utilized as many masking operations to define the section.
The method described in section. 8. The method of claim 5, wherein the p^-silicon substrate is sliced with a resistance of 1 to 5 Ω·cm and crystallographic orientation <100>. 9. The method according to claim 8, wherein the epitaxially grown n^-silicon layer has a resistance value of 1 to 3 Ω·cm. 10. The p^-tub area of silicon is 8 x 10^1^2 and 2 x 10^1^3 cm^-^ per unit section in the solid.
10. The method of claim 9, having a total impurity level between 2. 11. N-DMOS, P-DM formed in step (H)
n corresponding to the active region of the OS and PNP transistor
The silicon area is 1×10^1 per unit area in the solid.
11. The method of claim 10, having a total impurity content between ^3 and 3 x 10^1^3 cm^-^2. 12. N-DMOS, NPN formed in step (I);
The p-silicon region corresponding to the active region of P-MOS and PNP transistors is 4×1 per unit area in the solid.
12. The method of claim 11, having a total impurity level between 0^1^3 and 7x10^1^3 cm^-^2. 13. The n^+ silicon region formed in step (J) is
10^1^5 and 10^1^6c per unit compartment in the solid
13. The method according to claim 12, having a total impurity content between m^-^2.