JPH02124636A - Synchronous circuit - Google Patents

Abstract

PURPOSE:To shorten the holding time of an asynchronous input signal with respect to a clock signal by fetching the asynchronous input signal from the input clock signal at a 1st stage circuit and outputting a signal synchronized with an internal clock signal. CONSTITUTION:The 1st stage logic circuit 6 consists of an AND/NOR gate, to which an asynchronous input signal I and an input clock signal phi are inputted. The asynchronous input signal I is fetched when the input clock signal phiis at a high level, and the 1st stage logic circuit 6 holds and outputs the data at the fall of the input clock signal phi for a period when the input clock signal phi is at a low level. The next stage logic circuit 7 consists of an OR/ NAND gate, which receives the 1st stage output signal the input clock signal phiand the internal clock signal phi2, fetches the 1st stage output for a period when the input clock signal phi is at a low level and the internal clock signal phi2 is at a high level and outputs an output '0' synchronously with the internal clock signal phi2. Thus, the holding time of the asynchronous input signal I with respect to the clock signal is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization circuit, and particularly to a synchronization circuit that synchronizes an asynchronous input signal using a clock signal in an asynchronous input circuit of an LSI.

[Conventional technology]

FIG. 6 is a circuit diagram showing an example of a conventional synchronization circuit, and FIG.
The figure is a time chart of FIG. 6.

Based on the input clock signal φ, the internal clock generation circuit 9 generates non-overlapping two-phase internal clocks φ1. φ2 is created. The first stage logic circuit 6 receives an asynchronous input circuit and an internal clock φl, takes in data while the internal clock φ1 is at a high level, and holds the data after falling.

The next-stage logic circuit 7 receives the output of the first-stage logic circuit 6 and the internal clock φ23, and outputs a synchronized output signal “0” in synchronization with the rising edge of the internal clock φ2.

[Problem to be solved by the invention]

The conventional synchronization circuit described above uses internal clocks φl and φ2 in the first stage and the next stage, and as shown in the timing diagram of FIG. 7, the internal clock φ□ has a delay time of 11 from the input clock signal 1. , the hold time 10 of the asynchronous input signal I with respect to the clock signal equal to this delay time
In order to reduce this hold time, a delay circuit must be placed between the asynchronous input terminal of the LSI and the input of the synchronization circuit.

[Means to solve the problem]

The synchronization circuit of the present invention includes a first-stage logic circuit to which an asynchronous input signal and an input clock signal are input, and an output signal of the first-stage logic circuit, an input clock signal, and a non-overlapping two-phase internal clock signal generated from the input clock signal. It has a next-stage logic circuit for input.

〔Example〕

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
This is a time chart of the figure. The first stage logic circuit 6 is AND
- It is constituted by a NOR gate, and an asynchronous input signal I and an input clock signal φ are input thereto. The asynchronous signal I is taken in during the high level period of the input clock signal φ, and the first stage logic circuit 6 holds and outputs the data at the falling edge of the input clock signal φ during the low level period of the input clock signal φ.

The next stage logic circuit 7 is constituted by an OR-NAND gate, and receives the first stage output signal, input clock signal φ, and internal clock signal φ2. The next stage logic circuit 7 takes in the first stage output during the period when the input clock signal φ is at a low level and the internal clock signal φ2 is at a high level, and outputs an output "0" in synchronization with the internal clock signal φ2.

Further, FIG. 4 is a circuit diagram showing a second embodiment of a synchronization circuit that outputs a signal synchronized with the internal clock signal φ1.

FIG. 3 is a circuit diagram of a third embodiment of the present invention.

The first stage logic circuit 6 is composed of a transfer gate and an inverter, and receives an asynchronous input terminal and an input clock signal φ. During the period when the input clock signal φ is at a high level, the first stage logic circuit 6 opens the transfer gate 21, takes in the asynchronous input signal ■, holds the data after the fall of the input clock signal φ, and outputs the data.

The next stage logic circuit 7 is composed of a transfer gate, an inverter, and a NOR gate, and receives the above-mentioned first stage output signal, input clock signal φ, and internal clock signal φ2. In the next stage logic circuit, the transfer gate 22 is opened while the input clock signal φ is at a low level and the internal clock signal φ2 is at a high level, takes in the above-mentioned first stage output, and outputs an output signal "0" synchronized with the internal clock signal φ2. " is output.

Further, FIG. 5 is a circuit diagram showing a fourth embodiment of a synchronization circuit that outputs a signal synchronized with the internal clock signal φl.

〔Effect of the invention〕

As explained above, the present invention takes in an asynchronous input signal using an input clock signal in the first stage circuit, and outputs a signal synchronized with the internal clock signal using the input clock signal and the internal clock signal in the second stage circuit. By doing so, the hold time of the asynchronous input signal with respect to the clock signal can be reduced, and there is no need for a delay circuit between the input terminal of the LSI and the synchronization circuit to reduce the hold time, and the hold time caused by using the delay circuit can be reduced. This has the effect of reducing fluctuations in time due to power supply voltage and ambient temperature of the LSI.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a time chart of FIG. 1, FIG. 3 is a circuit diagram of a third embodiment of the present invention, and FIG. A circuit diagram showing a second embodiment synchronized with the internal clock φ1 with the same configuration as the embodiment of
FIG. 5 shows a configuration similar to that of the third embodiment using an internal clock φ1.
FIG. 6 is a circuit diagram of a conventional example, and FIG. 7 is a time chart of FIG. 6. 6...First stage logic circuit, 7...Next stage logic circuit, 8...
- LSI in which a synchronization circuit is used, 9... Internal clock generation circuit, 10... Hold time of asynchronous input signal with respect to input clock signal, 11... Delay time from input clock signal to internal clock signal -21,2
2...Transfer gate, φ...Input clock signal, φ1. φ2...Internal clock signal, ■...Asynchronous input signal, O...Synchronized output signal.

Claims (1)

[Claims] In an asynchronous input circuit of an LSI, an asynchronous input signal and an input clock signal are input to the first stage logic circuit of the asynchronous input circuit, and a signal is generated inside the LSI from the output signal of the first stage logic circuit, the input clock signal, and the input clock signal. A synchronization circuit having a next-stage logic circuit to which a non-overlapping two-phase internal clock signal is input.