JP2000293985A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which stage division can be performed optimally in a wide frequency band while increasing speed of data output. SOLUTION: In a semiconductor memory provided with a memory cell, a read-amplifier 4a amplifying data transferred to a data bus when data from a memory cell is read out, and an output buffer for outputting output data amplified by the read-amplifier 4a to an output terminal, starting a read- amplifier is controlled by responding to a clock edge prescribing a data output of an external clock signal. In this constitution, operation of a core circuit 3 transferring data to a data bus can be separated from operation of a data output circuit including a read-amplifier, and division of an operation time can be optimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a dynamic random access memory.

[0002]

2. Description of the Related Art In recent years, there has been an increasing need for high-speed data transfer technology in semiconductor memory devices. In particular, various architectures and circuits have been proposed to shorten the access time.

A conventional semiconductor memory device will be described below.

FIG. 3 is a block diagram showing a main configuration of a conventional semiconductor memory device. In FIG. 3, reference numeral 1 designates an external clock signal CLK, and internally receives clocks CLK1 and C1.
A clock generation circuit for generating LK2, an address decode circuit 2 for taking in and decoding an external address signal in synchronization with the internal clock CLK1, 2a an address buffer, 2b a core address decoder, and 2c a peripheral address decoder. 3 is a core circuit including a memory cell, a sense amplifier, etc., 4 is a data transfer circuit for outputting data from the memory cell, and 4a is a data bus pair DL, X
A read amplifier for amplifying DL data, 4b is data D
This is an output buffer circuit for outputting Q.

[0005] The data read operation of the conventional semiconductor memory device configured as described above will be described with reference to FIG. When a read command is input as a command, the internal clock CLK1 is generated by the clock generation circuit 1 from the external clock CLK, and the internal clock CL is generated.
The address is fetched by K1. After the address is fetched, the data is transferred to the output buffer circuit 4b by sequentially operating with the address decode circuit 2, the core circuit 3, and the read amplifier 4a based on the internal clock CLK1. After that, the output buffer circuit 4b is activated by the internal clock CLK2 generated through the clock generation circuit 1 from the clock edge defining the data output of the external clock CLK, and the data DQ is output.

[0006]

However, in the conventional configuration, the digital operation time of the latch circuit and the buffer circuit of the data output stage is shorter than the analog operation time of the core circuit and the data transfer circuit. Makes optimization difficult.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor memory device which can optimally divide a stage in a wide frequency band while speeding up data output.

[0008]

In order to solve this problem, a semiconductor memory device according to the present invention is a semiconductor memory device which operates in synchronization with an external clock signal, and comprises a memory cell and a memory cell. A read amplifier that amplifies the data transferred to the data bus when reading data; and an output buffer for outputting the output data amplified by the read amplifier to an output terminal, and defines the data output of the external clock signal. The read amplifier is activated in response to a clock edge.

With this configuration, when reading data,
The operation of the core circuit from address input to the transfer of data to the data bus can be separated from the operation of the data output circuit including the read amplifier that amplifies the data on the data bus. can do. Further, by synchronizing the read amplifier with an external clock, a margin can be provided for the analog operation at the time of data transfer depending on the frequency, and particularly, at a low frequency, data transfer with a larger margin can be performed.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a main configuration of a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device of the present embodiment is, for example, a clock synchronous type D
RAM. In FIG. 1, 1 is an external clock signal C
A clock generation circuit for taking in LK and internally generating clocks CLK1 and CLK2, an address decoding circuit 2 for taking in and decoding an external address signal in synchronization with the internal clock CLK1, and 2a an address buffer, 2a
b is a core address decoder and 2c is a peripheral address decoder. 3 is a core circuit including a memory cell, a sense amplifier, etc., 4 is a data transfer circuit for outputting data from the memory cell, 4a is a read amplifier for amplifying data of the data bus pair DL and XDL, and 4b is data DQ Is an output buffer circuit for outputting. Internal clock CL
K2 is input to the read amplifier 4a.

The data read operation of the semiconductor memory device configured as described above will be described below with reference to FIG.

In the data read operation, the operation of transferring data from the address input to the data bus pair DL, XDL which is the input of the read amplifier 4a is the same as in the conventional example. Thereafter, the read amplifier 4a outputs the internal clock CL generated by the clock generation circuit 1 from the clock edge (the second rising edge from the left in FIG. 2) that defines the data output of the external clock CLK.
Activated in synchronization with K2. In response to the activation of the read amplifier 4a, data transferred from the core circuit 3 to the data bus is output by sequential processing for generating a control signal for the output buffer circuit 4b.

As described above, during the data read operation,
The operation of the core circuit from the input of an address until the data is transferred to the data bus can be separated from the operation of the data output circuit including the read amplifier that amplifies the data on the data bus. I have to. Also, by synchronizing the read amplifier with an external clock,
There is a margin in the analog operation at the time of data transfer depending on the frequency, and particularly at a low frequency, data transfer with a larger margin can be performed.

[0015]

As described above, according to the present invention, the read amplifier is controlled in synchronization with the external clock that defines the output,
An excellent semiconductor memory device that can optimally divide a stage in a wide frequency band while increasing the data output speed can be provided by a configuration in which subsequent output circuits are sequentially controlled.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating a data read operation of the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a block diagram showing a main configuration of a conventional semiconductor memory device;

FIG. 4 is a timing chart illustrating a data read operation of a conventional semiconductor memory device;

[Explanation of symbols]

 Reference Signs List 1 clock generation circuit 2 address decode circuit 3 core circuit 4 data transfer circuit 4a read amplifier 4b output buffer circuit

Claims (1)

[Claims] 1. A semiconductor memory device operating in synchronization with an external clock signal, comprising: a memory cell; a read amplifier for amplifying data transferred to a data bus when reading data from the memory cell; An output buffer for outputting the output data amplified by the read amplifier to an output terminal, wherein the read amplifier is activated in response to a clock edge defining the data output of the external clock signal. Semiconductor storage device.