JPH02122642A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH02122642A JPH02122642A JP63277857A JP27785788A JPH02122642A JP H02122642 A JPH02122642 A JP H02122642A JP 63277857 A JP63277857 A JP 63277857A JP 27785788 A JP27785788 A JP 27785788A JP H02122642 A JPH02122642 A JP H02122642A
- Authority
- JP
- Japan
- Prior art keywords
- sealing resin
- pad
- external lead
- coupling wiring
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000011347 resin Substances 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 230000008878 coupling Effects 0.000 claims abstract description 21
- 238000010168 coupling process Methods 0.000 claims abstract description 21
- 238000005859 coupling reaction Methods 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 claims abstract description 21
- 239000008188 pellet Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000002344 surface layer Substances 0.000 abstract description 2
- 238000007740 vapor deposition Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.
従来の樹脂封止型半導体装置は第３図（ａ）（ｂ）に示
す様に、アイランド２に搭載された半導体ペレット３の
パッド７と外部リード１をワイヤ１０にて接合し、封止
樹脂１１にて封止された構造が一般的であった。As shown in FIGS. 3(a) and 3(b), the conventional resin-sealed semiconductor device connects the pad 7 of the semiconductor pellet 3 mounted on the island 2 and the external lead 1 with a wire 10, and A structure sealed at 11 was common.
上述した従来の樹脂封止型半導体装置は、ワイヤ１０に
てパッド７と外部リード１とを対向させて結合している
が、直線的にしか配線できないため、バット及び外部リ
ード形成の為の自由度が小さくなるという欠点があった
。さらに、ワイヤ１０は一本ずつしか結合できないとい
う欠点があった。In the conventional resin-sealed semiconductor device described above, the pad 7 and the external lead 1 are connected by the wire 10 so as to face each other, but since wiring can only be done in a straight line, there is no freedom for forming the butt and the external lead. There was a drawback that the degree was small. Furthermore, there is a drawback that the wires 10 can only be connected one by one.
本発明の樹脂封止型半導体装置は、外部リードと、アイ
ランドに固着された半導体ペレットと、前記外部リード
と半導体ペレット上のパッドとを結合する結合配線と、
前記半導体ペレットと結合配線と外部リードの一部とを
樹脂封止してなる樹脂封止型半導体装置において、前記
結合配線は封止樹脂の溝中に堆積された導体により形成
されているものである。A resin-sealed semiconductor device of the present invention includes an external lead, a semiconductor pellet fixed to an island, and a coupling wiring that couples the external lead and a pad on the semiconductor pellet.
In the resin-sealed semiconductor device in which the semiconductor pellet, the coupling wiring, and a part of the external lead are sealed with resin, the coupling wiring is formed of a conductor deposited in a groove of the sealing resin. be.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第１図において樹脂封止型半導体装置は、外部リード１
と、アイランド２に固着された半導体ペレット３と、こ
の半導体ペレット３上のパッド７と外部リード１とを結
合する結合配線４と、内部封止樹脂５と外部封止樹脂６
とから主に構成されており、そして、特に結合配線４は
内部封止樹脂５の溝中に堆積された金やアルミニウム等
の金属膜から形成されている。以下第２図を併用してそ
の製造方法を説明する。In FIG. 1, the resin-sealed semiconductor device has an external lead 1
, a semiconductor pellet 3 fixed to the island 2, a coupling wiring 4 that couples the pad 7 on the semiconductor pellet 3 and the external lead 1, an inner sealing resin 5 and an outer sealing resin 6.
In particular, the coupling wiring 4 is formed from a metal film such as gold or aluminum deposited in the groove of the internal sealing resin 5. The manufacturing method will be described below with reference to FIG.
まず第２図（ａ＞に示すように、半導体ペレット３をリ
ードフレームのアイランド２上に固着したのち、アイラ
ンド２、半導体ペレット３及び外部リード１の先端部を
ポリイミド等の内部封止樹脂５を用いて封止する。First, as shown in FIG. 2 (a), the semiconductor pellet 3 is fixed onto the island 2 of the lead frame, and then the island 2, the semiconductor pellet 3, and the tips of the external leads 1 are covered with an internal sealing resin 5 such as polyimide. Use to seal.
次に第２図（ｂ）に示すように、例えばレーザ光を用い
て内部封止樹脂６をエツチングし、外部リード１の先端
部とパッド７の表面を露出する溝８を形成する。Next, as shown in FIG. 2(b), the internal sealing resin 6 is etched using, for example, a laser beam to form a groove 8 that exposes the tip of the external lead 1 and the surface of the pad 7.
次に第２図（Ｃ）に示すように、溝８内を覆う金やアル
ミニウムからなる金属膜４Ａを蒸着法等により形成する
。Next, as shown in FIG. 2(C), a metal film 4A made of gold or aluminum is formed by vapor deposition or the like to cover the inside of the groove 8.
次に第２図（ｄ）に示すように、内部封止樹脂らの表面
層を砥石等により研削除去する。この操作により外部リ
ード１の先端部とパッド７を接続する結合配線４が形成
される。Next, as shown in FIG. 2(d), the surface layer of the internal sealing resin is ground away using a grindstone or the like. By this operation, the coupling wire 4 connecting the tip of the external lead 1 and the pad 7 is formed.
次に第１図に示すように、結合配線４を含む内部封止樹
脂５の周囲を外部封止樹脂６により封止し、樹脂封止型
半導体装置を完成させる。Next, as shown in FIG. 1, the periphery of the internal sealing resin 5 including the coupling wiring 4 is sealed with an external sealing resin 6, thereby completing a resin-sealed semiconductor device.
このように本実施例によれば、外部リード１とパッド７
とを結合する結合配線４は、内部封止樹脂５に形成され
た溝中に形成されるため、結合配線を非直線的に形成す
ることができる。従って外部リードとパッドの位置は特
に対向させる必要がなくなるため、外部リードとパッド
の設計の自由度は大きくなる。In this way, according to this embodiment, the external lead 1 and the pad 7
Since the coupling wiring 4 that couples the two is formed in the groove formed in the internal sealing resin 5, the coupling wiring can be formed non-linearly. Therefore, there is no need for the external leads and pads to be particularly opposed to each other, and the degree of freedom in designing the external leads and pads is increased.
以上説明したように発明は、外部リードと半導体ペレッ
トのパッドを結合する結合配線を、封止樹脂の溝中に堆
積された導体により形成することにより、結合配線を非
直線的に形成できるため、外部リードとパッドの設計の
自由度を大きくできるという効果がある。更に外部リー
ドとパッドとの結合配線を同時に形成できるという効果
もある。As explained above, in the present invention, by forming the coupling wiring that couples the external lead and the pad of the semiconductor pellet with a conductor deposited in the groove of the sealing resin, the coupling wiring can be formed non-linearly. This has the effect of increasing the degree of freedom in designing external leads and pads. Furthermore, there is also the advantage that coupling wiring between external leads and pads can be formed at the same time.
第１図は本発明の一実施例の断面図、第２図（ａ）〜（
ｄ）は本発明の一実施例の製造方法を説明する為の半導
体チップの断面図、第３図（ａ）、（ｂ）は従来例の平
面図及びＡ−Ａ’線断面図である。
１・・・外部リード、２・・・アイランド、３・・・半
導体ペレット、４・・・結合配線、５・・・内部封止樹
脂、６・・・外部封止樹脂、７・・・パッド、８・・・
溝、１０・・・ワイヤ、１１・・・封止樹脂。
代雇人弁理士内原 晋
昂１FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2(a) to (
d) is a sectional view of a semiconductor chip for explaining a manufacturing method according to an embodiment of the present invention, and FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along line AA' of a conventional example. DESCRIPTION OF SYMBOLS 1... External lead, 2... Island, 3... Semiconductor pellet, 4... Coupling wiring, 5... Internal sealing resin, 6... External sealing resin, 7... Pad , 8...
Groove, 10... wire, 11... sealing resin. Representative Patent Attorney Shinko Uchihara 1
Claims (1)
トと、前記外部リードと半導体ペレット上のパッドとを
結合する結合配線と、前記半導体ペレットと結合配線と
外部リードの一部とを樹脂封止してなる樹脂封止型半導
体装置において、前記結合配線は封止樹脂の溝中に堆積
された導体により形成されていることを特徴とする樹脂
封止型半導体装置。An external lead, a semiconductor pellet fixed to the island, a coupling wiring that couples the external lead to a pad on the semiconductor pellet, and a resin seal between the semiconductor pellet, the coupling wiring, and a part of the external lead. A resin-sealed semiconductor device, wherein the coupling wiring is formed of a conductor deposited in a groove of a sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63277857A JPH02122642A (en) | 1988-11-01 | 1988-11-01 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63277857A JPH02122642A (en) | 1988-11-01 | 1988-11-01 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02122642A true JPH02122642A (en) | 1990-05-10 |
Family
ID=17589248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63277857A Pending JPH02122642A (en) | 1988-11-01 | 1988-11-01 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02122642A (en) |
-
1988
- 1988-11-01 JP JP63277857A patent/JPH02122642A/en active Pending
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