JPH02122440U - - Google Patents
Info
- Publication number
- JPH02122440U JPH02122440U JP3152989U JP3152989U JPH02122440U JP H02122440 U JPH02122440 U JP H02122440U JP 3152989 U JP3152989 U JP 3152989U JP 3152989 U JP3152989 U JP 3152989U JP H02122440 U JPH02122440 U JP H02122440U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- frame
- lead frame
- view
- shaped clamper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Description
第1図は本考案に用いるクランパの斜視図、第
2図はクランパの断面図、第3図は使用状態を示
す断面図、第4図は他の実施例を示す断面図、第
5図はハイブリツドICの平面図、第6図はハイ
ブリツドICの断面図、第7図は一般的なボンデ
イングツールの要部断面図、第8図は従来の改良
型ボンデイング装置の平面図、第9図及び第10
図は従来のリードフレームの温度分布図である。 1……リードフレーム、2……アイランド部、
4……配線基板、6……電子部品、13……ヒー
タブロツク、20……クランパ、21……加熱手
段。
2図はクランパの断面図、第3図は使用状態を示
す断面図、第4図は他の実施例を示す断面図、第
5図はハイブリツドICの平面図、第6図はハイ
ブリツドICの断面図、第7図は一般的なボンデ
イングツールの要部断面図、第8図は従来の改良
型ボンデイング装置の平面図、第9図及び第10
図は従来のリードフレームの温度分布図である。 1……リードフレーム、2……アイランド部、
4……配線基板、6……電子部品、13……ヒー
タブロツク、20……クランパ、21……加熱手
段。
Claims (1)
- リードフレームのアイランド部に配線基板を介
して複数の電子部品をマウントし、リードフレー
ムの外部リードを枠状のクランパでヒータブロツ
クへ押圧して配線基板上の要部をワイヤボンデイ
ングする装置において、前記枠状のクランパに加
熱手段を付設したことを特徴とする半導体製造装
置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3152989U JPH02122440U (ja) | 1989-03-20 | 1989-03-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3152989U JPH02122440U (ja) | 1989-03-20 | 1989-03-20 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02122440U true JPH02122440U (ja) | 1990-10-08 |
Family
ID=31257445
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3152989U Pending JPH02122440U (ja) | 1989-03-20 | 1989-03-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02122440U (ja) |
-
1989
- 1989-03-20 JP JP3152989U patent/JPH02122440U/ja active Pending