JPH02117175A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the withstand voltage of an MIOS semiconductor memory by providing the first region touching the end section of a channel region directly, and the second region touching the first region and having impurity density higher than that of the first region. CONSTITUTION:N<+> diffusion regions 7, 8 and N<-> diffusion regions 9, 10 are formed in a P-type silicon substrate 1; thin silicon oxide film 4 is provided spreading over the N<-> diffusion regions 9, 10; a silicon nitride film 5 and a gate electrode 6 are laminated on the thin silicon oxide film 4 in this order; and besides lateral wall films 11 made from silicon oxide films are provided at the sides of the gate section. This constitution lightens the electric field concentration in the channel regions in the vicinities of the drain and source regions of MIOS semiconductor memories, and makes it possible to enhance the voltage-withstanding characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to MIO8 (metal-insulating film-silicon oxide film-
The present invention relates to a semiconductor memory device comprising a semiconductor type field effect transistor, and particularly to a novel structure capable of improving its reliability.

(Prior art) In the MIO8 type semiconductor memory device, there is a gap between the gate and the substrate of 20 to
Applying a high voltage of about 25 V to the trap level in the insulating film at or near the interface between the silicon oxide film and the insulating film,
Information is stored by injecting charge from the semiconductor side and increasing the volume to change the threshold voltage of the transistor.

Conventionally, a semiconductor memory device having an MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) structure as shown in FIG. 3 is well known as a typical MIO8 type semiconductor memory device. 1 is a P-type silicon substrate, 2 and 3 are source and drain regions.

4 is a thin silicon oxide film, and 5 is a silicon nitride film.

6 is a gate electrode. MNO8 with structure as shown in Figure 3
In a type semiconductor memory device, a thin silicon oxide film 4 is spread over the entire portion facing and in contact with a channel region sandwiched between a source region 2 and a drain region 3, and its thickness is usually equal to that of a charge tunnel region. In order to make it easier to wake up, we have kept the number of participants small, about 20 people. The thickness of the silicon nitride film 5 on the thin silicon oxide film 4 is set at 300 V so that writing and erasing can be performed at a voltage of 20 to 25 V.
There are only about 500 people, which is a small number compared to the Philippines.

(Problems to be Solved by the Invention) Therefore, in an MNO8 type semiconductor memory device with a conventional configuration, when the gate is Ov and a high voltage of 20 to 25 V is applied to the drain, the electric field between the gate electrode and the drain is
This greatly affects the electric field between the drain and substrate, causing electric field concentration in the channel region near the drain region, causing
There are problems in that breakdown occurs between the substrates and the thin oxide film on the area is easily destroyed, which is an obstacle in circuit design.

SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide a novel structure that can improve the withstand voltage of an MNOS type semiconductor memory device.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides - a thin film that serves as a tunneling medium on a channel region sandwiched between a source region and a drain region provided in a conductive type semiconductor substrate; In a semiconductor memory device having a gate structure including a silicon oxide film, an insulating film on the thin silicon oxide film, and a gate electrode on the insulating film, a sidewall film made of an insulating film is provided on a side surface of the gate structure. At least one of the source region and the drain region includes a first region in which liquid is directly applied to an end of the channel region, and a first region located away from the channel region and in contact with the first region and having an impurity concentration. The second region is higher than the first region.

(Function) According to this configuration, the end of the gate insulating film, which is made up of a thin silicon oxide film as a tunnel region and an insulating film as a region for trapping tunneled charges, is covered by the insulating film on the sidewall. The electric field between the gate electrode and the source and drain can be relaxed, and since the source and drain regions are formed with two types of diffusion regions: low concentration and high concentration, it is possible to improve the diffusion breakdown voltage.
Compared to the conventional structure, the electric field concentration in the channel region near the source and drain regions can be alleviated, and the withstand voltage characteristics are improved to the conventional structure (15
-20V) can be improved by 10 to 15V.

(Embodiment) A semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG.

This is the N+ diffusion region 7, 8 in the P type silicon substrate 1.
．． N″′ diffusion regions 9, 10 are formed, and N− diffusion regions 9
, 10 is provided with a thin silicon oxide film 4,
It has a structure in which silicon nitride@5 and a gate electrode 6 are sequentially laminated on a thin silicon oxide film 4, and a sidewall film 11 made of a silicon oxide film is further provided on the side surface of the gate portion.

Next, FIG. 2 shows an example of a manufacturing method for realizing the structure shown in FIG. 1.

First, as shown in FIG. 2(A), P-type silicon wall plate 1
After forming a silicon oxide film 12 to a thickness of 500 mm over the entire surface and further forming a silicon nitride film 13 of about 1,200 thickness, predetermined portions are etched using a known photoetching technique for element isolation.

Next, as shown in FIG. 2(B), a field oxide film 14 is formed to an IP level by a normal thermal oxidation method.

Next, as shown in FIG. 2(C), the silicon nitride film 13
After the silicon oxide film 12 thereunder is sequentially removed by etching, the silicon oxide film 4 is oxidized at 800° C. in an oxygen atmosphere to form a thin silicon oxide film 4 having a thickness of about 20 layers.

Next, as shown in FIG. 2(D), a silicon oxide film 4 is formed.
On top, silane (S i H4) and ammonia (NH,)
A silicon nitride film 5 is grown using a vapor phase growth method based on a chemical reaction.
form. In this example, a silicon nitride film 5 was formed to a thickness of 500 nm under the conditions of a growth temperature of 750° C. and a gas flow rate ratio of NHs/S x H4 = 100.Then, the entire surface was doped with phosphorus (approximately 2 XIO"an-")
A polysilicon film 15 is formed by about 4,000 layers, and then a polysilicon film 15 is formed, leaving only the portion that can become a gate.
, the silicon nitride film 5 and the silicon oxide film 4 are patterned by a known photoetching technique using a photoresist, and then phosphorous ions are implanted using the polysilicon film 15 and the field oxide film 14 as masks (50%
keV, 1XIO"cm-"), N-diffusion regions 9, 10
form.

Next, as shown in FIG. 2(E), a silicon oxide film 16 is formed on the entire surface by a vapor phase growth method based on a chemical reaction between SiH, (J2 gas and N, O gas.) N
, O/SiH, Cff, approximately 3000 people were formed under conditions of = 2,900°C.

Next, as shown in FIG. 2(F), a portion of the silicon oxide film 16 remains as a sidewall on the side surface of the gate portion.
In this embodiment, the silicon oxide film 16 is removed by a known anisotropic etching technique. Next, the N'' diffusion region 7.8 is etched by anisotropic etching using a mixed gas of Freon gas and oxygen gas. Arsenic ions were implanted using a photoresist as a mask (40keV, 2XIO”
am-”) to form.

Next, as shown in FIG. 2(G), a silicon oxide film 17 is deposited on the entire surface by a known vapor phase growth method, and then in order to push in the source and drain and to densify the silicon oxide film 17, Heat treatment is performed at 1000° C. for 20 minutes in an N2 atmosphere. Finally, a contact hole is opened using a known photoetching technique, and an aluminum electrode 18 is formed, thereby producing an MNO8 type semiconductor memory device as shown in FIG. 2(G).

In this embodiment, a method was shown in which the N0 diffusion regions 7 and 8 were formed using photoresist as a mask. However, in another embodiment, if the formation conditions of the sidewall film are appropriately selected, self-aligned formation can be achieved using the sidewall film as a mask. can be formed into

In addition, in this embodiment, as an MIO3 type semiconductor memory device, M
Although we have described the case of NOS type semiconductor memory devices, MONO in which a silicon nitride film is oxidized as a gate insulating film
An 8 (metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor) structure may also be used, and in place of the silicon nitride film, for example, aluminum oxide<Aa2oz) may be used.
It goes without saying that a high dielectric constant film such as tantalum oxide (T am Oz ) may also be used.

(Effects of the Invention) As is clear from the above description, according to the present invention, electric field concentration in the channel region near the input and source regions of the MIO8IO8 type semiconductor memory device is alleviated, and the withstand voltage characteristics are improved. This makes it possible to greatly contribute to the reliability of MIO8IO8 type semiconductor memory devices.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the structure of an MNO8 type semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing a method for manufacturing the same semiconductor memory device, and FIG. FIG. 2 is a cross-sectional view showing the configuration of a storage device. 1...P-type silicon substrate, 4...Thin silicon oxide film, 5...Silicon nitride film. 6...Gate electrode, 7,8...No diffusion region, 9,10...N- diffusion region, 11...Side wall silicon oxide film. Patent applicant Matsushita Electronics Co., Ltd. Figure 1 1... 4... 5... 6... 7.8... 9.10... 11... P-type silicon production record Chemical silicon phosphorescent silicon probe electrode 2.3...Source 8 to U/Drain @44 Thinness 1 change silicon 5 ,...Q silicon waist 6... Kate ton pole

Claims (1)

[Claims] A thin silicon oxide film that can serve as a tunneling medium is provided on a source region and a drain region provided in a semiconductor substrate of one conductivity type, and on a channel region, an insulating film is provided on the thin silicon oxide film, and the insulating film is provided on the thin silicon oxide film. In a semiconductor memory device having a gate structure having a gate electrode thereon, a sidewall film made of an insulating film is provided on a side surface of the gate structure, and at least one of the source region and the drain region is located at an end of the channel region. and a second region located away from the channel region, in contact with the first region, and having an impurity concentration higher than that of the first region. semiconductor storage device.